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Mingyuan Yu, Ting Li, Jiaqi Yang, Shuangshuang Zhang, Fujiang Lin, Lin He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process[J]. Journal of Semiconductors, 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005
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M Y Yu, T Li, J Q Yang, S S Zhang, F J Lin, L He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process[J]. J. Semicond., 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005.
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A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process
DOI: 10.1088/1674-4926/37/7/075005
More Information
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Abstract
This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2.-
Keywords:
- SAR ADC,
- low power,
- high speed,
- subrange,
- modified SAR logic
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References
[1] Pang W Y, Wang C S, Chang Y K, et al. A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications. IEEE A-SSCC, 2009:149[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] -
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