1. Introduction
NOR flash memory, known for its high reliability and fast random access, has become a critical component in IoT, 5G, automotive electronics, and aerospace applications. As semiconductor technology advances, the scaling of NOR flash to the 50 nm node represents the cutting edge of non-volatile memory technology. This node not only enables higher integration density and faster performance but also meets the rigorous demands of modern applications, such as real-time processing and extreme environmental conditions. However, this technological progression intensifies a critical commercialization barrier: dielectric reliability degradation. Key parameters for evaluating NOR flash memory include data retention[1, 2], cell anti-breakdown capability[3−5], and resistance to ionizing radiation[6−8]. Scaling down induced failures, particularly dielectric burnout, transition reliability challenges from purely technical challenges to determinants of commercial viability. In automotive and aerospace industries that require defect-free certification, even marginal yield reductions escalate production costs exponentially. This directly undermines the cost-performance benefits enabled by node scaling.
Fig. 1(a) illustrates the schematic structure of a NOR flash cell, consisting of monocrystalline silicon (AA), tunnel oxide, polycrystalline silicon (floating gate, FG), ONO (oxide, nitride, oxide), and polycrystalline silicon (control gate, CG). The reliability challenges stem from the intrinsic physical mechanisms of NOR flash operations. Programming and erasing (P/E) cycles require high electric fields to impart sufficient energy for electrons to enter or escape the floating gate[9], through two established mechanisms: Fowler-Nordheim tunneling during erasing and Channel Hot Electron Injection during programming[10−12].
As the technology node scales toward 50 nm, the progressive reduction in FG thickness and width necessitates compensatory increases in cell-open depth. This geometric scaling reduces the control gate-to-active area (CG-AA) distance, as shown in Fig. 1(b)[13]. According to the JEDEC standard, NOR flash memory must sustain over 100,000 P/E cycles. Our TCAD simulations reveal intensified electric field concentrations at AA top corners and CG bottom corners during P/E cycling, particularly under erase operations due to nearly double the CG-AA bias compared to programming[3, 14]. Transmission electron microscopy (TEM) in Fig. 1(c) confirms severe profile damage predominantly at these regions, making them the primary failure sites during cycling burn-in tests. While previous studies for improvement of reliability predominantly focused on process-level optimizations, including interface engineering[1, 4], defect reduction[3], and recipe refinement[5] to improve data retention and leakage control, these approaches all encounter inherent structural limitations when scaling down to advanced nodes, which are insufficient to support the 50 nm node reliability requirement.
This study introduces a high-reliability NOR flash cell design optimized for the 50 nm technology node. By carefully adjusting key structural parameters such as floating gate thickness, width, and cell-open depth, the CG-AA corner distance is significantly increased, reducing electric field concentrations and mitigating burnout issues. Importantly, these enhancements are achieved without sacrificing P/E speed or data retention performance. The proposed design reduces the early-cycle CG-AA burnout failure rate from 1000 ppm to below 10 ppm, representing a major advancement in reliability. Compared with existing approaches focusing on data retention [3−8], our work pioneers simultaneous optimization of anti-breakdown capability and operational performance through structural control. This breakthrough not only addresses critical challenges in scaling NOR flash but also ensures its competitiveness in high-reliability markets, paving the way for broader commercialization.
2. Simulations and experiment
2.1 Experimental optimization
Based on TCAD simulation and TEM analysis of the 50 nm NOR flash cell structure, it can be indentified that the CG-AA interface is the most vulnerable region under cycling stress. To perform reliability optimization, we first fabricated a conventional 50nm NOR flash cell (C1), using a standard semiconductor manufacturing process. First, the cell active area (CAA) pattern was defined through CAA etching process, followed by shallow trench isolation (STI) to electrically isolate adjacent cells. Next, deep N-Well and standard high-voltage well were formed through ion implantation process. Subsequently, the tunnel oxide layer was grown using in-situ steam generation (ISSG) to achieve superior uniformity and quality, and FG was deposited via plasma-enhanced chemical vapor deposition. The inter-poly dielectric (IPD), consisting of an ONO stack, and CG were sequentially deposited using low-pressure chemical vapor deposition. Finally, the contact loop and back-end-of-line (BEOL) layers were fabricated using conventional processes to establish interconnection and enable package.
To improve reliability and mitigate CG-AA interface degradation, we implemented two major process changes through adjustments to STI etch and cell-open etch steps. A 40% reduction in STI etch time enhances FG thickness and reduces FG width, while a 43% extension of cell-open loop etch time achieves enlarged cell-open depth. These targeted structural optimizations yield the new C2 structure. Fig. 2(a) and Fig. 2(b) illustrate the detailed structural differences between the C1 and C2 designs, highlighting the enhancements achieved through structural optimizations. Compared to the original design, the C2 structure exhibited significant improvements in critical dimensions, including increasing the FG thickness by 23.5%, reducing the FG width by 7.4%, and increasing the cell-open depth by 7.6%, as shown in Table 1. Combining these parameters, the CG-AA corner distance has increased from 37.4 nm to 45.7 nm, which theoretically allows for higher voltage and improved reliability of the NOR flash cell.
Parameter | C1 (old) | C2 (new) | Difference |
FG thickness (nm) | 58.7 | 72.5 | 23.5% |
FG width (nm) | 72.9 | 67.5 | −7.4% |
Cell-open depth (nm) | 59.2 | 63.7 | 7.6% |
CG-AA corner distance (nm) | 37.4 | 45.7 | 22.2% |
TCAD vertical e-field peak value (V/cm) | 9.17×106 | 6.50×106 | −29.1% |
TCAD horizontal e-field peak value (V/cm) | 9.58×106 | 7.82×106 | −18.4% |
CG-AA TDDB T63% lifetime (s) | 68 | 570 | 738% |
CG-AA burnout failure (PPM) | 1000 | <10 | − |
PGM Speed (V/Pulse) | 3.9 | 4.5 | 15.4% |
ERS Speed (V/Pulse) | 5.5 | 5.9 | 7.3% |
Data Retention(V) | 0.9 | 0.9 | Comparable |
2.2 TCAD simulation of electric field distribution in the CG-AA structure
TEM results indicated that the CG-AA interface, particularly at the AA top corners and CG bottom corners, is the most vulnerable region for dielectric breakdown due to high electric field concentration. To theoretically validate this observation, TCAD simulations were performed to analyze the electric field distribution in both the vertical (D1 cut) and horizontal (D2 cut) directions under erase bias conditions, as illustrated in Fig. 2(a).
The vertical electric field profile, shown in Fig. 3(a), revealed that the electric field at the cell-open corner was significantly higher than at other locations within the device. Similarly, the horizontal electric field profile, shown in Fig. 3(b), demonstrated that the AA corners experienced greater electric field concentrations compared to other regions. These results confirm that CG-AA burnout predominantly occurs between the AA corner and the cell-open corner due to excessive localized electric field stress.
With the novel C2 structure, TCAD simulations showed a significant reduction in electric field intensity. TCAD software, model and related parameters are refered to Table 2. The peak vertical electric field was 29% lower in C2 compared to C1, as shown in Fig. 3(a) and Table 1, while the peak horizontal electric field was 18% lower, as shown in Fig. 3(b) and Table 1.
Item | Content | ||
Software | Sentaurus TCAD | ||
Input | Simulation structure | ||
Main physical model | Quantum model | Quantum potential | |
Mobility model | Enormal, doping dependence, high field saturation | ||
Density of states model | Effectiveintrinsic density (old slot boom) | ||
Recombination model | SRH (DopingDep) avalanche Band2Band | ||
Main parameter | Silicon relative permittivity | 11.7 | |
Silicon electron affinity | 4.0727 eV | ||
Silicon bandgap | 1.12416 eV | ||
Silicon mobility-electron | 1.4170 × 103 cm2/(V·s) | ||
Silicon mobility-hole | 4.7050 × 102 cm2/(V·s) | ||
Oxide relative permittivity | 3.9 | ||
Oxide electron affinity | 0.9 eV | ||
Oxide bandgap | 9.0 eV | ||
Output | Electric field |
These reductions indicate that the structural modifications in C2 significantly lower electric field strength in critical regions, which is expected to improve CG-AA reliability, reduce burn-in failure rates, and enhance endurance under P/E cycles, as further validated by experimental results.
3. Result and discussion
3.1 Device reliability improvement
The reliability of the NOR flash memory device was significantly enhanced through structural modifications, as evidenced by both Time-Dependent Dielectric Breakdown (TDDB) tests and failure rate measurements. The TDDB test results, depicted in Fig. 4, show a substantial improvement in the dielectric lifetime of the C2 structure compared to the C1 structure. Specifically, the T63% lifetime of the C2 structure increased from 68 s in C1 to 570 s in C2, as shown in Table 1. This 7.38× improvement directly correlates with the 22% expanded CG-AA distance, demonstrating the effectiveness of the structural modifications in enhancing the reliability of the NOR flash memory by reducing the likelihood of dielectric breakdown at the CG-AA interface.
In addition to the TDDB results, the early-cycle CG-AA burnout failure rate was significantly reduced. A reliability test was arranged to conduct 5000 times P/E cycling endurance test on 10,000 samples to check the failure rate of CG-AA burnout in the early cycing time period of cell P/E operation by EDA DM-24. As shown in Table 1, the failure rate decreased from 1000 ppm in C1 to less than 10 ppm in C2. This reduction in failure rate highlights the outstanding effect of the new C2 structure on improving cell endurance performance, addressing the critical challenge of dielectric burnout in early cycling periods.
3.2 Cost reduction enabled by enhanced reliability
The reliability enhancement achieved with the C2 structure not only improves device performance but also brings significant cost benefits. One key aspect is the reduction in FN stress time during the Characterization Program (CP) test. The conventional CP program generally contains FN stress test item, it was used to distinguish normal bit and weak bit[3]. The weak bit would be screened out as breakdown bin in CP test by Advantest T5830. As shown in Fig. 5(a), the FN stress time for the C2 structure can be significantly reduced without compromising reliability. In C2 structure, after a certain stress threshold (value: a), no additional CG-AA burnout occurred, while the C1 structure continued to experience burnout up to 40a. This reduction in FN stress time from 40a to a highlights the potential for cost savings in manufacturing. The improved reliability of C2 allows for more efficient testing, which in turn reduces overall testing time and cost, making it an economically viable solution for high-volume production.
3.3 P/E speed enhancement and data retention stability
For actual applications for NOR flash, it was crucial to ensure that the improvements did not come at the expense of operational performance, such as P/E speed and data retention capability. To consider the impact on cell operation performance for the new structure C2, relevate tests on P/E speed and data retention performance were arranged on tester Advantest T5830.
To raise the confidence level in the P/E speed test, we used large sample counts (1000ea ICs) as test vehicle. All samples were programmed or erased to an identical VT state. The P/E speed is characterized by comparing the change of voltage threshold (ΔVT) between C1 and C2 structural cells under a certain P/E pulse. Larger ΔVT under equivalent pulse widths indicate greater charge transfer efficiency, directly correlating to faster P/E speed. As shown in Fig. 5(b) and Fig. 5(c), the erase ΔVT distribution shifts leftward and the program ΔVT distribution shifts rightward both indicate accelerated P/E speed. The intrinsic reason for the P/E speed improvement will be discussed in the next section.
For the data retention test, which is crucial for a non-volatile storage cell, a post cycling data retention (PCHTDR) test was performed to compare the charge storage capability of the C1 and C2 structure. VT of programmed cells (64ea ICs) was tested before and after the experiment 10,000 P/E cycling under temperature 85 °C and followed by 100 hours baking under temperature 125 °C. This protocol corresponds to 10-year retention capability at 55 °C through Arrhenius equation. ΔVT before and after the experiment can indicate data retention performance. The VT distribution of C2 remained comparable to that of C1, confirming equivalent charge retention capability, as shown in Fig. 5(d) and Table 1. The observed VT shifts during testing originate from inherent charge movement, with failure spec defined as normalized VT exceeding −1 V threshold. This confirms that the C2 structure maintains data retention performance despite the improvements in speed. These results indicate that the C2 structure achieves an optimal balance between speed and data retention without compromising either.
3.4 Gate coupling ratio optimization and structural trade-offs
The preceding results demonstrate reliability improvements, but their impact on fundamental device physics requires systematic analysis of capacitive coupling mechanisms. The erase speed in NOR flash memory exhibits strong dependence on the gate coupling ratio (GCR), which governs the effective electric field distribution across the FG under fixed word line (WL) bias conditions. It was well known that cell coupling ratio was related with the MOS device capacitor[15−17]. Based on our previous experiments, the GCR is fundamentally determined by the capacitor between ONO dielectric (CONO) and tunnel oxide (CTun):
GCR=CONO/(CONO+CTun). | (1) |
Here, CONO and CTun are defiend as follows:
CONO=ε×(WFG+2(H−h))×L/TONO | (2) |
CTun=ϵ×WAA×L/TTun | (3) |
where WFG represents floating gate width, H-h denotes cell-open depth, TONO indicates total ONO stack thickness, L corresponds to gate length, and TTun indicates total ONO stack thickness.
To enhance erase speed, achieving a higher GCR requires an increase in CONO. However, expanding WFG worsens the side effect of cell-to-cell disturbance, necessitating a reduction in WFG. To compensate for the GCR degradation caused by this reduction, the cell-open depth must be increased. However, a larger cell-open depth reduces the CG-AA distance, resulting in poorer CG-AA burnout performance. In other words, a balance must be struck between CG-AA anti-breakdown ability and GCR performance.
To systematically resolve the inherent conflict between GCR enhancement and reliability degradation, a comprehensive Design of Experiments (DOE) was implemented across six configurations (C1 and DOE1-DOE5), as detailed in Table 3. Building upon the baseline C1 parameters, which featured a 23.5% increased FG thickness and 7.4% reduced FG widthfor improved breakdown resistance, the cell-open depth progressively increased from 59.2 nm (C1) to 67.2 nm (DOE5).
Parameter | C1 | DOE1 | DOE2 | DOE3 | DOE4 | DOE5 |
FG thickness (nm) | 58.7 | 58.7×1.235 | ||||
FG width (nm) | 72.9 | 72.9×0.926 | ||||
Cell-open depth (nm) | 59.2 | 59.2 | 59.2×1.022 | 59.2×1.076 | 59.2×1.103 | 59.2×1.136 |
CG-AA corner distance (nm) | 37.4 | 37.4×1.286 | 37.4×1.259 | 37.4×1.222 | 37.4×1.149 | 37.4×1.118 |
Breakdown bin failure rate (%) | 2.5 | 0.8 | 0.82 | 0.8 | 1.13 | 1.75 |
GCR | 0.342 | 0.318 | 0.335 | 0.362 | 0.388 | 0.438 |
The relationship between the breakdown bin and GCR value was analyzed in Fig. 6. The GCR was positively correlated with the cell-open depth, which could be explained by the GCR empirical equation. However, beyond the critical cell-open depth threshold of 63.7 nm (DOE3), the breakdown failure rate increased exponentially. This indicated that cell-open depth condition DOE3 should be a turning point for CG-AA burnout. At the same time, the distance between AA corner and cell-open corner was increased by 22% accordingly. Comparing DOE3 with C1, breakdown bin was reduced to 0.8% from 2.5% while GCR was sligthly increased from 0.342 to 0.362.
This optimized parameter set was subsequently implemented in the C2 design. These experimental results validate that the DOE-driven parameter optimization successfully resolves the GCR-reliability trade-off, enabling concurrent enhancement of the traditionally competing NOR flash metrics: reliability, speed, and data retention.
4. Summary
In conclusion, CG-AA burnout in NOR flash has emerged as a critical reliability challenge during technology scaling to the 50 nm node. Through TEM characterization and TCAD simulations, we identified the AA and cell-open corners as the most vulnerable points for electric field concentrations. This work resolves the fundamental scaling-reliability conflict through coordinated structural optimization. By synergistically adjusting FG thickness, reducing FG width, and tuning cell-open depth, the proposed design achieves 100× improvement in early-cycle burnout rate, 15.4% and 7.3% faster P/E speed, and 97.5% reduction in CP test time while maintaining equivalent data retention performance. These advancements demonstrate that geometric parameter optimization can overcome traditional scaling limitations through electric field management, GCR control, and manufacturing efficiency, demonstrating an unprecedented multi-parameter optimization capability. This methodology establishes a generalizable framework for developing next-generation NOR flash memories that simultaneously meet automotive zero-defect requirements and cost-effective mass production needs.
Acknowledgments
This work was supported by the Fundamental Research Funds for the Central Universities (Grant HUST: 5003190012), and the Natural Science Foundation of Hubei Province (Grant No. 2024AFA043).