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A high reliability NOR flash cell in 50 nm node technology

Kevin Fang1, 2, Wei Wang2, Yibai Xue1, Fan Wang2, Dong Pan2, Yi Li1, and Jerry Zhou1, 2,

+ Author Affiliations

 Corresponding author: Yi Li, liyi@hust.edu.cn; Jerry Zhou, Jerry_Zhou@xmcwh.com

DOI: 10.1088/1674-4926/25030030CSTR: 32376.14.1674-4926.25030030

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Abstract: Along with NOR flash cell scaling down, dielectric burnout has gradually become one of the most important factors which affects product reliability, especially for high dropout voltage films. In this study, we demonstrate a reliability-enhanced NOR flash cell in 50 nm node technology through structural optimization of floating gate (FG) dimensions and active area profile. By synergistically increasing FG thickness, reducing FG width, and tuning cell-open depth, the control gate-to-active area corner distance expands by 22%, suppressing peak electric fields by 29% vertically and 18% horizontally. This structural innovation achieves: (1) 100× reduction in early-cycle burnout failures, (2) 7.38× Time Dependent Dielectric Breakdown lifetime improvement, while maintaining data retention and accelerating programming/erasing speeds by 15.4%/7.3%. The enhanced reliability enables 97.5% reduction in Fowler-Nordheim stress time during Characterization Program testing, providing a cost-effective solution for automotive-grade flash memories.

Key words: NOR flash50 nmreliabilitycell endurance burnout

NOR flash memory, known for its high reliability and fast random access, has become a critical component in IoT, 5G, automotive electronics, and aerospace applications. As semiconductor technology advances, the scaling of NOR flash to the 50 nm node represents the cutting edge of non-volatile memory technology. This node not only enables higher integration density and faster performance but also meets the rigorous demands of modern applications, such as real-time processing and extreme environmental conditions. However, this technological progression intensifies a critical commercialization barrier: dielectric reliability degradation. Key parameters for evaluating NOR flash memory include data retention[1, 2], cell anti-breakdown capability[35], and resistance to ionizing radiation[68]. Scaling down induced failures, particularly dielectric burnout, transition reliability challenges from purely technical challenges to determinants of commercial viability. In automotive and aerospace industries that require defect-free certification, even marginal yield reductions escalate production costs exponentially. This directly undermines the cost-performance benefits enabled by node scaling.

Fig. 1(a) illustrates the schematic structure of a NOR flash cell, consisting of monocrystalline silicon (AA), tunnel oxide, polycrystalline silicon (floating gate, FG), ONO (oxide, nitride, oxide), and polycrystalline silicon (control gate, CG). The reliability challenges stem from the intrinsic physical mechanisms of NOR flash operations. Programming and erasing (P/E) cycles require high electric fields to impart sufficient energy for electrons to enter or escape the floating gate[9], through two established mechanisms: Fowler-Nordheim tunneling during erasing and Channel Hot Electron Injection during programming[1012].

Fig. 1.  (Color online) (a) A schematic of NOR flash cell structure. (b) The trend between scaling down node and CG-AA distance. (c) Cross section TEM image of CG-AA burnout issue.

As the technology node scales toward 50 nm, the progressive reduction in FG thickness and width necessitates compensatory increases in cell-open depth. This geometric scaling reduces the control gate-to-active area (CG-AA) distance, as shown in Fig. 1(b)[13]. According to the JEDEC standard, NOR flash memory must sustain over 100,000 P/E cycles. Our TCAD simulations reveal intensified electric field concentrations at AA top corners and CG bottom corners during P/E cycling, particularly under erase operations due to nearly double the CG-AA bias compared to programming[3, 14]. Transmission electron microscopy (TEM) in Fig. 1(c) confirms severe profile damage predominantly at these regions, making them the primary failure sites during cycling burn-in tests. While previous studies for improvement of reliability predominantly focused on process-level optimizations, including interface engineering[1, 4], defect reduction[3], and recipe refinement[5] to improve data retention and leakage control, these approaches all encounter inherent structural limitations when scaling down to advanced nodes, which are insufficient to support the 50 nm node reliability requirement.

This study introduces a high-reliability NOR flash cell design optimized for the 50 nm technology node. By carefully adjusting key structural parameters such as floating gate thickness, width, and cell-open depth, the CG-AA corner distance is significantly increased, reducing electric field concentrations and mitigating burnout issues. Importantly, these enhancements are achieved without sacrificing P/E speed or data retention performance. The proposed design reduces the early-cycle CG-AA burnout failure rate from 1000 ppm to below 10 ppm, representing a major advancement in reliability. Compared with existing approaches focusing on data retention [3−8], our work pioneers simultaneous optimization of anti-breakdown capability and operational performance through structural control. This breakthrough not only addresses critical challenges in scaling NOR flash but also ensures its competitiveness in high-reliability markets, paving the way for broader commercialization.

Based on TCAD simulation and TEM analysis of the 50 nm NOR flash cell structure, it can be indentified that the CG-AA interface is the most vulnerable region under cycling stress. To perform reliability optimization, we first fabricated a conventional 50nm NOR flash cell (C1), using a standard semiconductor manufacturing process. First, the cell active area (CAA) pattern was defined through CAA etching process, followed by shallow trench isolation (STI) to electrically isolate adjacent cells. Next, deep N-Well and standard high-voltage well were formed through ion implantation process. Subsequently, the tunnel oxide layer was grown using in-situ steam generation (ISSG) to achieve superior uniformity and quality, and FG was deposited via plasma-enhanced chemical vapor deposition. The inter-poly dielectric (IPD), consisting of an ONO stack, and CG were sequentially deposited using low-pressure chemical vapor deposition. Finally, the contact loop and back-end-of-line (BEOL) layers were fabricated using conventional processes to establish interconnection and enable package.

To improve reliability and mitigate CG-AA interface degradation, we implemented two major process changes through adjustments to STI etch and cell-open etch steps. A 40% reduction in STI etch time enhances FG thickness and reduces FG width, while a 43% extension of cell-open loop etch time achieves enlarged cell-open depth. These targeted structural optimizations yield the new C2 structure. Fig. 2(a) and Fig. 2(b) illustrate the detailed structural differences between the C1 and C2 designs, highlighting the enhancements achieved through structural optimizations. Compared to the original design, the C2 structure exhibited significant improvements in critical dimensions, including increasing the FG thickness by 23.5%, reducing the FG width by 7.4%, and increasing the cell-open depth by 7.6%, as shown in Table 1. Combining these parameters, the CG-AA corner distance has increased from 37.4 nm to 45.7 nm, which theoretically allows for higher voltage and improved reliability of the NOR flash cell.

Fig. 2.  (Color online) Standard 50 nm generation NOR flash cell. (a) C1 cell structure, with narrower CG-AA distance. (b) C2 cell structure, with increased FG thickness, increased cell-open depth, and decreased FG width.
Table 1.  Comparison of properties of two NOR flash cell structures C1 and C2.
Parameter C1 (old) C2 (new) Difference
FG thickness (nm) 58.7 72.5 23.5%
FG width (nm) 72.9 67.5 −7.4%
Cell-open depth (nm) 59.2 63.7 7.6%
CG-AA corner distance (nm) 37.4 45.7 22.2%
TCAD vertical e-field peak value (V/cm) 9.17×106 6.50×106 −29.1%
TCAD horizontal e-field peak value (V/cm) 9.58×106 7.82×106 −18.4%
CG-AA TDDB T63% lifetime (s) 68 570 738%
CG-AA burnout failure (PPM) 1000 <10
PGM Speed (V/Pulse) 3.9 4.5 15.4%
ERS Speed (V/Pulse) 5.5 5.9 7.3%
Data Retention(V) 0.9 0.9 Comparable
DownLoad: CSV  | Show Table

TEM results indicated that the CG-AA interface, particularly at the AA top corners and CG bottom corners, is the most vulnerable region for dielectric breakdown due to high electric field concentration. To theoretically validate this observation, TCAD simulations were performed to analyze the electric field distribution in both the vertical (D1 cut) and horizontal (D2 cut) directions under erase bias conditions, as illustrated in Fig. 2(a).

The vertical electric field profile, shown in Fig. 3(a), revealed that the electric field at the cell-open corner was significantly higher than at other locations within the device. Similarly, the horizontal electric field profile, shown in Fig. 3(b), demonstrated that the AA corners experienced greater electric field concentrations compared to other regions. These results confirm that CG-AA burnout predominantly occurs between the AA corner and the cell-open corner due to excessive localized electric field stress.

Fig. 3.  (Color online) TCAD simulations results in the CG-AA structure. (a) Vertical electric field profile. (b) Horizontal electric field profile.

With the novel C2 structure, TCAD simulations showed a significant reduction in electric field intensity. TCAD software, model and related parameters are refered to Table 2. The peak vertical electric field was 29% lower in C2 compared to C1, as shown in Fig. 3(a) and Table 1, while the peak horizontal electric field was 18% lower, as shown in Fig. 3(b) and Table 1.

Table 2.  TCAD model and parameters.
Item Content
Software Sentaurus TCAD
Input Simulation structure
Main physical model Quantum model Quantum potential
Mobility model Enormal, doping dependence, high field saturation
Density of states model Effectiveintrinsic density (old slot boom)
Recombination model SRH (DopingDep) avalanche Band2Band
Main parameter Silicon relative permittivity 11.7
Silicon electron affinity 4.0727 eV
Silicon bandgap 1.12416 eV
Silicon mobility-electron 1.4170 × 103 cm2/(V·s)
Silicon mobility-hole 4.7050 × 102 cm2/(V·s)
Oxide relative permittivity 3.9
Oxide electron affinity 0.9 eV
Oxide bandgap 9.0 eV
Output Electric field
DownLoad: CSV  | Show Table

These reductions indicate that the structural modifications in C2 significantly lower electric field strength in critical regions, which is expected to improve CG-AA reliability, reduce burn-in failure rates, and enhance endurance under P/E cycles, as further validated by experimental results.

The reliability of the NOR flash memory device was significantly enhanced through structural modifications, as evidenced by both Time-Dependent Dielectric Breakdown (TDDB) tests and failure rate measurements. The TDDB test results, depicted in Fig. 4, show a substantial improvement in the dielectric lifetime of the C2 structure compared to the C1 structure. Specifically, the T63% lifetime of the C2 structure increased from 68 s in C1 to 570 s in C2, as shown in Table 1. This 7.38× improvement directly correlates with the 22% expanded CG-AA distance, demonstrating the effectiveness of the structural modifications in enhancing the reliability of the NOR flash memory by reducing the likelihood of dielectric breakdown at the CG-AA interface.

Fig. 4.  (Color online) TDDB Weibull Distribution for CG-AA.

In addition to the TDDB results, the early-cycle CG-AA burnout failure rate was significantly reduced. A reliability test was arranged to conduct 5000 times P/E cycling endurance test on 10,000 samples to check the failure rate of CG-AA burnout in the early cycing time period of cell P/E operation by EDA DM-24. As shown in Table 1, the failure rate decreased from 1000 ppm in C1 to less than 10 ppm in C2. This reduction in failure rate highlights the outstanding effect of the new C2 structure on improving cell endurance performance, addressing the critical challenge of dielectric burnout in early cycling periods.

The reliability enhancement achieved with the C2 structure not only improves device performance but also brings significant cost benefits. One key aspect is the reduction in FN stress time during the Characterization Program (CP) test. The conventional CP program generally contains FN stress test item, it was used to distinguish normal bit and weak bit[3]. The weak bit would be screened out as breakdown bin in CP test by Advantest T5830. As shown in Fig. 5(a), the FN stress time for the C2 structure can be significantly reduced without compromising reliability. In C2 structure, after a certain stress threshold (value: a), no additional CG-AA burnout occurred, while the C1 structure continued to experience burnout up to 40a. This reduction in FN stress time from 40a to a highlights the potential for cost savings in manufacturing. The improved reliability of C2 allows for more efficient testing, which in turn reduces overall testing time and cost, making it an economically viable solution for high-volume production.

Fig. 5.  (Color Online) (a) The correlation between FN stress time and CP breakdown bin fail rate. (b) VT distribution post erasing. (c) VT distribution post programming. (d) VT distribution of data retention test.

For actual applications for NOR flash, it was crucial to ensure that the improvements did not come at the expense of operational performance, such as P/E speed and data retention capability. To consider the impact on cell operation performance for the new structure C2, relevate tests on P/E speed and data retention performance were arranged on tester Advantest T5830.

To raise the confidence level in the P/E speed test, we used large sample counts (1000ea ICs) as test vehicle. All samples were programmed or erased to an identical VT state. The P/E speed is characterized by comparing the change of voltage threshold (ΔVT) between C1 and C2 structural cells under a certain P/E pulse. Larger ΔVT under equivalent pulse widths indicate greater charge transfer efficiency, directly correlating to faster P/E speed. As shown in Fig. 5(b) and Fig. 5(c), the erase ΔVT distribution shifts leftward and the program ΔVT distribution shifts rightward both indicate accelerated P/E speed. The intrinsic reason for the P/E speed improvement will be discussed in the next section.

For the data retention test, which is crucial for a non-volatile storage cell, a post cycling data retention (PCHTDR) test was performed to compare the charge storage capability of the C1 and C2 structure. VT of programmed cells (64ea ICs) was tested before and after the experiment 10,000 P/E cycling under temperature 85 °C and followed by 100 hours baking under temperature 125 °C. This protocol corresponds to 10-year retention capability at 55 °C through Arrhenius equation. ΔVT before and after the experiment can indicate data retention performance. The VT distribution of C2 remained comparable to that of C1, confirming equivalent charge retention capability, as shown in Fig. 5(d) and Table 1. The observed VT shifts during testing originate from inherent charge movement, with failure spec defined as normalized VT exceeding −1 V threshold. This confirms that the C2 structure maintains data retention performance despite the improvements in speed. These results indicate that the C2 structure achieves an optimal balance between speed and data retention without compromising either.

The preceding results demonstrate reliability improvements, but their impact on fundamental device physics requires systematic analysis of capacitive coupling mechanisms. The erase speed in NOR flash memory exhibits strong dependence on the gate coupling ratio (GCR), which governs the effective electric field distribution across the FG under fixed word line (WL) bias conditions. It was well known that cell coupling ratio was related with the MOS device capacitor[1517]. Based on our previous experiments, the GCR is fundamentally determined by the capacitor between ONO dielectric (CONO) and tunnel oxide (CTun):

GCR=CONO/(CONO+CTun). (1)

Here, CONO and CTun are defiend as follows:

CONO=ε×(WFG+2(Hh))×L/TONO (2)
CTun=ϵ×WAA×L/TTun (3)

where WFG represents floating gate width, H-h denotes cell-open depth, TONO indicates total ONO stack thickness, L corresponds to gate length, and TTun indicates total ONO stack thickness.

To enhance erase speed, achieving a higher GCR requires an increase in CONO. However, expanding WFG worsens the side effect of cell-to-cell disturbance, necessitating a reduction in WFG. To compensate for the GCR degradation caused by this reduction, the cell-open depth must be increased. However, a larger cell-open depth reduces the CG-AA distance, resulting in poorer CG-AA burnout performance. In other words, a balance must be struck between CG-AA anti-breakdown ability and GCR performance.

To systematically resolve the inherent conflict between GCR enhancement and reliability degradation, a comprehensive Design of Experiments (DOE) was implemented across six configurations (C1 and DOE1-DOE5), as detailed in Table 3. Building upon the baseline C1 parameters, which featured a 23.5% increased FG thickness and 7.4% reduced FG widthfor improved breakdown resistance, the cell-open depth progressively increased from 59.2 nm (C1) to 67.2 nm (DOE5).

Table 3.  Cell structure change experiment.
ParameterC1DOE1DOE2DOE3DOE4DOE5
FG thickness (nm)58.758.7×1.235
FG width (nm)72.972.9×0.926
Cell-open depth (nm)59.259.259.2×1.02259.2×1.07659.2×1.10359.2×1.136
CG-AA corner distance (nm)37.437.4×1.28637.4×1.25937.4×1.22237.4×1.14937.4×1.118
Breakdown bin failure rate (%)2.50.80.820.81.131.75
GCR0.3420.3180.3350.3620.3880.438
DownLoad: CSV  | Show Table

The relationship between the breakdown bin and GCR value was analyzed in Fig. 6. The GCR was positively correlated with the cell-open depth, which could be explained by the GCR empirical equation. However, beyond the critical cell-open depth threshold of 63.7 nm (DOE3), the breakdown failure rate increased exponentially. This indicated that cell-open depth condition DOE3 should be a turning point for CG-AA burnout. At the same time, the distance between AA corner and cell-open corner was increased by 22% accordingly. Comparing DOE3 with C1, breakdown bin was reduced to 0.8% from 2.5% while GCR was sligthly increased from 0.342 to 0.362.

Fig. 6.  (Color Online) GCR and breakdown bin correlation with cell-open depth

This optimized parameter set was subsequently implemented in the C2 design. These experimental results validate that the DOE-driven parameter optimization successfully resolves the GCR-reliability trade-off, enabling concurrent enhancement of the traditionally competing NOR flash metrics: reliability, speed, and data retention.

In conclusion, CG-AA burnout in NOR flash has emerged as a critical reliability challenge during technology scaling to the 50 nm node. Through TEM characterization and TCAD simulations, we identified the AA and cell-open corners as the most vulnerable points for electric field concentrations. This work resolves the fundamental scaling-reliability conflict through coordinated structural optimization. By synergistically adjusting FG thickness, reducing FG width, and tuning cell-open depth, the proposed design achieves 100× improvement in early-cycle burnout rate, 15.4% and 7.3% faster P/E speed, and 97.5% reduction in CP test time while maintaining equivalent data retention performance. These advancements demonstrate that geometric parameter optimization can overcome traditional scaling limitations through electric field management, GCR control, and manufacturing efficiency, demonstrating an unprecedented multi-parameter optimization capability. This methodology establishes a generalizable framework for developing next-generation NOR flash memories that simultaneously meet automotive zero-defect requirements and cost-effective mass production needs.

This work was supported by the Fundamental Research Funds for the Central Universities (Grant HUST: 5003190012), and the Natural Science Foundation of Hubei Province (Grant No. 2024AFA043).



[1]
Chen H L, Liu B T, Gu L. Data retention enhancement of modern 55nm NOR flash memory. 2022 China Semiconductor Technology International Conference, 2022, 1
[2]
Yu J M, Park J Y, Lee G B, et al. Demonstration of thermally-assisted programming with high speed and improved reliability for junctionless nanowire NOR flash memory. IEEE Trans Nanotechnol, 2019, 18, 1110 doi: 10.1109/TNANO.2019.2945321
[3]
Sun P, Li Y, Yao Y, et al. Study for NOR Flash cell burn out failure improvement in the advanced node below 65nm2019 IEEE 13th International Conference on ASIC, 2019, 1
[4]
Chen H L, Tong Y X, Qi X Y, et al. Silicide profile optimization on active area in 4XNM ETOX NOR flash memory. 2023 China Semiconductor Technology International Conference, 2023, 1
[5]
Du Y H, Gu L, Chen H L, et al. Yield improvement in 4X node technology ETOX NOR flash by optimizing control gate related process and design. 2024 Conference of Science and Technology for Integrated Circuits, 2024, 1
[6]
Chen C Z, Hu D Y, Wu H M. Effective radiation damage to floating gate of flash memory. 2021 China Semiconductor Technology International Conference, 2021, 1
[7]
Vargas-Sierra S, Tanios B, González-Luján J J, et al. Tid Radiation Effects of 1Gb cots nor Flash Memories for the esa juice Mission. 2019 19th European Conference on Radiation and Its Effects on Components and Systems, 2019, 1
[8]
Tanios B, Kaddour M, Forgerit B, et al. Single event effects characterization of 55-65nm NOR flash for space applications. 2021 21th European Conference on Radiation and Its Effects on Components and Systems, 2021, 1
[9]
Verma R. Flash memory quality and reliability issues. IEEE International Workshop on Memory Technology, Design and Testing, 1996, 32
[10]
Lenzlinger M, Snow E H. Fowler-Nordheim tunneling into thermally grown SiO2. IEEE Trans Electron Devices, 1968, 15(9), 686
[11]
Cottrell P E, Troutman R R, Ning T H. Hot-electron emission in N-channel IGFET’s. IEEE Trans Electron Devices, 1979, 26(4), 520 doi: 10.1109/T-ED.1979.19456
[12]
Eitan B, Frohman-Bentchkowsky D. Hot-electron injection into the oxide in n-channel MOS devices. IEEE Trans Electron Devices, 1981, 28(3), 328 doi: 10.1109/T-ED.1981.20336
[13]
Lee J S. Review paper: Nano-floating gate memory devices. Electron Mater Lett, 2011, 7(3), 175 doi: 10.1007/s13391-011-0901-5
[14]
Yang X N, Liu J, Zheng Z W, et al. Impact of P/E cycling on read current fluctuation of NOR Flash memory cell: A microscopic perspective based on low frequency noise analysis. 2015 IEEE International Reliability Physics Symposium, 2015, 5B.7.1
[15]
Shibata T, Ohmi T. A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Trans Electron Devices, 1992, 39(6), 1444 doi: 10.1109/16.137325
[16]
Chen H L, Xu R, Wang H, et al. Improvement of disturb and endurance in NOR flash memory. 2022 China Semiconductor Technology International Conference, 2022, 1
[17]
Ma J Y, Wang L, Liang C D, et al. Structure optimization of 4X NM nor flash for improving cell performance. 2024 Conference of Science and Technology for Integrated Circuits, 2024, 1
Fig. 1.  (Color online) (a) A schematic of NOR flash cell structure. (b) The trend between scaling down node and CG-AA distance. (c) Cross section TEM image of CG-AA burnout issue.

Fig. 2.  (Color online) Standard 50 nm generation NOR flash cell. (a) C1 cell structure, with narrower CG-AA distance. (b) C2 cell structure, with increased FG thickness, increased cell-open depth, and decreased FG width.

Fig. 3.  (Color online) TCAD simulations results in the CG-AA structure. (a) Vertical electric field profile. (b) Horizontal electric field profile.

Fig. 4.  (Color online) TDDB Weibull Distribution for CG-AA.

Fig. 5.  (Color Online) (a) The correlation between FN stress time and CP breakdown bin fail rate. (b) VT distribution post erasing. (c) VT distribution post programming. (d) VT distribution of data retention test.

Fig. 6.  (Color Online) GCR and breakdown bin correlation with cell-open depth

Table 1.   Comparison of properties of two NOR flash cell structures C1 and C2.

Parameter C1 (old) C2 (new) Difference
FG thickness (nm) 58.7 72.5 23.5%
FG width (nm) 72.9 67.5 −7.4%
Cell-open depth (nm) 59.2 63.7 7.6%
CG-AA corner distance (nm) 37.4 45.7 22.2%
TCAD vertical e-field peak value (V/cm) 9.17×106 6.50×106 −29.1%
TCAD horizontal e-field peak value (V/cm) 9.58×106 7.82×106 −18.4%
CG-AA TDDB T63% lifetime (s) 68 570 738%
CG-AA burnout failure (PPM) 1000 <10
PGM Speed (V/Pulse) 3.9 4.5 15.4%
ERS Speed (V/Pulse) 5.5 5.9 7.3%
Data Retention(V) 0.9 0.9 Comparable
DownLoad: CSV

Table 2.   TCAD model and parameters.

Item Content
Software Sentaurus TCAD
Input Simulation structure
Main physical model Quantum model Quantum potential
Mobility model Enormal, doping dependence, high field saturation
Density of states model Effectiveintrinsic density (old slot boom)
Recombination model SRH (DopingDep) avalanche Band2Band
Main parameter Silicon relative permittivity 11.7
Silicon electron affinity 4.0727 eV
Silicon bandgap 1.12416 eV
Silicon mobility-electron 1.4170 × 103 cm2/(V·s)
Silicon mobility-hole 4.7050 × 102 cm2/(V·s)
Oxide relative permittivity 3.9
Oxide electron affinity 0.9 eV
Oxide bandgap 9.0 eV
Output Electric field
DownLoad: CSV

Table 3.   Cell structure change experiment.

ParameterC1DOE1DOE2DOE3DOE4DOE5
FG thickness (nm)58.758.7×1.235
FG width (nm)72.972.9×0.926
Cell-open depth (nm)59.259.259.2×1.02259.2×1.07659.2×1.10359.2×1.136
CG-AA corner distance (nm)37.437.4×1.28637.4×1.25937.4×1.22237.4×1.14937.4×1.118
Breakdown bin failure rate (%)2.50.80.820.81.131.75
GCR0.3420.3180.3350.3620.3880.438
DownLoad: CSV
[1]
Chen H L, Liu B T, Gu L. Data retention enhancement of modern 55nm NOR flash memory. 2022 China Semiconductor Technology International Conference, 2022, 1
[2]
Yu J M, Park J Y, Lee G B, et al. Demonstration of thermally-assisted programming with high speed and improved reliability for junctionless nanowire NOR flash memory. IEEE Trans Nanotechnol, 2019, 18, 1110 doi: 10.1109/TNANO.2019.2945321
[3]
Sun P, Li Y, Yao Y, et al. Study for NOR Flash cell burn out failure improvement in the advanced node below 65nm2019 IEEE 13th International Conference on ASIC, 2019, 1
[4]
Chen H L, Tong Y X, Qi X Y, et al. Silicide profile optimization on active area in 4XNM ETOX NOR flash memory. 2023 China Semiconductor Technology International Conference, 2023, 1
[5]
Du Y H, Gu L, Chen H L, et al. Yield improvement in 4X node technology ETOX NOR flash by optimizing control gate related process and design. 2024 Conference of Science and Technology for Integrated Circuits, 2024, 1
[6]
Chen C Z, Hu D Y, Wu H M. Effective radiation damage to floating gate of flash memory. 2021 China Semiconductor Technology International Conference, 2021, 1
[7]
Vargas-Sierra S, Tanios B, González-Luján J J, et al. Tid Radiation Effects of 1Gb cots nor Flash Memories for the esa juice Mission. 2019 19th European Conference on Radiation and Its Effects on Components and Systems, 2019, 1
[8]
Tanios B, Kaddour M, Forgerit B, et al. Single event effects characterization of 55-65nm NOR flash for space applications. 2021 21th European Conference on Radiation and Its Effects on Components and Systems, 2021, 1
[9]
Verma R. Flash memory quality and reliability issues. IEEE International Workshop on Memory Technology, Design and Testing, 1996, 32
[10]
Lenzlinger M, Snow E H. Fowler-Nordheim tunneling into thermally grown SiO2. IEEE Trans Electron Devices, 1968, 15(9), 686
[11]
Cottrell P E, Troutman R R, Ning T H. Hot-electron emission in N-channel IGFET’s. IEEE Trans Electron Devices, 1979, 26(4), 520 doi: 10.1109/T-ED.1979.19456
[12]
Eitan B, Frohman-Bentchkowsky D. Hot-electron injection into the oxide in n-channel MOS devices. IEEE Trans Electron Devices, 1981, 28(3), 328 doi: 10.1109/T-ED.1981.20336
[13]
Lee J S. Review paper: Nano-floating gate memory devices. Electron Mater Lett, 2011, 7(3), 175 doi: 10.1007/s13391-011-0901-5
[14]
Yang X N, Liu J, Zheng Z W, et al. Impact of P/E cycling on read current fluctuation of NOR Flash memory cell: A microscopic perspective based on low frequency noise analysis. 2015 IEEE International Reliability Physics Symposium, 2015, 5B.7.1
[15]
Shibata T, Ohmi T. A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Trans Electron Devices, 1992, 39(6), 1444 doi: 10.1109/16.137325
[16]
Chen H L, Xu R, Wang H, et al. Improvement of disturb and endurance in NOR flash memory. 2022 China Semiconductor Technology International Conference, 2022, 1
[17]
Ma J Y, Wang L, Liang C D, et al. Structure optimization of 4X NM nor flash for improving cell performance. 2024 Conference of Science and Technology for Integrated Circuits, 2024, 1
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    Kevin Fang, Wei Wang, Yibai Xue, Fan Wang, Dong Pan, Yi Li, Jerry Zhou. A high reliability NOR flash cell in 50 nm node technology[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25030030
    K Fang, W Wang, Y B Xue, F Wang, D Pan, Y Li, and J Zhou, A high reliability NOR flash cell in 50 nm node technology[J]. J. Semicond., 2025, 46(12), 122301 doi: 10.1088/1674-4926/25030030
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    Received: 15 March 2025 Revised: 20 May 2025 Online: Accepted Manuscript: 20 June 2025Uncorrected proof: 23 July 2025

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      Kevin Fang, Wei Wang, Yibai Xue, Fan Wang, Dong Pan, Yi Li, Jerry Zhou. A high reliability NOR flash cell in 50 nm node technology[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25030030 ****K Fang, W Wang, Y B Xue, F Wang, D Pan, Y Li, and J Zhou, A high reliability NOR flash cell in 50 nm node technology[J]. J. Semicond., 2025, 46(12), 122301 doi: 10.1088/1674-4926/25030030
      Citation:
      Kevin Fang, Wei Wang, Yibai Xue, Fan Wang, Dong Pan, Yi Li, Jerry Zhou. A high reliability NOR flash cell in 50 nm node technology[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25030030 ****
      K Fang, W Wang, Y B Xue, F Wang, D Pan, Y Li, and J Zhou, A high reliability NOR flash cell in 50 nm node technology[J]. J. Semicond., 2025, 46(12), 122301 doi: 10.1088/1674-4926/25030030

      A high reliability NOR flash cell in 50 nm node technology

      DOI: 10.1088/1674-4926/25030030
      CSTR: 32376.14.1674-4926.25030030
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      • Kevin Fang got his bachelor’s degree in 2003 from Tongji University and his master’s degree in 2011 from Huazhong University of Science and Technology. Now his is a doctoral student at Huazhong University of Science and Technology under the supervision of Prof. Yi Li. His research focuses on reliability issues of 50 nm floating gate NOR flash memory products
      • Yi Li currently serves as a professor at Huazhong University of Science and Technology (HUST). He obtained his PhD in microelectronics from HUST in 2014. His primary research interests are centered on memristors and their applications in the realms of in - memory computing and neuromorphic computing
      • Jerry Zhou got his bachelor’s degree in 2004 from Wuhan University of Technology and his master’s degree in 2014 from Wuhan University. He is currently a doctoral student at Huazhong University of Science and Technology. His research focuses on non-volatile memory process and reliability research
      • Corresponding author: liyi@hust.edu.cnJerry_Zhou@xmcwh.com
      • Received Date: 2025-03-15
      • Revised Date: 2025-05-20
      • Available Online: 2025-06-20

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