A two-dimensional (2D) multi-channel silicon-based microelectrode array is developed for recording neural signals.Three photolithographic masks are utilized in the fabrication process.SEM images show that the microprobe is 1.2mm long,100μm wide,and 30μm thick,with recording sites spaced 200μm apart for good signal isolation.For the individual recording sites,the characteristics of impedance versus frequency are shown by in vitro testing.The impedance declines from 14MΩ to 1.9kΩ as the frequency changes from 0 to 10MHz.A compatible PCB (print circuit board) aids in the less troublesome implantation and stabilization of the microprobe.

A low-power,high-frequency CMOS peak detector is proposed.This detector can detect RF signal and base-band signal peaks.The circuit is designed using SMIC 0.35μm standard CMOS technology.Both theoretical calculations and post simulations show that the detection error is no more than 2% for various temperatures and processes when the input amplitude is larger than 400mV.The detection bandwidth is up to 10GHz,and its static current dissipation is less than 20μA.

A near-infrared single-photon detection system is established by using pigtailed InGaAs/InP avalanche photodiodes.With a 50GHz digital sampling oscilloscope,the function and process of gated-mode (Geiger-mode) single-photon detection are intuitionally demonstrated for the first time.The performance of the detector as a gated-mode single-photon counter at wavelengths of 1310 and 1550nm is investigated.At the operation temperature of 203K,a quantum efficiency of 52% with a dark count probability per gate of 2.4E-3,and a gate pulse repetition rate of 50kHz are obtained at 1550nm.The corresponding parameters are 43%,8.5E-3,and 200kHz at 238K.

Based on the dielectric continuum model and Loudon’s uniaxial crystal model,quasi-confined (QC) optical phonon modes and electron-QC phonon coupling functions in quasi-one-dimensional (Q1D) wurtzite quantum well wires (QWWs) are deduced and analyzed.Numerical calculations on an AlN/GaN/AlN wurtzite QWW are performed.The results reveal that the dispersions of the QC modes are quite obvious only when the free wave-number kz in the z-direction and the azimuthal quantum number m are small.The reduced behavior of the QC modes in wurtzite quantum systems is clearly observed.Through the discussion of the electron-QC mode coupling functions,it is found that the lower-frequency QC modes in the high-frequency region play a more important role in the electron-QC phonon interactions.Moreover,our computations also prove that kz and mhave a similar influence on the electron-QC phonon coupling properties.

New boundary conditions and a 2D potential distribution along the channel of a high-k gate-dielectric MOSFET,including both the gate dielectric material region and the depletion region,are given.Based on this distribution,a 2D threshold-voltage model with the fringing-field and short-channel effects is developed for a high-k gate-dielectric MOSFET.The model agrees well with experimental data and a quasi 2D model,and is even more accurate than the quasi 2D model at higher drain voltages.Factors affecting the threshold behavior of the high-k gate-dielectric MOSFET are discussed in detail.

An emitter self-aligned InP-based single heterojunction bipolar transistor with a cutoff frequency (fT) of 162GHz is reported.The emitter size is 0.8μm×12μm,the maximum DC gain is 120,the offset voltage is 0.10V,and the typical breakdown voltage at IC=0.1μA is 3.8V.This device is suitable for high-speed low-power applications,such as OEIC receivers and analog-to-digital converters.

Based on the minimum settling time (MST) theory and step-response analysis of the second order system in active switched capacitor (SC) networks,a novel clock feedthrough frequency compensation (CFFC) method for a folded-cascode OTA is proposed.The damping factor η is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling.Research results indicate that the settling time of the compensated OTA is reduced by 22.7%;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns;for VGA application,fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.

A current-mode DC-DC buck converter with high stability is presented.The loop gain’s expression of the current-mode converter is derived by employing an advanced model of a current-mode control converter.After analyzing the loop gain’s expression,which illustrates the method of selecting suitable frequency compensation for the control loop,a novel pole-zero tracking frequency compensation is proposed.Based on theoretical analysis,a DC-DC buck converter with high stability is designed with 0.5μm-CMOS technology.The simulated results reveal that the stability of the converter is independent of the load current and the input voltage.Moreover,the converter provides a full load transient response setting time of less than 5μs and overshoots and undershoots of less than 30mV.

This paper presents the total dose radiation performance of 0.8μm SOI CMOS devices fabricated with full dose SIMOX technology.The radiation performance is characterized by threshold voltage shifts and leakage currents of transistors and standby currents of ASIC as functions of the total dose up to 500krad(Si).The experimental results show that the worst case threshold voltage shifts of front channels are less than 320mV for pMOS transistors under off-gate radiation bias at 1Mrad(Si) and less than 120mV for nMOS transistors under on-gate radiation bias.No significant radiation-induced leakage current is observed in transistors to 1Mrad(Si).The standby currents of ASIC are less than the specification of 5μA over the total dose range of 500krad(Si).

The properties of strong-coupling excitons in semiconductor quantum dots are investigated using the linear combination operator and unitary transformation methods.The ground state energy of the heavy-hole exciton is obtained under the effective-mass approximation.The influences of the radius of the quantum dots and the confinement strength on the ground state energy of the strong-coupling exciton in the semiconductor quantum dots are discussed in the case of strong-coupling.Numerical calculations are performed for a TlCl semiconductor.Our results illustrate that the energy of the ground state heavy-hole exciton decreases with the increase of the radius of the quantum dots and increases with the increase of the confinement strength ω0 of quantum dots.

Lattice perfection,deep level defects,electrical properties,dislocations,and the growth polarity of bulk ZnO single crystal are characterized with X-ray diffraction,photoluminescence,the Hall effect,and optical microscopy.The influence of the defects on the material properties is discussed through comparison of the ZnO single crystal before and after annealing.

Single-layer and multilayer ZnO thin films are deposited by means of gas discharge active reaction evaporation through single and multiple depositions at relatively lower temperatures.AFM and XRD patterns show that these films possess multicrystal fabric that gives priority to (002),and the grain dimension of the multilayer ZnO film is increased.A multilayer ZnO film with a nonlinear coefficient of 61.54 and varistor voltage of 20.10V can be obtained at a 200℃ annealing temperature.The varistor voltage can be reduced significantly by increasing the annealing temperature within a certain range.The mechanism behind the effect of different layers and annealing temperature on varistor characteristics of ZnO thin films is also discussed.

Nanocrystalline silicon carbide (nc-SiC) thin films are fabricated on silicon (100) substrates by helicon wave plasma enhanced chemical vapor deposition (HW-PECVD) in a high hydrogen dilution scheme.The structure and morphology of the deposited films are studied using X-ray diffraction,Fourier transform infrared spectroscopy,and scanning electron microscopy.The fluorescence of the samples is characterized by photoluminescence (PL).The nc-SiC films deposited at the substrate temperature of 500℃ show a strong infrared absorption peak,which is related to the TO vibration mode of SiC.X-ray diffraction analysis shows that the structure of the films is of the hexagonal 6H-SiC poly type.Intense ultraviolet emission is observed at room temperature under the excitation of a Xe lamp,and a PL peak shift is detected for the films deposited at different H2 flow rates.

This paper reports a method for fabricating pentacene o-dichlorobenzene solution.Uniform and larger-area poly-crystal pentacene thin films are obtained at about 100℃.The thin films formed on Si and SiO2 surfaces are characterized by UV-Vis absorption spectrum,optical microscopy,scanning electron microscopy,atomic force microscopy,and X-ray diffraction spectroscopy.

Silicon based PZT films are prepared by the sol-gel process. The electrodes are shaped with the lift-off technique and annealing. The PZT films are patterned by chemical etching before crystallization annealing.The electrodes and PZT films are analyzed by SEM,EDX,and XRD.The results show that the films are in the perovskite phase. The patterning process improves conditions of photolithography and etching,enhances qualities of figures of electrodes and PZT films without reducing their performance.The patterning technology of electrodes and PZT films does not require a long chemical etching process and improves the compatibility of fabrication of PZT films with MEMS.

The effects of a Cr diffusion barrier on the performance of flexible Cu(InxGa1-x)Se2(CIGS) solar cells deposited on stainless steel (SS) substrate are investigated.The XRD and SEM results show that the Cr barrier layer can partly block the thermal diffusion of Fe impurities from SS substrate to a CIGS absorber layer and also remarkably reduce the surface roughness of the CIGS layers,and thus the crystalline quality of CIGS thin films is improved.Iron in the compound FeInSe2 forms a deep level defect in the CIGS absorber layers and degrades the photovoltaic properties.Flexible solar cells (with an active area of 0.87cm2) deposited on Soda-Lime glass/Mo,SS/Mo and SS/Cr barrier/Mo,using the same deposition conditions,have conversion efficiencies of 10.7%,7.95%,and 8.58%,respectively.The enhancements of solar cells based on SS are due to the impacts of Cr barriers.

Due to the reaction vapor concentration gradient in LPCVD furnaces,as-grown oxide films tend to be thinner at the wafer edge than at the wafer center.ISSG (in-situ steam generation) annealing,a new low-pressure rapid oxidation annealing technique,is used to compensate this non-uniformity in thickness from oxide deposition and obtain uniform SiO2 thin films.Experimental data show that the variation of the oxide thickness (between the maximum and the minimum) is reduced from 0.76 to 0.16nm,and the standard deviation for 49 points is reduced from 0.25 to 0.04nm.The ISSG-annealed oxide films,with a tunneling electrical field improved to 4.3MV/cm,also show better interface quality than those annealed by conventional O.2.The results provide a convenient and effective solution for planarizing deposited SiO2 thin films for VLSI manufacture

This paper reports the piezoresistive properties of resonant tunneling diodes (RTDs) as detected with a newly established testing system.The shifts of their I-V characteristics in different stress states are detected,demonstrating that the RTDs possess piezoresistive properties.The sensitivity of the RTDs is larger than 1E-8Pa-1.Moreover,to accurately illustrate the piezoresistive properties of RTD,the I-V characteristic coherence of an RTD is tested.According to the experimental results,the largest relative resistance shift of an RTD in the same environmental condition is less than 3%,1% of which is caused by the testing instrument.

Post-treated metal-induced unilaterally crystallized(MIUC) poly-Si technology using a triple frequency YAG solid-state laser is discussed in detail.It is found that MIUC TFT has good performance and uniformity.By using the triple frequency YAG laser post-treatment,the performance of the MIUC TFT can be further enhanced.The field-mobility of the MIUC TFT increases almost by a factor of two. In addition,the improvement of the performance and the uniformity of the post-treated TFTs are correlated to the modified laser condition and vary regularly,which implies that the laser post-treatment is controllable.This provides a foundation for industrialization.

This paper describes the design,fabrication,and performance of an X-band 8 W AlGaAs/InGaAs/GaAs PHEMT MMIC power amplifier.With a two-stage topology design,this amplifier is designed to fully match a 50Ω input and output impedance.The area of chip is 4.5mm×3mm.With 7.5V and 1.5A DC bias conditions,an output power of 8W,power added efficiency of 30%,and power gain of 15dB are achieved.

A GaAs power PHEMT with a dielectric-assisted T-shaped gate is reported.The gate length and the dimension of the gate head can be controlled in the T-shaped gate processing,and good process controllability and high yield can be achieved.GaAs power PHEMTs with a gate width of 19.2mm and Ku-band internally matched transistors with the combination of two chips are developed.The high power device demonstrates an output power of 20W with a power gain of 6dB and a typical power-added efficiency of 31% across the band of 14.0～14.5GHz.

A 10Gb/s low noise preamplifier based on a 0.2μm GaAs PHEMT is theoretically analyzed,simulated,and taped out for verification.A common-source topology is adopted to reduce the noise and enhance the sensitivity.The test results show that under a single supply voltage of 3.3V,the preamplifier has a trans-impedance of 57.8dB·Ω with a bandwidth of over 10GHz.The chip’s area is 0.5mm×0.4mm.According to the test results the preamplifier can operate well at 10Gb/s.

A new SOI LDMOS with folded silicon (FSOI-LDMOS) is proposed,in which the silicon substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain.The majority-carrier accumulation layer is formed in the drift region because of the extended gate when the device is in the on state,and the concentration of drift region is higher than that in conventional SOI-LDMOS with the same breakdown voltage due to from the additional electric field modulation.The extra majority-carrier is introduced on the side-wall of the trench,which further reduces the on-resistance of the drift region.In addition the channel density is double due to trenching in the folded channel,which reduces the channel on-resistance.3D ISE simulation indicates that the ultra-low specific on-resistance is obtained with a breakdown voltage of less than 40V in FSOI-LDMOS.

This paper analyzes the relation between the boundary curvature radius of the drain region and the breakdown voltage of RF RESURF LDMOS.The bending of the curve in the RESURF technology can increase the breakdown voltage greatly.Analysis and simulation prove that the high breakdown voltage and much lower on-resistance in the same device profile can be maintained by an impurity dose or by increasing the thickness of the drift region and reducing boundary curvature radius of the drain region under the REUSRF principle.

The ohmic contacts of Ti/Al/Ni/Au on AlGaN/GaN heterostructures are investigated by adopting different Ti/Al structures and thermal annealing processes.The results show that good ohmic contact with a low specific contact resistance of 3.30E-6Ω·cm2 is obtained by evaporating a Ti(20nm)/Al(120nm)/Ni(55nm)/Au(45nm) multilayer and annealing for 30s at 850℃ in ultra-high purity N2 ambient.The ohmic contact has good thermal stability and surface morphology,making it very suitable for manufacturing high performance AlGaN/GaN HEMTs.

A novel semi-insulation bonding SOI structure that is realized by LPCVD and introducing an epitaxial interim polysilicon layer is reported.The integrality percentage of this new wafer structure is more than 85%.The contact specific resistance of the Si-Si bonding interface is less than 5E-4Ω·cm2.It can be widely applied in high-voltage ICs,high-reliability ICs,MEMS,and OEIC.

Aiming at two main problems of SOI device--the low vertical breakdown voltage and self-heating effect--a novel SOI high-voltage power device with a variable-k dielectric layer (VkD) is proposed.A low-k dielectric is used to enhance the electric field of the buried layer on the drain side with a high electric field,and a high-thermal conductivity dielectric is used near the source side where the current density is large.The device thus can sustain a high voltage while simultaneously reducing the self-heating effect simultaneously.The results show that an electric field in the buried layer of 212V/μm and a breakdown voltage of 255V can be obtained for a VkD structure with a 2μm-thick Si layer and a 1μm buried layer with low k1=2.Compared with conventional SOI,the electric field of the buried layer and breakdown voltage of the VkD SOI are enhanced by 66% and 43%,respectively.The maximum temperature of the device is lowered by 52%.

A prototype PLL frequency synthesizer for a single-conversion digital cable TV tuner is integrated in a standard 0.25μm CMOS process, except for the LC tanks and active loop filter.Three-band VCOs with AAC (auto-amplitude control) circuit switches controlled by I2C provide a wideband amplitude stable output.A third order active loop filter is used to boost the tuning voltage.A 16/17 dual-modulus prescaler with on improved logic structure increases the speed.With the help of the system-behavior model of the loop,the design of the loop parameters and the evaluation of the frequency synthesizer are discussed in depth.The measurements results show that the locked range of the frequency synthesizer is 75 to 830MHz,the phase noise in the locked band can reach -90.46dBc/Hz at a 10kHz offset and -115dBc/Hz at a 100kHz offset.The spurious signal near the reference frequency is less than -90dB.

The dynamic and static characteristics of SOI piezoresistive microcantilever sensors are studied.Expressions for predicting the sensitivity and resolution of sensors used in surface stress measurement are derived.According to analysis of the influence of the parameters on the performance of the sensors,a parameter design and optimization process is presented.A suit of design parameters is deduced,with a sensitivity of -1.8E-3m/N,a resolution of 8.5E-5N/m,an elasticity coefficient of 0.023N/m,and a resonance frequency of 1.3E4Hz.

The influence of the linewidth enhancement factor and cross-gain modulation on the output power of an interferometer based on a semiconductor optical amplifier (SOA) is analyzed.It is found that two output ports of the interferometer do not reach the minimum and maximum simultaneously due to cross-gain modulation.The interferometer has a working range instead of one working point, and this range has a relation with α.The unbalanced state,working range and extinction ratio are discussed.With the increase of α,the degree of unbalanced and work range decrease,while the extinction ratio increases.Experimental results prove the correctness of theoretical analysis.

An Er3+-Yb3+ co-doped phosphate glass waveguide for applications in optical amplifiers is studied.The optical gain at the wavelength of 1535nm is measured,and an 8.5dB relative gain in a 1.2cm device is observed when the waveguide is pumped with a 976nm laser with 130mW of power.In this case,the device shows strong green luminescence,and the intensity increases as the power of the pump laser increases.Also,upconversion from 2H11/2 and 4S3/2 levels is confirmed by using a photomultiplier and a monochromator.

The fabrication and performance of a p-GaN/AlGaN/GaN Schottky photodetector are reported.Due to the polarization and Stark effects,spectral responses with a 10nm blue shift are observed.Under zero bias,the peak responsivity of the device is about 0.022A/W,and it increases to 0.19A/W under 1V reverse bias.The responsivity of the device is flat under a small forward bias,and two peaks appear at 283 and 355nm when the forward bias is increased to 1V.Based on the measurements and the polarization effect,the changes of carrier distribution are used to explain the working mechanism of this Schottky photodetector.The polarization effects can fundamentally affect the device response characteristics.Optimizing the device design and changing the bias can change the responsivity region and improve the peak responsivity of this Schottky ultraviolet photodetector.

A novel ultralow-voltage,low-power baseband processor for UHF RFID tags is presented.It is compatible with the "EPCTM Class-1 Generation-2 UHF RFID Protocol" and meets the special requirement of power consumption for passive tags.A new architecture of low-power baseband-processors fit for a power management scheme with a gated clock is proposed.It not only uses a novel scheme for generating pseudo-random numbers and a new partial decoder circuit,but also adopts other low-power technologies,such as a pipeline structure and reduced logic depth.The baseband processor can implement complex functions,including encoding/coding,anti-collision schemes,authorization schemes,and reading/writing operations to EEPROM.The chip is designed and fabricated using a 0.35μm 1P3M CMOS standard process.The minimum operation voltage is 1.5V,average current is 2.1μA,and power consumption is 3.15μW,with a die area of 1.1mm×0.8mm.

Various GaAs MMIC (monolithic microwave integrated circuit) passive components,including rectangle spiral inductors,MIM capacitors,and film resistors,are fabricated,and their equivalent circuit models are established.Various polynomial formulas are introduced to characterize models and performances of different passive components.This is convenient for circuit design.The extracted capacitance per unit area of the MIM capacitors is about 195pF/mm2,and the sheet resistance of the NiCr film resistors is about 16.1Ω/□.The effects of the geometrical parameters on the spiral inductors are also analyzed,and the results show that reducing the parasitic losses of the inductor areas helps to obtain high quality inductors.

This paper develops a nodal analysis model of in-plane electrothermal microactuators with the Galerkin method based on the weighted residue method.With high accuracy,easy modeling,and clear configuration,the model makes it possible to co-simulate with the control circuit,which means it can simulate the whole system with the electrothermal microactuators.The model is verified by simulation with ANSYS and agrees well with it.