A combination of atomic force microscopy (AFM) and scanning electron microscopy (SEM) is used to characterize dislocation etch pits in Si-doped GaN epilayer etched by molten KOH.Three types of etch pits with different shapes and specific positions in the surface have been observed,and a model of the etching mechanism is proposed to explain their origins.The pure screw dislocation is easily etched along the steps that the dislocation terminates.Consequently a small Ga-polar plane is formed to prevent further vertical etching,resulting in an etch pit shaped like an inverted truncated hexagonal pyramid at the terminal chiasma of two surface steps.However,the pure edge dislocation is easily etched along the dislocation line,inducing an etch pit of inverted hexagonal pyramid aligned with the surface step.The polarity is found to play an important role in the etching process of GaN.
A novel patterned-SOI LDMOSFET with a silicon window beneath the p-type channel was designed and fabricated for RF power amplifier applications.This novel device has good DC and RF characteristics.It has no kink effect on output performance,an off-state breakdown of up to 13V,and fT=6GHz at DC bias of Vg=Vd=3.6V.At 1.5GHz,a power-added efficiency (PAE) of 50% is achieved with an output power of up to 27dBm from this device
Based on a short anode GTO structure (SA-GTO),a novel GTO structure called an injection efficiency controlled gate turn off thyristor (IEC-GTO) is proposed,in which the injection efficiency can be controlled via an additional thin oxide layer located in the short anode contact region.The forward blocking,conducting,and switching characteristics are analyzed and compared with an SA-GTO and conventional GTO.The results show that the IEC-GTO can obtain a better trade-off relation between on-state and turn-off characteristics.Additionally,the width of the oxide layer covering the anode region and the doping concentration of the anode region are optimized,the process feasibility is analyzed,and a realization scheme is given.The results show that the introduction of an oxide layer would not increase the complexity of process of the IEC-GTO.
A new method,namely multiple point curvature compensation (MPCC),is proposed for the design of a bandgap reference,and its design principles,theoretical derivation,and one feasible circuitry implementation are presented.Being different from traditional techniques,this idea focuses on finding multiple temperatures in the whole range at which the first order derivatives of the output reference voltage equal zero.In this way,the curve of the output reference voltage is flattened and a better effect of curvature compensation is achieved.The circuitry is simulated in ST Microelectronics 0.18μm CMOS technology,and the simulated result shows that the average temperature coefficient is only 1ppm/℃ in the range from -40 to 125℃.
A large area multi-finger configuration power SiGe HBT device (with an emitter area of about 880μm2) was fabricated with 2μm double-mesa technology.The maximum DC current gain β is 214.The BVCEO is up to 10V,and the BVCBO is up to 16V with a collector doping concentration of 1e17cm-3 and collector thickness of 400nm.The device exhibits a maximum oscillation frequency fmax of 19.3GHz and a cut-off frequency fT of 18.0GHz at a DC bias point of IC=30mA and VCE=3V.MSG (maximum stable gain) is 24.5dB,and U (Mason unilateral gain) is 26.6dB at 1GHz.Due to the novel distribution layout,no notable current gain fall-off or thermal effects are observed in the I-V characteristics at high collector current.
A reproducible terahertz (THz) photocurrent was observed at low temperatures in a Schottky wrap gate single electron transistor with a normal-incident of a CH3OH gas laser with the frequency 2.54THz.The change of source-drain current induced by THz photons shows that a satellite peak is generated beside the resonance peak.THz photon energy can be characterized by the difference of gate voltage positions between the resonance peak and satellite peak.This indicates that the satellite peak exactly results from the THz photon-assisted tunneling.Both experimental results and theoretical analysis show that a narrow spacing of double barriers is more effective for the enhancement of THz response.
The influence of outside inertial shock combined with RF signal voltages on the properties of a shunt capacitive MEMS switch encapsulated in a low vacuum environment is analyzed considering the damping of the air around the MEMS switch membrane.An analytical expression that approximately computes the displacement induced by outside shock is obtained.According to the expression,the minimum required mechanical stiffness constant of an MEMS switch beam in some maximum tolerated insertion loss condition and some external inertial shock environment or the insertion loss induced by external inertial shock can also be obtained.The influence is also illustrated with an RF MEMS capacitive switch example,which shows that outside environment factors have to be taken into account when designing RF MEMS capacitive switches working in low vacuum.While encapsulating RF MEMS switches in low vacuum diminishes the air damping and improves the switch speed and operation voltage,the performances of a switch is incident to being influenced by outside environment.This study is very useful for the optimized design of RF MEMS capacitive switches working in low vacuum.
A power amplifier MIC with power combining based on AlGaN/GaN HEMTs was fabricated and measured.The amplifier consists of four 10×120μm transistors.A Wilkinson splitters and combining were used to divide and combine the power.By biasing the amplifier at VDS=40V,IDS=0.9A, a maximum CW output power of 41.4dBm with a maximum power added efficiency (PAE) of 32.54% and a power combine efficiency of 69% was achieved at 5.4GHz.
A novel wide-range CMOS variable gain amplifier (VGA) topology is presented.The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range of 80dB while using a single variable-gain stage.Temperature-compensation and decibel-linear gain characteristic are achieved by using a control circuit that provides a gain error lower than ±1.5dB over the full temperature and gain ranges.Realized in 0.25μm CMOS technology,a prototype of the proposed VGA provides a total gain range of 64.5dB with 55.6dB-linear range,a P-1dB varying from -17.5 to 11.5dBm,and a 3dB-bandwith varying from 65 to 860MHz while dissipating 16.5mW from a 2.5V supply voltage.
The design and implementation of a CMOS LC VCO with 3.2～6.1GHz tuning range are presented.This is achieved by enhancing the tuning capability of the binary-weighted band-switching MIM capacitor.The circuit has been implemented in a 0.18μm RF/Mixed-Signal CMOS process.The measured phase noise is -101.67dBc/Hz at 1MHz offset from a 5.5GHz carrier,and the VCO core draws 9.69mA current from a 1.8V supply.
We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling.Experimental results show that the leakage power consumption is underestimated by 52% if thermal effects are omitted.Furthermore,an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling.Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.
A 2.5Gb/s clock and data recovery (CDR) circuit is designed and realized in TSMC’s standard 0.18μm CMOS process.The clock recovery is based on a PLL.For phase noise optimization,a dynamic phase and frequency detector (PFD) is used in the PLL.The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is -111dBc/Hz at 10kHz offset.The rms jitter of the recovered 2.5Gb/s data is 3.3ps.The power consumption is 120mW.
Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied.Its structure is analyzed and the main parameters are proposed.A monolithic LC-tuned voltage controlled oscillator (LC-VCO) with low phase noise is fabricated with TSMC 0.18μm RF (radio frequency) CMOS technology.The measured phase noise is -117dBc/Hz at 4MHz off the center frequency of 4.189GHz.A down-scaling circuit with low power dissipation was fabricated in a TSMC 0.18μm mixed-signal CMOS process.The measured results show that the IC can work well under a 1.8V power supply.Its total power dissipation is only 13mW.
We apply a magnetic field B along the axis of an n-type doped weakly-coupled GaAs/AlAs superlattice (SL) to investigate the carrier transport in a low electric field.An abnormal enhancement of the current intensity by perpendicular B is observed for the ground state transport.Electron tunneling or hopping conduction via elastic scattering at low Bswitches over into resonant tunneling at higher B because in the latter case the electrons only partially occupy the first Landau level.
Si-clathrate compounds,n-type Ba8Ga16ZnxSi30-x(x=0,1,2,3,4),are synthesized by using the solid-state reaction method and the melting method.The effects of the replacement of Si with Zn on the structure and the electrical transmission characteristics are investigated for n-type Ba8Ga16ZnxSi30-x.The results indicate that the sample with the value of x =1 has the maximal bond angle distortion Δθ,Δθ=4.4. .The electrical conductivity of samples with x=0,2,4 is higher than that of samples with x=1,3.Among the samples,the electrical conductivity of Ba8Ga16Zn1Si29 is the lowest.The samples with x=0,2,4 exhibit a higher Seebeck coefficient than that of samples with x=1,3,and the value of the Seebeck coefficient decreases with the increase of the Zn composition.The power factor of Ba8Ga16Zn2Si28 compound is as large as 1.03e-3W/(m·K2) at 1000K.
CdTe thin films were etched with a mixture of nitric-phosphoric acid (NP) in water.A dilute solution of bromine in methanol (BM) was also applied to CdTe thin films for comparison.The effects of NP acid and BM pretreatments on the material properties were investigated.Then four back contact materials were deposited on the CdTe thin films etched with two surface pretreatments.A novel back-contact technique was proposed.Furthermore,two CdTe solar cells with high performance back contacts were measured from C-Vmeasurements and analyzed using energy band structure.
Resonant tunneling diodes (RTDs) with different barrier thicknesses were grown by molecular beam epitaxy (MBE) on semi-insulating InP substrates.The highest peak-to-valley current ratio is 18.39 at room temperature.The relationship between RTD direct current characteristics with barrier thickness,well and sub-well thickness,spacer thickness,and doping density are analyzed and discussed.
An 18-element small-signal equivalent circuit for GaN HEMTs is discussed.Two additional feedback resistances are incorporated into the intrinsic device to account for the leakage current from gate to source and drain compared with the conventional circuit structure.Furthermore,considering the distributed effects in high frequency applications,a new 20-element model is proposed and a corresponding direct extraction method is developed.The new modeling approach for GaN HEMTs is verified by comparing the simulated small-signal S-parameter,over wide frequency and bias ranges,with the measured data of a GaN HEMT with a 1μm gate length and a 200μm gate width.The results show that the 20-element modeling system is more accurate and stable in the high frequency application than that of the 18-element lumped model.
The research and fabrication of an InP-based AlAs/In0.53Ga0.47As double barrier single well resonant tunneling diode (RTD) device are reported.The material structure was grown on (001) semi-induction InP wafer by molecular beam epitaxy,and the device was fabricated with a mesa structure.The DC characteristics for the RTD sample were measured at room temperature.The peak-to-valley current ratio was 7.4,and the peak current density JP was 1.06e2A/cm2.
The timing characteristics of RTS in SMIC 90nm CMOS nMOS devices with a 1.4nm gate oxide are measured and analyzed.It is proposed that tunneling through the gate dielectric of electrons in the conduction band is responsible for RTS noise,and a detailed description of the mechanics of the RTS noise under high gate bias is presented.Also,based on the research from IMEC and TSMC,a physical model of the timing characteristics of the RTS noise versus gate bias is constructed,and the consistency of the experiment and the simulation shows the effectiveness of this model.The research in this paper provides new measures for dynamic characterization of border traps and the reliability of deep sub-micron MOS devices.
Based on an architecture model of a two-tone signal, we analyze the effects of the finite envelope modulator bandwidth and differential delay between envelope signal and RF phase signal on the intermodulation distortion (IMD), and derive a general simplified model that is much closer to laboratory measurements. This model overcomes the limitation of Raab’s model, which can only solve two specific instances:zero differential delay and infinite bandwidth of the envelope path. A contour map derived from the general model can help designers choose circuit parameters quickly and accurately. Finally, an envelope elimination and restoration RF power amplifier (EER RF PA) operating at 935MHz with a GSM/EDGE signal source is applied to demonstrate how to use the analysis method presented here.
An 850nm monolithically integrated optical receiver front end is developed with a 0.5μm GaAs PHEMT process,which comprises a metal-semiconductor-metal (MSM) photodetector and a distributed amplifier.The photodetector has a photosensitive area and capacitance of 50μm×50μm and 0.17pF,respectively,as well as a dark current of less than 17nA under a bias of 4V.The distributed amplifier has a -3dB bandwidth close to 20GHz,with a transimpedance of 46dBΩ.In the range of 50MHz ~16GHz,both the input and output voltage standing wave ratio are less than 2.The measured noise figure varies form 3.03 to 6.5dB.The output eye diagrams for 2.5Gb/s and 5Gb/s NRZ pseudorandom binary sequence are also obtained.
Schottky barrier GaN ultraviolet detectors are fabricated with a very low reverse saturation current density of 5.5e-14A/cm2 and very large Schottky barrier height of 1.18eV.The spectral responsivity of the detector at 0V and reverse bias was measured.There are no significant changes in the responsivity at reverse bias voltage.The peak responsivity of the detector at 0V is 0.214A/W at a wavelength of 3582nm.The spatial photoresponse was measured by 359nm light beam scanning across the photosensitive area of the detector at 0V and -3V.The changes in the photoresponse are no more than 0.6% in the central portion of the photosensitive area at biases of 0V and -3V.The Schottky barrier height decreases with near-band-edge ultraviolet illumination,especially near the transparent Schottky contact and near the Schottky contact pad.The open circuit voltage of the detector with 368nm light illumination is less than that with both 368 and 810nm light illumination, but the photocurrent of the detector with 368nm light illumination is nearly equal to that with both 368 and 810nm light illumination at 0V. The variation in occupied trap concentration at the GaN surface is estimated to be 8.4e10 cm-2 by the difference of the open circuit voltage of the detector between cases of illumination with 368nm light and 368nm+810nm light.
Based on study of the principle of OCDs and the theory of 1/f noise,we present a CTR model and 1/f noise model of OCDs.The electric noise and CTR of OCDs are measured over a wide range of currents,and the experimental results agree well with the proposed models.By integrating the CTR model and 1/f noise model,a relationship between CTR degradation and 1/f noise is further studied.The relationship is used to analyze irradiation experiments,and results agree precisely with the theoretical model.This proves by theory and experiment that the larger the noise magnitude,the closer the current exponent is to 2,leading to the degradation of device reliability and significant degradation of the CTR.Consequently,it is shown that noise can represent not only the CTR of OCDs but also the reliability of the device.
A 0～5GHz single-pole double-throw (SPDT) switching circuit using lateral metal-contacting MEMS switches is demonstrated. The MEMS switch consists of a set of quasi-finite ground coplanar waveguide (FGCPW) transmission lines and a right and left swing cantilever beam. A folded cantilever beam is proposed to reduce the driving voltage,and the structure is proven by theoretical analysis and simulation. The switches were successfully fabricated using the MetalMUMP process.At 5GHz,the measured insertion loss of the SPDT switching circuit is below 0.8dB,the return loss is higher than 20dB,and the isolation is as high as 40dB. The smallest pull-in voltage of the switches is 33V.
This paper presents a novel micro-structure ethanol gas sensor.The heater electrodes and signal electrodes were designed on the same plane in order to reduce cross-talk and make the fabrication easier.The whole design has been simulated using a 3D electro-thermo-mechanical finite element model through Ansys.The nano complex oxide La0.7Sr0.3FeO3 is employed to act as sensitive material coated on the surface of the substrate. Experimental results show that the sensitivity of this novel sensor is 8.0 when the concentration of the ethanol is 500ppm, the power consumption is approximately two thirds of that of commercial sintering gas sensors, the response time is about 1.5s, and the recovery time is about 2.5s.
A 1-write-port 8-read-port 32×32-bit register file has been designed in 1.8V 0.18μm CMOS technology. Low-swing bit-lines are used for both read and write operations. Together with the use of novel memory cells, high speed sensor amplifiers, self-reset address decoders, SCL circuits, clock gating, and delicate time control circuits, it has achieved both high speed and low power. Post-layout simulations in 1.8V with HSPICE indicate a write time of 1.7ns and a read time of 1.32ns. The power dissipation is 70mW for all 9 ports at 500MHz.
The cross-sectional microstructures of joints with Sn37Pb, Sn3.0Ag0.5Cu, and Sn0.7Cu under electromigration were investigated. At a temperature of 60℃ and current density of 1e3A/cm2,after 187h, micro-voids form at the electron entrance of the Sn37Pb solder/Cu interface, and strip-like Pb enriches the anode side. For Sn3.0Ag0.5Cu, electromigration only results in the dissolution of the substrate Cu at the cathode side, and the thicknesses of the Cu6Sn5 and Cu3Sn intermetallic layers at the anode side are markedly bigger than the counterparts at the cathode. Likewise, the Cu6Sn5 and Cu3Sn intermetallic layers at the anode side are thicker than the counterparts at the cathode, indicating that EM also occurs in the Sn0.7Cu joint, but little Cu dissolves into the solder at the cathode side.
