Periodic disposed quantum dot arrays are very useful for the large scale integration of single electron devices. Gold quantum dot arrays were self-assembled inside pore channels of ordered amino-functionalized mesoporous silica thin films, employing the neutralization reaction between chloroauric acid and amino groups. The diameters of quantum dots are controlled via changing the aperture of pore channels from 2.3 to 8.3 nm, which are characterized by HRTEM, SEM and FT-IR. UV-vis absorption spectra of gold nanoparticle/mesoporous silica composite thin films exhibit a blue shift and intensity drop of the absorption peak as the aperture of mesopores decreases, which represents the energy level change of quantum dot arrays due to the quantum size effect.

A process methodology has been adopted to transfer GaN thin films grown on sapphire substrates to Si substrates using metal bonding and laser lift-off techniques. After bonding, a single KrF (248 nm) excimer laser pulse was directed through the transparent sapphire substrates followed by low-temperature heat treatment to remove the substrates. The influence of bonding temperature and energy density of the excimer laser on the structure and optical properties of GaN films were investigated systemically. Atomic force microscopy, X-ray diffraction and photoluminescence measurements showed that (1) the quality of the GaN film was higher at a lower bonding temperature and lower energy density; (2) the threshold of the energy density of the excimer laser lift-off GaN was 300 mJ/cm2. The root-mean-square roughness of the transferred GaN surface was about 50 nm at a bonding temperature of 400 ℃.

The intrinsic defects in epitaxial semi-insulating 4H-SiC prepared by low pressure chemical vapor deposition (LPCVD) are studied by electron spin resonance (ESR) with different illumination times. The results show that the intrinsic defects in as-grown 4H-SiC consist of carbon vacancy (VC) and complex-compounds-related VC. There are two other apexes presented in the ESR spectra after illumination by Xe light, which are likely to be VSi and VCCSi. Illumination time changes the relative density of intrinsic defects in 4H-SiC; the relative density of intrinsic defects reaches a maximum when the illumination time is 2.5 min, and the ratio of VC to complex compounds is minimized simultaneously. It can be deduced that some VSi may be transformed to the complex-compounds-related VC because of the illumination.

The stresses, structural and electrical properties of n-type Si-doped GaN films grown by metalorganic chemical vapor deposition (MOCVD) are systemically studied. It is suggested that the main stress relaxation is induced by bending dislocations in low doping samples. But for higher doping samples, as the Si doping concentration increases, the in-plane stresses in the grown films are quickly relaxed due to the rapid increase of the edge dislocation densities. Hall effect measurements reveal that the carrier mobility first increases rapidly and then decreases with increasing Si doping concentration. This phenomenon is attributed to the interaction between various scattering process. It is suggested that the dominant scattering process is defect scattering for low doping samples and ionized impurity scattering for high doping samples.

Surface treatment plays an important role in the process of making high performance AlGaN/GaN HEMTs. A clean surface is critical for enhancing device performance and long-term reliability. By experimenting with different surface treatment methods, we find that using UV/ozone treatment significantly influences the electrical properties of Ohmic contacts and Schottky contacts. According to these experimental phenomena and X-ray photoelectron spectroscopy surface analysis results, the effect of the UV/ozone treatment and the reason that it influences the Ohmic/Schottky contact characteristics of AlGaN/GaN HEMTs is investigated.

The fabrication of enhancement-mode AlGaN/GaN HEMTs by fluorine plasma treatment on sapphire substrates is reported. A new method is used to fabricate devices with different fluorine plasma RF power treatments on one wafer to avoid differences between different wafers. The plasma-treated gate regions of devices treated with different fluorine plasma RF powers were separately opened by a step-and-repeat system. The properties of these devices are compared and analyzed. The devices with 150 W fluorine plasma treatment power and with 0.6 μm gate-length exhibited a threshold voltage of 0.57 V, a maximum drain current of 501 mA/mm, a maximum transconductance of 210 mS/mm, a current gain cutoff frequency of 19.4 GHz and a maximum oscillation frequency of 26 GHz. An excessive fluorine plasma treatment power of 250Wresults in a small maximum drain current, which can be attributed to the implantation of fluorine plasma in the channel.

The accurate extraction of AlGaN/GaN HEMT small-signal models, which is an important step in large-signal modeling, can exactly reflect the microwave performance of the physical structure of the device. A new method of extracting the parasitic elements is presented, and an open dummy structure is introduced to obtain the parasitic capacitances. With a Schottky resistor in the gate, a new method is developed to extract Rg. In order to characterize the changes of the depletion region under various drain voltages, the drain delay factor is involved in the output conductance of the device. Compared to the traditional method, the fitting of S11 and S22 is improved, and fT and fmax can be better predicted. The validity of the proposed method is verified with excellent correlation between the measured and simulated S-parameters in the range of 0.1 to 26.1 GHz.

A clear correspondence between the gated-diode generation–recombination (R–G) current and the performance degradation of an SOI n-channel MOS transistor after F–N stress tests has been demonstrated. Due to the increase of interface traps after F–N stress tests, the R–G current of the gated-diode in the SOI-MOSFET architecture increases while the performance characteristics of the MOSFET transistor such as the saturation drain current and sub-threshold slope are degraded. From a series of experimental measurements of the gated-diode and SOI-MOSFET DC characteristics, a linear decrease of the drain saturation current and increase of the threshold voltage as well as a like-line rise of the sub-threshold swing and a corresponding degradation in the trans-conductance are also observed. These results provide theoretical and experimental evidence for us to use the gated-diode tool to monitor SOI-MOSFET degradation.

An improved hot carrier injection (HCI) degradation model was proposed based on interface trap generation and oxide charge injection theory. It was evident that the degradation behavior of electric parameters such as Idlin, Idsat, Gm and Vt fitted well with this model. Devices were prepared with 0.35 μm technology and different LDD processes. Idlin and Idsat after HCI stress were analyzed with the improved model. The effects of interface trap generation and oxide charge injection on device degradation were extracted, and the charge injection site could be obtained by this method. The work provides important information to device designers and process engineers.

A self-built accurate and flexible large-signal model based on an analysis of the characteristics of InP double heterojunction bipolar transistors (DHBTs) is implemented as a seven-port symbolically defined device (SDD) in Agilent ADS. The model accounts for most physical phenomena including the self-heating effect, Kirk effect, soft knee effect, base collector capacitance and collector transit time. The validity and the accuracy of the large-signal model are assessed by comparing the simulation with the measurement of DC, multi-bias small signal S parameters for InP DHBTs.

Physical device models and numerical processing methods are presented to simulate a linear buried channel charge coupled devices (CCDs). The dynamic transfer process of CCD is carried out by a three-phase clock pulse driver. By using the semiconductor device simulation software MEDICI, dynamic transfer pictures of signal charges cells, electron concentration and electrostatic potential are presented. The key parameters of CCD such as charge transfer efficiency (CTE) and dark electrons are numerically simulated. The simulation results agree with the theoretic and experimental results.

In wireless mobile communications and wireless local area networks (WLAN), advanced InGaP HBT with power amplifiers are key components. In this paper, the microwave large signal dynamic waveform characteristics of an advanced InGaP HBT are investigated experimentally for 5.8 GHz power amplifier applications. The microwave large signal waveform distortions at various input power levels, especially at large signal level, are investigated and the reasons are analyzed. The output power saturation is also explained. These analyses will be useful for power amplifier designs.

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.

To drive the backplane of a liquid crystal display device and achieve different kinds of grey levels, a high-slew-rate operational amplifier with constant-gm input stage is presented. A Zener-diode structure is inserted between the tails of the complementary input pairs to keep the gm of the input stage constant. A novel slew rate enhancement circuit is implemented to achieve a very high slew rate. The chip has been implemented in a 0.5 μm CMOS process and the chip area of the operational amplifier circuit is 0.11 mm2. The testing results indicate that in the 5–8 V input range, the maximum gm fluctuation is only 4.2%. The result exhibits a high slew rate of 111 V/ s and 102 V/ s for the rising and falling edges under a 20 pF capacitance load, and the low frequency gain is up to 109 dB with a phase margin of 70 ℃.

A fully integrated low power RF transmitter for a WiMedia 3.1–4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between –10.7 and –3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18 μm RF CMOS process with an area of 1.74 mm2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10^–9. The chip dissipates 60 mW under a single 3.3 V supply.

This paper presents a microelectronic system which is capable of making a signal record and functional electric stimulation of an injured spinal cord. As a requirement of implantable engineering for the regeneration microelectronic system, the system is of low noise, low power, small size and high performance. A front-end circuit and two high performance OPAs (operational amplifiers) have been designed for the system with different functions, and the two OPAs are a low-noise low-power two-stage OPA and a constant-gm RTR input and output OPA. The system has been realized in CSMC 0.5-μm CMOS technology. The test results show that the system satisfies the demands of neuron signal regeneration.

In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented. The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescent current in skip mode for light loads, and produces low ripple in linear mode for heavy loads, which closes the gap between linear mode and skip mode with active regulation; a multi-mode charge pump employing the technique has been implemented in the UMC 0.6- m-BCD process. The results indicate that the charge pump works well and effectively; it has low ripple with special regulation, and minimizes the size of the capacitance, then decreases the area of the PCB board. The adjustable output of the positive charge pump is 10–30 V, and the maximum output ripple is 100 mV when the load current is 200 mA. The line regulation is 0.2%/V, and load regulation is 0.075%.

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.

Energy harvesting systems stimulate the development of power management for low power consumption applications. Improving the converter efficiency of power management circuits has become a significant issue in energy harvesting system design. This paper presents a variable step-down conversion ratio switched capacitor (SC) DC–DC converter to advance the converter efficiency of charge on the stored capacitor in a wireless monitoring system of orthopedic implants. The converter is designed to work at 1 MHz switching frequency and achieves 15 to 2 V conversion. Measurement results show that the converter efficiency can reach 42% including all circuit power consumption, which is much higher than previous work.

A radiation-hardened-by-design (RHBD) technique for phase-locked loops (PLLs) has been developed for single-event transient (SET) mitigation. By presenting a novel SET-resistant complementary current limiter (CCL) and implementing it between the charge pump (CP) and the loop filter (LPF), the PLL’s single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 93.1% and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.

Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.

A 1-V third order one-bit continuous-time (CT) Σ∆ modulator is presented. Designed in the SMIC mixed-signal 0.13-µm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT Σ∆ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm2.

A novel topology of current mirror (CM) with tunable output current is proposed. Two methods for output current tuning are presented. The first one utilizes an analog input voltage for linear current output, and the second one has an N-bit digital input signal for 2N un-continuous current outputs. A linearization method for low noise amplifier (LNA) is proposed and realized with this tunable CM. As the provider of the bias current, the CM has brought the LNA a lower NF (noise figure) and a higher IIP3 (input-referred third-order intercept point) compared with a conventional one. The experimental results show that the LNA achieves 1.47 dB NF and +19.83 dBm IIP3 at 860 MHz.

This paper describes an 8-bit 125MHz low-power CMOS fully-folding analog-to-digital converter (ADC). A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5 μm CMOS technology and occupies a die area of 2 × 1.5 mm2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/–0.8 LSB and 0.9 LSB/–1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HNO3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C–V and Jg–Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.