p-ZnxMg1-xO:Na/n-ZnO p-n junction light emitting diode (LED) was produced on n-ZnO (0001) single-crystal substrate using pulsed laser deposition. The realization of band gap engineering was achieved by the incorporation of Mg in ZnO layers and was confirmed by photoluminescence spectrum. The p-type ZnxMg1-xO:Na film with low resistance was obtained at 500 ℃ and in which, Na has taken effect evidenced by Hall and X-ray photoelectron spectroscopy measurements. The current–voltage curve of LED showed a rectifying behavior and obvious electroluminescence was realized by feeding a direct current up to 40 mA. Furthermore, its structural and electric characters are discussed as well.

A variational method combined with solving the force balance equation is adopted to investigate the influence of strain and hydrostatic pressure on electronic mobility in a strained wurtzite AlN/GaN heterojunction byconsidering the scattering of optical-phonons in a temperature ranges from 250 to 600 K. The effects of conductionband bending and an interface barrier are also considered in our calculation. The results show that electronic mobilitydecreases with increasing hydrostatic pressure when the electronic density varies from 1.0E12 to 6.5E2 cm–2. The strain at the heterojunction interface also reduces the electronic mobility, whereas the pressure influencebecomes weaker when strain is taken into account. The effect of strain and pressure becomes more obvious as temperatureincreases. The mobility first increases and then decreases significantly, whereas the strain and hydrostaticpressure reduce this trend as the electronic density increases at a given temperature (300 K). The results also indicatethat scattering from half space phonon modes in the channel side plays a dominant role in mobility.

To evaluate the charge transport properties of as-grown high resistivity CdZnTe crystals doped with In/Al, the α particle spectroscopic response was measured using an un-collimated ²⁴¹Am (5.48 MeV) radioactive sourceat room temperature. The electron mobility lifetime products (µτ)_e of the CdZnTe crystals were predicted by fittingplots of photo-peak position versus electrical field strength using the single carrier Hecht equation. A TOF techniquewas employed to evaluate the electron mobility for CdZnTe crystals. The mobility was obtained by fitting the electrondrift velocities as a function of the electrical field strengths, where the drift velocities were achieved by analyzing therise-time distributions of the voltage pulses formed by a preamplifier. A fabricated CdZnTe planar detector based ona low In concentration doped CdZnTe crystal with (µτ)_e = 2.3 × 10^-3 cm²/V and µ_e = 1000 cm²/(V·s), respectively, exhibits an excellent γ-ray spectral resolution of 6.4% (FWHM = 3.8 keV) for an un-collimated ²⁴¹Am @ 59.54 keV isotope.

With HfON filling the holes in porous silicon (PS), films with improved photoluminescence (PL) at roomtemperature were prepared. A strong blue peak at 425 nm and a red peak at 690 nm were observed in PL spectra. It is believed that the quantum-limited effect (QLE) and the polycrystalline structure of HfON is responsible forthe observed PL peaks. The stoichiometric proportion of N/O in the HfON layer has also a great influence on theintensity of blue light emission. Finally, the temperature quenching effect was observed to be greatly weakened forthe incorporation of HfON.

HfOxNy–HfO2–HfOxNy sandwich-stack (SS) film was investigated in comparison with HfO2 film ofthe same thickness. Higher thermal stability and better surface morphology can be observed for the SS film. Thisstructure also shows stronger immunity to interfacial oxidation compared with HfO2 film. Meanwhile, unlike theHfOxNy dielectric, the capacitance performance of SS film was not worse (but was even better) than a pure HfO2 film of the same thickness. The SS structure appears to be a promising high-k gate dielectric compared with bothpure HfOxNy and HfO2 dielectrics for future ULSI devices. Additionally, PDA treatment plays an important rolein improving the characteristics of SS film, which is confirmed by effective channel electron mobility and stressinduced leakage current (SILC) investigations.

A metal–insulator–silicon (MIS) capacitor with hemi-spherical grained poly atomic layer deposition (ALD) deposited Al2O3 and multi-layered chemical vapor deposition (CVD) TiN structure is fabricated. The impactof the deposition process and post treatment condition on the MIS capacitor’s time-dependent dielectric breakdown(TDDB) performance is also studied. With an optimized process, it is confirmed by Auger electron spectroscopy andsecondary ion mass spectrometry analysis that the Al(CH3)3/O3-based ALD Al2O3 dielectric film is carbon free andthe hydrogen content is as low as 9 × 10¹⁹ cm^-3. The top electrode TiN is obtained by multi-layered TiCl4/NH3 CVD deposited TiN followed by 120 s post NH3 treatment after each layer. This has higher diffusion barrier in preventingimpurity diffusion through TiN into the Al2O3 dielectric due to its smaller grain size. As shown in energy dispersive X-ray analysis, there is no chlorine residue in the MIS capacitor structure. The leakage current of the capacitor islower than 1 × 10^-12 A/cm² . No early failures under stress conditions are found in its TDDB test. The novel MIS capacitor is proven to have excellent reliability for advanced DRAM technology.

PZT thin films were successfully prepared through sol–gel. The annealing temperature was confirmed through DTA analyzing. The trigonal and tetragonal phase transition was analyzed through Raman scattering. The intensity of the A1(2TO) mode and the A1(3TO)T mode were enhanced with the increase of the annealing temperature. So, the conclusions were obtained that the trigonal phase turned into a tetragonal phase as temperature increased.

High concentrations of Si and Zn were implanted into (0001) AlN bulk crystal grown by the self-seeded physical vapor transport (PVT) method. Cathode luminescence (CL) and photoluminescence (PL) spectroscopy were used to investigate the defects and properties of the implanted AlN. PL spectra of the implanted AlN are dominated by a broad near-band luminescence peak between 200 and 254 nm. After high temperature annealing, implantationinduced lattice damages are recovered and the PL intensity increases significantly, suggesting that the implantedimpurity Si and Zn occupy lattice site of Al. CL results imply that a 457 nm peak is Al vacancy related. Resistanceof the AlN samples is still very high after annealing, indicating a low electrical activation efficiency of the impurityin AlN single crystal.

The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition (LPCVD) are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600–800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems (MEMS) devices, especially in high resonance frequency (high-f) and high quality factor (high-Q) MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2–5 mΩ·cm. These reported approaches avoid the high temperature annealing process (> 1000 ℃), and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.

Composites consisting of hydrogenated amorphous silicon (a-Si: H, inorganic) and zinc phthalocyanine (ZnPc, organic) were prepared by vacuum evaporation of ZnPc and sequential deposition amorphous silicon via plasma enhanced chemical vapor deposition (PECVD). The optical and electrical properties of the composite film have been investigated. The results demonstrate that ZnPc can endure the temperature and bombardment of the PECVD plasma and photoconductivity of the composite film was improved by 89.9% compared to pure a-Si: Hfilm. Electron mobility-lifetime products µ_T of the composite film were increased by nearly one order of magnitude from 6.96 × 10^-7 to 5.08 ×
10^-6 cm²/V. Combined with photoconductivity spectra of the composites and pure a-Si:H, we tentatively elucidate the improvement in photoconductivity of the composite film.

ZnS whiskers were successfully synthesized by the chemical vapor deposition method with the assistance of CuS micro-spheres. The composition, morphology and structure of the samples were characterized by X-ray diffraction, X-ray energy dispersive spectroscopy, scanning electron microscopy, and the temperature-dependent photoluminescence (PL) spectrum over a temperature range from 10 to 250 K was studied. The results show that the as-synthesized ZnS whiskers have an average length of 0.3 mm and diameter of 2.5 µm with a cubic zinc-blende structure. There exist three emission bands in the blue, green and yellow regions, and the emission mechanism is discussed. As the temperature increases, the temperature-dependent PL spectrum shows anomalous behavior, where distinct inverted V-shaped characters of blue and green emission integrated intensity and an inconspicuous S-shape of blue emission peak energy are observed. The transition mechanism is discussed.

A GaSb crystal incorporated with Mn has been grown by the Bridgman method on the Polizon facility onboard the FOTON-M3 spacecraft. Structural defects and growth striations have been successfully revealed by the chemical etching method. By calculating various parameters of the convection, the striation patterns can be explained, and the critical value of the Taylor number, which characterizes the convective condition of the rotating magnetic field induced azimuthal flow, was shown. The stresses generated during crystal growth can be reflected by the observations of etch pit distribution and other structural defects. Suggestions for improving the space experiment to improve the quality of the crystal are given.

Silicon materials compensated by deep level impurities such as nickel and gold have negative temperature coefficient (NTC) characteristics. In this work, n-type silicon wafers are smeared by nickel chloride ethanol solution and gold chloric acid ethanol solution, and subsequently put in the opening environment to heat. The electrical resistance and B-value of the thermistors made by this silicon material are measured and analyzed. When the silicon surface concentration of gold atoms is 2 × 10^-6 mol/cm², the uniformity of the single-crystal silicon material is optimal. When the diffusion temperature is between 900 and 1000 ℃, a material with high B-value and low electrical resistivity is obtained. The B–T and R–T change laws calculated by the theory of semiconductor deep level energy are basically consistent with the experimental results.

The effect of Si (100) surface S passivation was investigated. A thick film with a high roughness value was formed on the Si surface treated by (NH₄)₂S solution, which was attributed to physical adsorption of S atoms. SEM and XPS analyses reveal that Si surface atoms were chemically bonded with S atoms after Si surface treatment in NH₄OH and (NH₄)₂S mixing solution. This induces a more ideal value for the Schottky barrier height compared with a diode treated only by HF solution, indicating that surface states originating from dangling bonds are passivated with S atoms.

The fabrication and photoelectrical characteristics of suspended ZnO nanowire (NW) field-effect transistors(FETs) are presented. Single-crystal ZnO NWs are synthesized by a hydrothermal method. The fabricated FETs exhibit excellent performance. When V_ds = 2.5 V, the peak transconductance of the FETs is 0.396 µS, the average electron mobility is 50.17 cm²/(V·s), the resistivity is 0.96 × 10² Ω·cm at V_gs = 0 V, and the current on/off ratio (I_onI_off) is approximately 105. ZnO NW-FET devices exposed to ultraviolet radiation (2.5 µW/cm²) exhibit punchthrough and threshold voltage (V_th) shift (from –0.6 V to +0.7 V) and a decrease by almost half of the source–drain current (I_ds, from 560 nA to 320 nA) due to drain-induced barrier lowering. Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.

A semi-empirical analytic model for the threshold voltage instability of a MOSFET is derived from Shockley–Read–Hall (SRH) statistics to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression for the filled trap densityin terms of dynamic time is derived from SRH statistics. The semi-empirical analytic model for the threshold voltage instability is developed based on MOSFET device physics between the threshold voltage and the induced trapdensity. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.

The advent of fully integrated GaN PA-LNA circuits makes it meaningful to investigate the noise performance under high drain bias. However, noise performance of AlGaN/GaN HEMTs under high bias has not received worldwide attention in theoretical studies due to its complicated mechanisms. The noise value is moderately higher and its rate of increase is fast with increasing high voltage. In this paper, several possible mechanisms are proposed to be responsible for it. Impact ionization under high electric field incurs great fluctuation of carrier density, which increases the drain diffusion noise. Besides, higher gate leakage current related shot noise and a more severe selfheating effect are also contributors to the noise increase at high bias. Analysis from macroscopic and microscopic perspectives can help us to design new device structures to improve noise performance of AlGaN/GaN HEMTs under high bias.

High frequency intrinsic small-signal model parameter extraction for microwave SiGe heterojunction bipolar transistors is studied, with a focus on the main feedback elements including the emitter series resistor, internal and external base–collector capacitors as well as the base series resistor, all of which are important in determining the behavior of the device equivalent circuit. In accordance with the respective features of definition of the Y- and Z parameters, a novel combined use of them succeeds in reasonably simplifying the device equivalent circuit and thus decoupling the extraction of base–collector capacitances from other model parameters. As a result, a very simple direct extraction method is proposed. The proposed method is applied for determining the SiGe HBT small-signal model parameters by taking numerically simulated Y- and Z-parameters as nominal “measurement data” with the help of a Taurus-device simulator. The validity of the method is preliminarily confirmed by the observation of certain linear relations of device frequency behavior as predicted by the corresponding theoretical analysis. Furthermore, theextraction results can be used to reasonably account for the dependence of the extracted model parameters on device geometry and process parameters, reflecting the explicit physical meanings of parameters, and especially revealing the distributed nature of the base series resistor and its complex interactions with base–collector capacitors. Finally, the accuracy of our model parameter extraction method is further validated by comparing the modeled and simulated S -parameters as a function of frequency.

A new double gate SOI LDMOS with a step doping profile in the drift region is proposed. The structure is characterized by one surface gate and another embedded gate under the P-body region. The broadened current flow path and the majority carrier accumulation layer on the side wall of the embedded gate reduce the specificon-resistance (R_on,sp). The electric field distribution is improved due to the embedded gate and step doping profile, resulting in a high breakdown voltage (BV) and low R_on,sp. The influences of device parameters on BV and R_on,sp, spare investigated by simulation. The results indicate that BV is increased by 35.2% and R_on,sp is decreased by 35.1% compared to a conventional SOI LDMOS.

Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-µm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-µm silicide CMOS technology are also presented.

The mode of a novel SiGe-OI optical waveguide is analyzed, and its single-mode conditions are derived. The Ge content and structure parameters of SiGe-OI optical waveguides are respectively optimized. Under an operation wavelength of 1300 nm, the structures of SiGe-OI rib optical waveguides are built and analyzed with Optiwave software, and the optical field and transmission losses of the SiGe-OI rib optical waveguides are analyzed. The optimization results show that when the structure parameters H, h, W are respectively 500 nm, 250 nm, 500 nm and the Ge content is 5%, the total power loss of SiGe-OI rib waveguides is 0.3683 dB/cm considering the loss of radiation outside the waveguides and materials, which is less than the traditional value of 0.5 dB/cm. The analytical technique for SiGe-OI optical waveguides and structure parameters computed by this paper are proved to be accurate and computationally efficient compared with the beam propagation method (BPM) and the experimental results.

:A kind of AlGaInP light emitting diode (LED) with surface anti-reflecting structure has been introduced to solve the problems of low light efficiency and restricted luminous intensity. The new structure can be demonstrated theoretically and experimentally, and LEDs with the new structure have higher on-axis luminous intensity and larger saturation current than conventional LEDs and LEDs with ITO film only, which is caused by higher external quantum efficiency and also higher internal quantum efficiency. The new LEDs are especially suitable for working at large injected currents.

Amorphous/crystalline silicon heterostructure solar cells have been fabricated by hot wire chemical vapor deposition (HWCVD) on textured p-type substrates. The influence of chemical polish (CP) etching and the post annealing process on the solar cell performance have been studied. The CP treatment leads to a reduction of stress in the i-layer by the slight rounding of the pyramid peaks, therefore improving the deposition coverage and the contact by each layer, which is beneficial for the performance of the solar cells. An optimized etching time of 10–15 s has been obtained. A post annealing process leads to a considerably improved open voltage (V_oc), filled factor (FF), and conversion efficiency (η) by restructuring the deposited film and reducing the series resistance. An efficiency of 15.14% is achieved that represents the highest result reported in China for an amorphous/crystalline heterostructure solar cells based on the textured p-type substrates.

Performance of concentrating photovoltaic/thermal system is researched by experiment and simulation calculation. The results show that the I–V curve of the GaAs cell array is better than that of crystal silicon sola rcell arrays and the exergy produced by 9.51% electrical efficiency of the GaAs solar cell array can reach 68.93% of the photovoltaic/thermal system. So improving the efficiency of solar cell arrays can introduce more exergy and the system value can be upgraded. At the same time, affecting factors of solar cell arrays such as series resistance, temperature and solar irradiance also have been analyzed. The output performance of a solar cell array with lowerseries resistance is better and the working temperature has a negative impact on the voltage in concentrating light intensity. The output power has a –20 W/V coefficient and so cooling fluid must be used. Both heat energy and electrical power are then obtained with a solar trough concentrating photovoltaic/thermal system.

Content addressable memory (CAM) is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N+2L+4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N+2L+5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.

A novel fully differential telescopic operational transconductance amplifier (OTA) is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18 µm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.

This paper presents the design of a 26–40 GHz monolithic doubly-balanced mixer for high-speed wireless communication. A modified Marchand balun is used to expand the bandwidth. A coupled line of the U section improves the port to port isolation and provides the IF-output port. The mixer was simulated and fabricated in 0.15-µm GaAs PHEMT technology; the measurement results agree well with the simulation results. The mixer achieves low conversion loss of 5.9 to 8.6 dB and high isolation over a 26–40 GHz RF/LO bandwidth and a DC-14 GHz IF bandwidth.

A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative g_m-cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 µm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5–9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply

An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 µm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order lowpass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730–5.340 MHz. The in-band third order harmonic input intercept point (IIP3) is 16.621 dBm, with 50 Ω as the source impedance. The input referred noise is about 47.455 µV_rms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm² and it can be utilized in GPS (global positioning system) and Bluetooth systems.

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-µm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/℃ and the power supply rejection ratio of output voltage without any filtering capacitor is –40 dB and –33 dB at 100 Hz and 10 MHz, respectively.

This paper introduces the design of a l.8 V low dropout voltage regulator (LDO) and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 µm CMOS technology. The measured result reveals that the LDO0s power supply rejection (PSR) is about −58 dB and –54 dB at 20 Hz and 1 kHz respectively, the response time is 4 µs and the quiescent current is 20 µA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.

A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture descriptionfile, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 µm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

This paper presents a low power cyclic analog-to-digital convertor (ADC) design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks (MDACs) and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully optimized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation (UMC) 0.18-µm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 µW in normal working mode and less than 150 nW in sleep mode.

A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop(PLL) calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implementedin a 0.18 µm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 µs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18 µm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter ofthe PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

This paper presents an implementation for improving muti-level cell NOR flash memory program throughput based on the channel hot electron (CHE) temperature characteristic. The CHE I_g temperature characteristic is analyzed theoretically with the Lucky electron model, and a temperature self-adaptive programming algorithm is proposed to increase I_g according to the on-die temperature. Experimental results show that the program throughput increases significantly from 1.1 MByte/s without temperature self-adaptive programming to 1.4 MByte/s with the proposed method at room temperature. This represents a 30% improvement and is 70 times faster than the program throughput in Ref. [1].

A novel wafer level bonding method based on Cu–Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu₆Sn₅ phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10^-9 atm cc/s are possible, meeting the demandsof MIL-STD-883E.