The effect of a high temperature AlN buffer layer grown by the initially alternating supply of ammonia (IASA) method on AlGaN/GaN heterostructures was studied. The use of AlN by the IASA method can effectively increase the crystalline quality and surface morphology of GaN. The mobility and concentration of 2DEG of AlGaN/GaN heterostuctures was also ameliorated.

Total dose hardened fully-depleted SOI materials are fabricated on separation by implanted oxygen (SIMOX) materials by silicon ion implantation and annealing. The ID–VG characteristics of pseudo-MOS transistors pre- and post-irradiation are tested with 60Co gamma rays. The chemical bonds and the structure of Si in the buried oxide are also studied by X-ray photoelectron spectroscopy and cross-sectional high-resolution transmission electron microscopy, respectively. The results show that Si nanocrystals in the buried oxide produced by ion implantation are efficient deep electron traps, which can significantly compensate positive charge buildup during irradiation. Si implantation can enhance the total-dose radiation tolerance of the fully-depleted SOI materials.

Two methods are proposed to fabricate stacked ruthenium (Ru) nanocrystals (NCs): rapid thermal annealing (RTA) for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2–4 nm and 3E12 cm–2 for the former method, compared to 3–7 nm and 2E12 cm–2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor (MOS) capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.

A 0.09 mm m-plane GaN film is deposited via hydride vapor phase epitaxy (HVPE) on a γ-LiAlO2 substrate. To research the anisotropy between directions with different angles with the c-axis in the m plane, photoluminescence (PL) measurements were carried out. The results show that the electronic transition was influenced by the electric field along the c-axis, which results in an obvious anisotropy, but the influence was weakened by the hexagonal symmetry along the c-axis.

This paper describes a method using both reduced pressure chemical vapor deposition (RPCVD) and ultrahigh vacuum chemical vapor deposition (UHVCVD) to grow a thin compressively strained Ge film. As the first step, low temperature RPCVD was used to grow a fully relaxed SiGe virtual substrate layer at 500 ℃ with a thickness of 135 nm, surface roughness of 0.3 nm, and Ge content of 77%. Then, low temperature UHVCVD was used to grow a high quality strained pure Ge film on the SiGe virtual substrate at 300 ℃ with a thickness of 9 nm, surface roughness of 0.4 nm, and threading dislocation density of ～105 cm–2. Finally, a very thin strained Si layer of 1.5–2 nm thickness was grown on the Ge layer at 550 ℃ for the purpose of passivation and protection. The whole epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.

Epitaxial growth on n-type 4H-SiC 8° off-oriented substrates with a size of 10 × 10 mm2 at different temperatures with various gas flow rates has been performed in a horizontal hot wall CVD reactor, using trichlorosilane (TCS) as a silicon precursor source together with ethylene as a carbon precursor source. The growth rate reached 23 μm/h and the optimal epilayer was obtained at 1600 ℃ with a TCS flow rate of 12 sccm in C/Si of 0.42, which has a good surface morphology with a low RMS of 0.64 nm in an area of 10 × 10 μm2. The homoepitaxial layer was obtained at 1500 ℃ with low growth rate (< 5 μm/h) and the 3C-SiC epilayers were obtained at 1650 ℃ with a growth rate of 60–70 μm/h. It is estimated that the structural properties of the epilayers have a relationship with the growth temperature and growth rate. Silicon droplets with different sizes are observed on the surface of the homoepitaxial layer in a low C/Si ratio of 0.32.

The thermal conductance of devices with different body contacts is studied. A new analytical expression is proposed. This expression can be used in parameter extraction, which gives both good efficiency and high precision. The ratio of thermal conductance of the body contact region to that of the body region is nearly equal to the ratio of the area. The use of an H shape gate body contact is suggested to aid power dissipation in SOI MOSFETs.

Gallium nitride (GaN) based light emitting diodes (LEDs) with a thick and high quality ZnO film as a current spreading layer grown by metal-source vapor phase epitaxy (MVPE) are fabricated successfully. Compared with GaN-based LEDs employing a Ni/Au or an indium tin oxide transparent current spreading layer, these LEDs show an enhancement of the external quantum efficiency of 93% and 35% at a forward current of 20 mA, respectively. The full width at half maximum of the ZnO (002) ω-scan rocking curve is 93 arcsec, which corresponds to a high crystal quality of the ZnO film. Optical microscopy and atomic force microscopy are used to observe the surface morphology of the ZnO film, and many regular hexagonal features are found. A pectrophotometer is used to study the different absorption properties between the ZnO film and the indium tin oxide film of the GaN LED. The mechanisms of the extraction quantum efficiency increase and the series resistance change of the GaN-based LEDs with ZnO transparent current spreading layers are analyzed.

The doping profile function of a double base epilayer is constructed according to drift–diffusion theory. Then an analytical model for the base transit time b is developed assuming a small-level injection based on the characteristics of the 4H-SiC material and the principle of the 4H-SiC BJTs. The device is numerically simulated and validated based on two-dimensional simulation models. The results show that the built-in electric field generated by the double base epilayer configuration can accelerate the carriers when transiting the base region and reduce the base transit time. From the simulation results, the base transit time reaches a minimal value when the ratio of L2/L1 is about 2.

Abstract: Quantum-dot laser diodes (QD-LDs) with a Fabry–Perot cavity and quantum-dot semiconductor optical amplifiers (QD-SOAs) with 7° tilted cavity were fabricated. The influence of a tilted cavity on optoelectronic active devices was also investigated. For the QD-LD, high performance was observed at room temperature. The threshold current was below 30 mA and the slope efficiency was 0.36 W/A. In contrast, the threshold current of the QD-SOA approached 1000 mA, which indicated that low facet reflectivity was obtained due to the tilted cavity design. A much more inverted carrier population was found in the QD-SOA active region at high operating current, thus offering a large optical gain and preserving the advantages of quantum dots in optical amplification and processing applications. Due to the inhomogeneity and excited state transition of quantum dots, the full width at half maximum of the electroluminescence spectrum of the QD-SOA was 81.6 nm at the injection current of 120 mA, which was ideal for broad bandwidth application in a wavelength division multiplexing system. In addition, there was more than one lasing peak in the lasing spectra of both devices and the separation of these peak positions was 6–8 nm, which is approximately equal to the homogeneous broadening of quantum dots.

It has been a scientific and technological problem in the field of microelectronics for several decades that the electrical method is used to measure the peak junction temperature of power transistors. Based on the excessive thermotaxis effect of low current, a novel electrical measurement method of the peak junction temperature is presented in this paper. The method is called the thermal spectrum analysis method of transistors, simply designated TSA (thermal spectrum analysis method). Unlike the common method which uses a single measuring current, TSA uses multi-step currents to measure temperature-sensitive parameters. Based on the excessive thermotaxis effect of low current and the sub-transistor parallel model, the peak junction temperature and non-uniform property of junction temperature distribution are analyzed successfully.

To isolate the active layer from air, double organic layer organic field-effect transistors have been fabricated, based on a two-step vacuum-deposition process. Pentacene acted as the active layer, and subsequently, CuPc was deposited above the pentacene and served as a protecting layer for the active layer. Due to the same electrical characteristics but different morphologies, the bilayer structure was effective in decreasing the contamination of impurities and gas, and then improved the device stability in air.

Crosstalk of HgCdTe long-wavelength infrared (LWIR) n-on-p diode arrays was measured using scanning laser microscopy. During the measurement, HgCdTe diode arrays with different diode pitches were frontside illuminated by a He–Ne laser at liquid nitrogen temperature and room temperature. The experimental results show that crosstalk between the nearest neighboring diodes decreases exponentially as the diode pitch increases, and the factors that affect the obtained crosstalk are presented and analyzed. Crosstalk out of the nominal diode area (optically sensitive area) is also measured and discussed.

A 100- m-long electroabsorption modulator monolithically integrated with passive waveguides at the input and output ports is fabricated through ion implantation induced quantum well intermixing, using only a two-step low-pressure metal–organic vapor phase epitaxial process. An InGaAsP/InGaAsP intra-step quantum well is introduced to the active region to improve the modulation properties. In the experiment high modulation speed and high extinction ratio are obtained simultaneously, the electrical-to-optical frequency response (E/O response) without any load termination reaches to 22 GHz, and extinction ration is as high as 16 dB.

Based on a self-developed AlGaN/GaN HEMT with 2.5 mm gate width technology on a SiC substrate, an X-band GaN combined solid-state power amplifier module is fabricated. The module consists of an AlGaN/GaN HEMT, Wilkinson power couplers, DC-bias circuit and microstrip line. For each amplifier, we use a bipolar DC power source. Special RC networks at the input and output and a resistor between the DC power source and the gate of the transistor at the input are used for cancellation of self-oscillation and crosstalk of low-frequency of each amplifier. At the same time, branches of length 3 /4 for Wilkinson power couplers are designed for the elimination of self-oscillation of the two amplifiers. Microstrip stub lines are used for input matching and output matching. Under Vds = 27 V, Vgs = –4.0 V, CWoperating conditions at 8 GHz, the amplifier module exhibits a line gain of 5.6 dB with power added efficiency of 23.4%, and output power of 41.46 dBm (14 W), and the power gain compression is 3 dB. Between 8 and 8.5 GHz, the variation of output power is less than 1.5 dB.

As the tuning frequency of an integrated LC-voltage controlled oscillator (LC-VCO) increases, it is difficult to co-design the active negative resistance core and the varactor to achieve wideband frequency range, low phase noise, constant bandwidth and small tuning gain together. The presented VCO solves the problem by designing a set of changeable varactor units. The whole VCO was implemented in a 0.18 μm CMOS process. The measured result shows –120 dBc/Hz phase noise at 1 MHz offset. The measured tuning range is from 4.2 to 5 GHz and the tuning gain is 8–10 MHz/V. The VCO draws 4 mA from a 1.5 V supply voltage.

Abstract: This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35 μm COMS technology with active area of 2.0 × 2.5 mm2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

A time-domain digitally controlled oscillator (DCO) is proposed. The DCO is composed of a free-running ring oscillator (FRO) and a two lap-selectors integrated flying-adder (FA). With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13 μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.

In a typical RFID system the reader transmits modulated RF power to provide both data and energy for the passive transponder. Low modulation index RF energy is preferable for an adequate tag power supply and increase in communication range but gives rise to difficulties for near-field conventional demodulation. Therefore, a novel ASK demodulator for minimum 20% modulation index RF signal detection over a range of 23 dB is presented. Thanks to the proposed innovative divisional linear conversion from the power into voltage signal, the detection sensitivity is ensured over a wide power range with low power consumption of 8.6 μW. The chip is implemented in UMC 0.18 μm mix-mode CMOS technology, and the chip area is 0.06 mm2.

A fast-hopping 3-band (mode 1) multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below –50 dBc, while the in-band spurious tones are below –34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 × 1.8 mm2.

Abstract: A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18-μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output P1dB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is –70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of –104 dBc/Hz at 100 kHz frequency offset and –120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm2 including pads.

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the direct-conversion principle and consists of a low noise amplifier (LNA) and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.

A 5-Gb/s 2 : 1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780  μm2 . At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered-off static random access memory (SRAM). Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25 μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architecture is presented. It exhibits IEEE 802.11 a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 corner frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35 μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm2 and 0.11 mm2 (calibration circuit excluded), respectively.

An integrated single-inductor dual-output (SIDO) switching DC–DC converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. A decoupling small signal model is proposed to analyze the multi-loop system and to design the on-chip compensators. An average current control mode is introduced with lossless, continuous current detection. The converter has been fabricated in a 0.25 μm 2P4M CMOS process. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 kHz.

This paper presents a controllable resistor, which is formed by a MOS-resistor working in the deep triangle region and an auxiliary circuit. The auxiliary circuit can generate the gate–source voltage which is proportional to the output current of an low dropout regulator for the MOS-resistor. Thus, the equivalent output resistance of the MOS-resistor is inversely proportional to the output current, which is a suitable feature for pole-zero tracking frequency compensation methods. By switching the type of the MOS-resistor and current direction through the auxiliary circuit, the controllable resistor can be suitable for different applications. Three pole-zero tracking frequency compensation methods based on a single Miller capacitor with nulling resistor, unit-gain compensation cell and pseudo-ESR (equivalent serial resistor of load capacitor) power stage have been realized by this controllable resistor. Their advantages and limitations are discussed and verified by simulation results.

A high-order curvature-compensated and high power-supply rejection ratio (PSRR) BiCMOS bandgap reference is presented. The circuit utilizes positive temperature characteristics of the saturation current ISS and forward current gain of the bipolar transistors to realize a low temperature coefficient (TC) as well as filter capacitors and level-shift structures to improve the PSRR. Implemented in 0.6 μm BCD process, the proposed voltage reference consumes a supply current of 28 A at 3.6 V. A temperature coefficient of 2.8 ppm/℃, PSRR of more than 80 dB at low frequencies and a line regulation of 50 ppm/V from 3.6 to 5.5 V are easily achieved, which make it widely applicable in portable equipment.

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC–DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump's power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.

The planar patch-clamp technique has been applied to high throughput screening in drug discovery. The key feature of this technique is the fabrication of a planar patch-clamp substrate using appropriate materials. In this study, a planar patch-clamp substrate was designed and fabricated using a silicon-on-insulator (SOI) wafer. The access resistance and capacitance of SOI-based planar patch-clamp substrates are smaller than those of bulk silicon-based planar substrates, which will reduce the distributed RC noise.

A two-step process of Ni silicide formed on bulk silicon, and the effects of different process conditions, including two-step RTA temperature and time, selective etching, and process protective nitrogen gas on the properties of the Ni silicide film have been studied. In particular, the experiments show that the quality of NiSi film is very sensitive to the process conditions of the first RTA. The experiments also show that the quality of the film is very sensitive to the flow of protective nitrogen gas. The corresponding mechanisms are discussed.

A lithography-independent and wafer scale method to fabricate a metal nanogap structure is demonstrated. Polysilicon was first dry etched using photoresist (PR) as the etch mask patterned by photolithography. Then, by depositing conformal SiO2 on the polysilicon pattern, etching back SiO2 anisotropically in the perpendicular direction and removing the polysilicon with KOH, a sacrificial SiO2 spacer was obtained. Finally, after metal evaporation and lifting-off of the SiO2 spacer, an 82 nm metal-gap structure was achieved. The size of the nanogap is not determined by the photolithography, but by the thickness of the SiO2. The method reported in this paper is compatible with modern semiconductor technology and can be used in mass production.

Currently, 200 mm wafer foundry companies are beginning to explore production feasibility under ground rules smaller than 0.11 μm while maintain the cost advantages of KrF exposure tool systems. The k1 factor under 0.11 μm at 248 nm illumination will be below 0.35, which means the process complexity is comparable with 65 nm at 193 nm illumination. In this paper, we present our initial study in the CD process window, mask error factor and CD through pitch performance at the 0.09 μm ground rule for three critical layers—gate poly, metal and contact. The wafer data in the process window and optical proximity will be analyzed. Based on the result, it is shown that the KrF tool is fully capable of sub 0.11 μm node mass production.

The influence of deposition, annealing conditions, and etchants on the wet etch rate of plasma enhanced chemical vapor deposition (PECVD) silicon nitride thin film is studied. The deposition source gas flow rate and annealing temperature were varied to decrease the etch rate of SiNx:H by HF solution. A low etch rate was achieved by increasing the SiH4 gas flow rate or annealing temperature, or decreasing the NH3 and N2 gas flow rate. Concentrated, buffered, and dilute hydrofluoric acid were utilized as etchants for SiO2 and SiNx:H. A high etching selectivity of SiO2 over SiNx:H was obtained using highly concentrated buffered HF.