To study the physical origin of the non-ohmic behavior of WO3 ceramics, the effects of heat treatmentin different atmospheres on WO3 varistors were investigated. Experiments showed that there was a dependence of the nonlinear coefficient on thermal treatment under different atmospheres. Thermal treatments in argon and oxygen atmospheres at 900 ℃ proved this dependence, and indicated that the nonlinear coefficient got significantly lower when the samples were thermally treated under argon atmosphere. Subsequent exposure to oxygen atmosphere at the same temperature led to the restoration of electrical properties. The result shows that the physical origin of the non-ohmic behavior of WO3 ceramics is oxygen on the grain surfaces adsorbed by intrinsic defects.

This paper describes the first domestic Ku-band power AlGaN/GaN HEMT fabricated on a sapphire substrate. The device with a gate width of 0.5 mm and a gate length of 0.35 μm has exhibited an extrinsic current gain cutoff frequency of 20 GHz and an extrinsic maximum frequency of oscillation of 75 GHz. Under VDS = 30 V, CW operating conditions at 14 GHz, the device exhibits a linear gain of 10.4 dB and a 3-dB-gain-compressed output power of 1.4 W with a power added efficiency of 41%. Under pulse operating conditions, the linear gain is 12.8 dB and the 3-dB-compressed output power is 1.7 W. The power density reaches 3.4 W/mm.

A new SOI LIGBT (lateral insulated-gate bipolar transistor) with cathode- and anode-gates on partial membrane is proposed. A low on-state resistance is achieved when a negative voltage is applied to the anode gate. In the blocking state, the cathode gate is shortened to the cathode and the anode gate is shortened to the anode, leading to a fast switching speed. Moreover, the removal of the partial silicon substrate under the drift region avoids collecting charges beneath the buried oxide, which releases potential lines below the membrane, yielding an enhanced breakdown voltage (BV). Furthermore, a high switching speed is obtained due to the absence of the drain–substrate capacitance. Lastly, a combination of uniformity and variation in lateral doping profiles helps to achieve a high BV and low special on-resistance. Compared with a conventional LIGBT, the proposed structure exhibits high current capability, low special on-resistance, and double the BV.

A new trench gate IGBT structure with a floating P region is proposed, which introduces a floating P region into the trench accumulation layer controlled IGBT (TAC-IGBT). The new structure maintains a low on-state voltage drop and large forward biased safe operating area (FBSOA) of the TAC-IGBT structure while reduces the leakage current and improves the breakdown voltage. In addition, it enlarges the short circuit safe operating area (SCSOA) of the TAC-IGBT, and is simple in fabrication and design. Simulation results indicate that, for IGBT structures with a breakdown voltage of 1200 V, the leakage current of the new trench gate IGBT structure is one order of magnitude lower than the TAC-IGBT structure and the breakdown voltage is 150 V higher than the TAC-IGBT.

A carrier stored trench-gate bipolar transistor (CSTBT) with a p-floating layer (PF-CSTBT) is proposed. Due to the p-floating layer, the thick and highly doped carrier stored layer can be induced, and the conductivity modulation effect will be enhanced near the emitter. The accumulation resistance and the spreading resistance are reduced. The on-state loss will be much lower than in a conventional CSTBT. With the p-floating layer, the distribution of electric fields of the conventional IGBT is reformed, and the breakdown voltage is remarkably improved. The simulation results have shown that the forward voltage drop (VCE-on) of the novel structure is reduced by 20% and 17% respectively, compared with the conventional trench IGBT (TIGBT) and CSTBT under the same conditions. Moreover, an increment of more than 100 V of the breakdown voltage is achieved without sacrificing the SCSOA (short circuit safety operation area) compared with the conventional TIGBT.

A GMR (giant magneto-resistive) spin valve sensor for magnetic recording has been designed in an attempt to solve the Barkhausen noise problem in small-sized GMR sensors. In this study, the GMR ratio of the top-pinned spin valve is optimized to a value of 13.2%. The free layer is magnetized perpendicular to the pinned layer by a CoCrPt permanent magnetic bias so that a linear magnetic field response can be obtained. An obvious improvement on performance is observed when the permanent magnetic bias is magnetized, while the GMR sensor has a steadier MR–H loop and a smaller coercive field.

An MWCNT-doped (multi-walled carbon nanotube) SnO2 thin film NO2 gas sensor, prepared by radio frequency reactive magnetron sputtering, showed a high sensitivity to ultra-low concentrations of NO2 in the parts per billion range. X-ray diffraction, X-ray photoelectron spectroscopy, and scanning electron microscopy (SEM) characterizations indicated that the MWCNTs were affected by the morphology of the SnO2 thin film and the particle size. The properties of the MWCNT-doped SnO2 sensor, such as sensitivity, selectivity, and response-recovery time, were investigated. Experimental results revealed that the MWCNT-doped SnO2 thin film sensor response to NO2 gas depended on the operating temperature, NO2 gas concentration, thermal treatment conditions, film thickness, and so on. The mechanism of the gas-sensing property of the MWCNT-doped SnO2 thin film sensor was investigated and showed that the improved gas-sensing performance should be attributed to the effects between MWCNTs (p-type) and SnO2 (n-type) semiconductors.

The design of a 1.76–2.56 GHz CMOS voltage-controlled oscillator (VCO) with switched capacitor array and switched inductor array is presented. Fabricated in 0.18 μm 1P6M CMOS technology, the VCO achieves a 37% frequency tuning range. The measured phase noise varies between –118.5 dBc/Hz and –122.8 dBc/Hz at 1 MHz offset across the tuning range. Power consumption is about 14.4 mW with a 1.8 V supply. Based on a reconfigurable LC tank with switched capacitor array and switched inductor array, the tuning range is analyzed and derived in terms of design parameters, yielding useful equations to guide the circuit design.

A built-in linearizer was applied to improve the linearity in a 5.2-GHz power amplifier microwave monolithic integrated circuit (MMIC), which was undertaken with 0.15-μm AlGaAs/InGaAs D-mode PHEMT technology. The power amplifier (PA) was studied taking into account the linearizer circuit and the coplanar waveguide (CPW) structures. Based on these technologies, the power amplifier, which has a chip size of 1.44 × 1.10 mm², obtained an output power of 13.3 dBm and a power gain of 14 dB in the saturation region. An input third-order intercept point (IIP₃) of –3 dBm, an output third-order intercept point (OIP₃) of 21.1 dBm and a power added efficiency (PAE) of 22% were attained, respectively. Finally, the overall power characterization exhibited high gain and high linearity, which illustrates that the power amplifier has a compact circuit size and exhibits favorable RF characteristics. This power circuit demonstrated high RF characterization and could be used for microwave power circuit applications at 5.2 GHz.

A 3–5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio ultra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4–5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with 0.45 dB gain fluctuations across 3–5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5–5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below –13 dB over 2.9–5.4 GHz. The input-referred 1-dB compression point (IP1dB) is –11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.

This paper presents a new circuit scheme to control the current surge in the boosting phase of an radio frequency idenfication–nonvolative memory pump. By introducing a circuit block consisting of a current reference and a current mirror, the new circuit scheme can keep the period-average current of the pump constantly below the desired level, for example, 2.5 μA. Therefore, it can prevent the rectified supply of the RFID tag IC from collapsing in the boosting phase of the pump. The presented scheme could effectively reduce the voltage drop on the rectified supply from more than 50% to even zero, but could cost less area. Moreover, an analytical expression to calculate the boosting time of a pump in the new scheme is developed.

A wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier (VGA), a comparator and a charge pump, and the dB-linear gain is controlled by the charge pump. The AGC was implemented in a 0.18 μm CMOS technology. The dynamic range of the VGA is more than 55 dB, the bandwidth is 30 MHz, and the gain error is lower than 1.5 dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW, and the area of the AGC is 700×450 m2.

A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultrawide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18- m CMOS technology. The S11 of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz–2 GHz. The variable gain range is 12–42 dB at 0.25 GHz and 4–36 dB at 2 GHz. The DSB NF at maximum gain is 3.1–6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.

This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious free dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3.1×2.1 mm2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.

A high linearity, undersampling 14-bit 357 kSps cyclic analog-to-digital convert (ADC) is designed for a radio frequency identification transceiver system. The passive capacitor error-average (PCEA) technique is adopted for high accuracy. An improved PCEA sampling network, capable of eliminating the crosstalk path of two pipelined stages, is employed. Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area. An additional digital calibration block is added to compensate for the error due to defective layout design. The presented ADC is fabricated in a 180 nm CMOS process, occupying 0.65×1.6 mm2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range (SFDR), and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm2 in the 0.13-μm CMOS process.

This paper presents a novel high precision and wide range adjustable LED constant-current drive controller design. Compared with the traditional technique, the conventional mirror resistance is substituted by a MOSFET with fixed drain voltage, and a negative feedback amplifier is used to keep all mirror device voltages equal, so that the output current is precise and not affected by the load supply voltage. In addition, the electric property of the mirror MOSFET is optimized by a current subsection mirror (CSM) mechanism, thus ensuring a wide range of output current with high accuracy. A three-channel LED driver chip based on this project is designed and fabricated in the TSMC 0.6 μm BCD process with a die area of 1.1×0.7 mm2. Experimental results show that the proposed LED drive controller works well, and, as expected, the output current can be maintained from 5 to 60 mA. A relative current accuracy error of less than 1% and a maximal relative current matching error of 1.5% are successfully achieved.

An improved low distortion sigma–delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma–delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC. The modulator has been implemented by a 0.18 μm CMOS process and operates at a single 1.8 V supply voltage. Experimental results show that for a 1.25 MHz @ –6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.

The design and measurement of a snap-shot mode cryogenic readout circuit (ROIC) for GaAs/AlGaAs QWIP FPAs was reported. CTIA input circuits with pixel level built-in electronic injection transistors were proposed to test the chip before assembly with a detector array. Design optimization techniques for cryogenic and low power are analyzed. An experimental ROIC chip of a 128×128 array was fabricated in 0.35μm CMOS technology. Measurements showed that the ROIC could operate at 77 K with low power dissipation of 35 mW. The chip has a pixel charge capacity of 2.57E6 electrons and transimpedance of 1.4E7 electrons. Measurements showed that the transimpedance non-uniformity was less than 5% with a 10 MHz readout speed and a 3.3 V supply voltage.

We first study the impacts of soft errors on various types of CAM for different feature sizes. After presenting a soft error immune CAM cell, SSB-RCAM, we propose two kinds of reliable CAM, DCF-RCAM and DCK-RCAM. In addition, we present an ignore mechanism to protect dual cell redundancy CAMs against soft errors. Experimental results indicate that the 11T-NOR CAM cell has an advantage in soft error immunity. Based on 11T-NOR, the proposed reliable CAMs reduce the SER by about 81% on average with acceptable overheads. The SER of dual cell redundancy CAMs can also be decreased using the ignore mechanism in specific applications.

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance–voltage (C–V ) analysis.