The surface structures of wurtzite ZnO (0001) and (000^-1) surfaces are investigated by using a first-principles calculation of plane wave ultra-soft pseudo-potential technology based on density functional theory (DFT). The calculated results reveal that the surface energy of ZnO–Zn is bigger than that of ZnO–O, and the ZnO–Zn surface is more unstable and active. These two surfaces are apt to relax inward, but the contractions of the ZnO–Zn surface are smaller than the ZnO–O surface. Due to the dispersed Zn4s states and the states of stronger hybridization between the Zn and O atoms, the ZnO–Zn surface shows n-type conduction, while the O2p dangling-bond bands in the upper part of the valence cause the ZnO–O surface to have p-type conduction. The above results are broadly consistent with the experimental results.

The laser-generated surface acoustic wave (SAW) technique is an accurate, fast and nondestructive solution to determine the mechanical properties of ultra thin films. SAWs are dispersive during the wave propagation on the layered structure. The Young's moduli of thin films can be obtained by matching the experimentally and theoretically calculated dispersive SAW curves. A short ultraviolet laser pulse is employed to generate the broad spectral range of the dispersive SAWs. The frequency range of dispersive SAWs in this study reaches 180 MHz, which is adequate for the SAW technique applied for the investigated samples. In this work, the Young's moduli of a series of nanoporous Black Diamond^TM low dielectric constant (low-k) films deposited on a Si (100) substrate are characterized successfully by the SAW technique.

Two SiO₂/Si interface structures, which are described by the double bonded model (DBM) and the bridge oxygen model (BOM), have been theoretically studied via first-principle calculations. First-principle simulations demonstrate that the width of the transition region for the interface structure described by DBM is larger than that for the interface structure described by BOM. Such a difference will result in a difference in the gate leakage current. Tunneling current calculation demonstrates that the SiO₂/Si interface structure described by DBM leads to a larger gate leakage current.

A typical GaInP/GaInAs/Ge tandem solar cell structure operating under AM0 illumination is proposed, and the current–voltage curves are calculated for different recombination velocities at both front and back-surfaces of the three subcells by using a theoretical model including optical and electrical modules. It is found that the surface recombination at the top GaInP cell is the main limitation for obtaining high efficiency tandem solar cells.

According to thermodynamic and kinetic theory, considering the variation of bulk free energy and superficial energy after nucleation as well as the migration of atoms, we study systematically the planar nucleation and crystallization that relate to two possible transition mechanisms in the annealing process of ion implanted Si: (1) liquid/solid transition: the critical nucleation work is equal to half the increased superficial energy and inversely proportional to the supercooling Δ T. Compared with bulk nucleation, the radius of the critical nucleus decreases by half, and the nucleation rate attains its maximum at T = T_m/2. (2) amorphous/crystalline transition: the atoms contained in the critical nucleus and situated on its surface, as well as critical nucleation work, are all directly proportional to the height of the nucleus, and the nucleation barrier is equal to half the superficial energy too. In addition, we take SiGe semiconductor as a specific example for calculation; a value of 0.03 eV/atom is obtained for the elastic strain energy, and a more reasonable result can be gotten after taking into account its effect on transition Finally, we reach the following conclusion as a result of the calculation: for the annealing of ion implanted Si, no matter what the transition method is—liquid or solid planar nucleation—the recrystallization process is actually carried out layer by layer on the crystal substrate, and the probability of forming a "rod-like" nucleus is much larger than that of a "plate-like" nucleus.

Lead iodide (PbI₂) films have been prepared by the electron beam evaporation technique, and their photoconductive response to visible light was investigated under different deposition and illumination conditions. It is found that the films' photoconductive response speed increases and the relative sensitivity decreases with the increase of substrate temperature due to the opposite requests for photo-carrier lifetime. Further, appropriately increasing the film's thickness and rising substrate temperature simultaneously can effectively balance the opposite demands. Under optimized conditions of a substrate temperature of 200 ℃, a source–substrate distance of 30 cm and a deposition time of 10 min, the prepared films exhibit the best response properties. In addition, the response to illumination with different wavelengths was also measured, revealing that the decline of response performance with increasing wavelength is due to the lower photon energy of incident light.

Electrodeposition is a promising and low cost method to synthesize CuIn_xGa_1-xSe₂ (CIGS)thin films as an absorber layer for solar cells. The effect of bath temperature on the properties of CIGS thin films was investigated in this paper. CIGS films of 1 μ m thickness were electrodeposited potentiostatically from aqueous solution, containing trisodium citrate as a complexing agent, on Mo/glass substrate under a voltage of –0.75 V, and bath temperatures were varied from 20 to 60oC. The effects of bath temperature on the properties of CIGS thin films were characterized by X-ray diffraction (XRD) and scanning electron microscopy. XRD revealed the presence of the CuIn_0.7Ga_0.3Se₂ phase, the optimal phase for application in solar cells. The grain dimensions and crystallizability increase along with the increase of the bath temperature, and the films become stacked and homogeneous. There were few changes in surface morphology and the composition of the films.

YBa₂Cu₃O_{7 - δ} (YBCO) films were deposited on (100)-oriented LaAlO₃ (LAO) single crystal substrates by the dip-coating process using low-fluorine solution. Their microstructures were characterized with the aid of X-ray diffractometry, scanning electron microscopy and high-resolution transmission electron microscopy. Their superconducting properties were measured by the standard four-probe method. The experiment results show that the film obtained under high enough humidity conditions exhibits better c-axis texture and superconducting properties than the film under a relatively low humidity conditions. Based on the classical nucleation and chemical reaction thermodynamics theory, the underlying crystalline and growth mechanisms of YBCO films under certain humidity conditions are explained in combination with our experimental results. It is suggested that the unreacted intermediate phases such as BaF₂ and CuO aggregated in the YBCO grain boundary will cause lattice distortion in the YBCO matrix and further induce the formation of a-axis oriented YBCO grains as crystallization proceeds. Therefore, it is believed that the relative content of water vapor within the heat-treatment atmosphere plays quite an important role in the preparation of c-axis oriented YBCO film with good superconducting properties.

Mn–W co-doped ZnO (ZMWO) thin films with low resistivity and high transparency were successfully prepared on glass substrate by direct current (DC) magnetron sputtering at low temperature. The sputtering power was varied from 65 to 150 W. The crystallinity and resistivity of ZMWO films greatly depend on sputtering power while the optical transmittance and optical band gap are not sensitive to sputtering power. All the deposited films are polycrystalline with a hexagonal structure and have a preferred orientation along the c-axis perpendicular to the substrate. Considering the crystallinity and the electrical and optical properties, we suggest that the optimal sputtering power in this experiment is 90 W and, at this power, the ZMWO film has the lowest resistivity of 9.8 × 10^-4 Ω.cm with a high transmittance of approximately 89% in the visible range.

An enhancement-mode AlGaN/GaN HEMT with a threshold voltage of 0.35 V was fabricated by fluorine plasma treatment. The enhancement-mode device demonstrates high-performance DC characteristics with a saturation current density of 667 mA/mm at a gate bias of 4 V and a peak transconductance of 201 mS/mm at a gate bias of 0.8 V. The current-gain cut-off frequency and the maximum oscillation frequency of the enhancement-mode device with a gate length of 1 μ m are 10.3 GHz and 12.5 GHz, respectively, which is comparable with the depletion-mode device. A numerical simulation supported by SIMS results was employed to give a reasonable explanation that the fluorine ions act as an acceptor trap center in the barrier layer.

Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth, based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited. The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation. The dynamic characteristics, especially reverse diode characteristics, are equivalent or even superior to foreign counterparts.

A diagram representation method is proposed to interpret the complicated charge pumping (CP) processes. The fast and slow traps in CP measurement are defined. Some phenomena such as CP pulse rise/fall time dependence, frequency dependence, the voltage dependence for the fast and slow traps, and the geometric CP component are clearly illustrated at a glance by the diagram representation. For the slow trap CP measurement, there is a transition stage and a steady stage due to the asymmetry of the electron and hole capture, and the CP current is determined by the lower capturing electron or hole component. The method is used to discuss the legitimacy of the newly developed modified charge pumping method.

We demonstrate a two-dimensional (2D) full-band ensemble Monte–Carlo simulator for heterostructures, which deals with carrier transport in two different semiconductor materials simultaneously as well as at the boundary by solving self-consistently the 2D Poisson and Boltzmann transport equations (BTE). The infrastructure of this simulator, including the energy bands obtained from the empirical pseudo potential method, various scattering mechanics employed, and the appropriate treatment of the carrier transport at the boundary between two different semiconductor materials, is also described. As verification and calibration, we have performed a simulation on two types of silicon–germanium (Si–Ge) heterojunctions with different doping profiles—the p–p homogeneous type and the n–p inhomogeneous type. The current–voltage characteristics are simulated, and the distributions of potential and carrier density are also plotted, which show the validity of our simulator.

A brand new and feasible method for measuring the carrier lifetime and capture cross-section of a barrier by using the negative resistance segment of the I–V characteristics of a barrier-type thyristor (BTH) is put forward. The measuring principle and calculation method are given. The BTH samples are experimentally measured and the results are analyzed in detail.

A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC (digital-to-analog converter). With this process, an NJFET with a pinch-off voltage of about –1.5 V and a breakdown voltage of about 16 V, an NLDDMOS (N-type lightly-dosed-drain in MOS) with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V, and a Zener diode with a reverse voltage of about 5.6 V were obtained. Measurement results showed that the converter had a reference temperature coefficient of less than ± 25 ppm/℃, a differential coefficient error of less than ± 0.3 LSB, and a linear error of less than ± 0.5 LSB. The depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or DACs.

Ni/Au Schottky contacts with thicknesses of either 50 Å/50 Å or 600 Å/2000 Å were deposited on strained Al_0.3Ga_0.7N/GaN heterostructures. Using the measured C–V curves and I–V characteristics at room temperature, the calculated density of the two-dimensional electron-gas (2DEG) of the 600 Å/2000 Å thick Ni/Au Schottky contact is about 9.13 × 10¹² cm^–2 and that of the 50 Å/50 Å thick Ni/Au Schottky contact is only about 4.77 × 10¹² cm^–2. The saturated current increases from 60.88 to 86.34 mA at a bias of 20 V as the thickness of the Ni/Au Schottky contact increases from 50 Å/50 Å to 600 Å/2000 Å. By self-consistently solving Schrodinger's and Poisson's equations, the polarization charge sheet density of the two samples was calculated, and the calculated results show that the polarization in the AlGaN barrier layer for the thick Ni/Au Schottky contact is stronger than the thin one. Thus, we attribute the results to the increased biaxial tensile stress in the Al_0.3Ga_0.7N barrier layer induced by the 600 Å/2000 Å thick Ni/Au Schottky contact.

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.

We have theoretically calculated the photovoltaic conversion efficiency of a monolithic dual-junction GaInP/GaInAs device, which can be experimentally fabricated on a binary GaAs substrate. By optimizing the bandgap combination of the considered structure, an improvement of conversion efficiency has been observed in comparison to the conventional GaInP₂/GaAs system. For the suggested bandgap combination 1.83 eV/1.335 eV, our calculation indicates that the attainable efficiency can be enhanced up to 40.45% (300 suns, AM1.5d) for the optimal structure parameter (1550 nm GaInP top and 5500 nm GaInAs bottom), showing promising application prospects due to its acceptable lattice-mismatch (0.43%) to the GaAs substrate. oindent

PANI/ZnPcCl₁₆ (polyaniline doped with sulfosalicylic acid/hexadecachloro zinc phthalocyanine) powders were vacuum co-deposited onto Si substrates, where Pt interdigitated electrodes were made by micromachining. The PANI/ZnPcCl₁₆ films were characterized and analyzed by SEM, and the influencing factors on its intrinsic performance were analyzed and sensitivities of the sensors were investigated by exposure to chlorine (Cl₂) gas. The results showed that powders prepared with a stoichiometric ratio of (ZnPcCl₁₆)_0.6(PANI)_0.4 had a preferential sensitivity to Cl₂ gas, superior to those prepared otherwise; the optimal vacuum co-deposition conditions for the films are a substrate temperature of 160 ℃, an evaporation temperature of 425 ℃ and a film thickness of 75 nm; elevating the operation temperature (above 100 ℃) or increasing the gas concentration (over 100 ppm) would improve the response characteristics, but there should be upper levels for each. Finally, the gas sensing mechanism of PANI/ZnPcCl₁₆ films was also discussed.

A closed-form model for the frequency-dependent per-unit-length resistance of trapezoidal cross-sectional interconnects is presented. The frequency-dependent per-unit-length resistance R(f) of a trapezoidal interconnect line is first obtained by a numerical method. Using the method we quantify the trapezoid edge effect on the resistance of the interconnect and the current density distribution in the cross section. Based on this strict numerical result, a novel closed-form model R(f) for a single trapezoidal interconnect is fitted out using the Levenberg–Marquardt method. This R(f) can be widely used for analyzing on-chip interconnects when the frequency is changing. The model is computationally very efficient with respect to the numerical method, and the results are found to be accurate.

A new SOI LDMOS structure with buried n-islands (BNIs) on the top interface of the buried oxide (BOX) is presented in a p-SOI high voltage integrated circuits (p-SOI HVICs), which exhibits good self-isolation performance between the power device and low-voltage control circuits. Furthermore, both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μ m, but also modulate the lateral electric field distribution, resulting in an improvement of the breakdown voltage of the BNI SOI LDMOS. A 673 V BNI SOI LDMOS is experimentally obtained and presents an excellent self-isolation performance in a p-SOI HVIC.

The conventional circuit model of a bit-stream adder based on sigma delta (Σ Δ ) modulation is improved with pipeline technology to make it work correctly at high frequencies. The integrated circuit (IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency. The IC is fabricated in TSMC's 0.18-μ m CMOS process. The chip area is 475 × 570 μ m². A fully digital Σ Δ signal generator is designed with a field programmable gate array to test the chip. Experimental results show that the chip meets the function and performance demand of the design, and the chip can work at a frequency of higher than 4 GHz. The noise performance of the adder is analyzed and compared with both theory and experimental results. oindent

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18 μ m CMOS process. A low power mixed-signal LC VCO, a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time. The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations. The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3 μs.

This paper presents a width controller, a dead time controller, a discontinuous current mode (DCM) controller and a frequency skipping modulation (FSM) controller for a high frequency high efficiency buck DC–DC converter. To improve the efficiency over a wide load range, especially at high switching frequency, the dead time controller and width controller are applied to enhance the high load efficiency, while the DCM controller and FSM controller are proposed to increase the light load efficiency. The proposed DC–DC converter controllers have been designed and fabricated in the Chartered 0.35 μ m CMOS process, and the measured results show that the efficiency of the buck DC–DC converter is above 80% over a wide load current range from 8 to 570 mA, and the peak efficiency is 86% at 10 MHz switching frequency.

A low jitter, low spur multiphase phase-locked loop (PLL) for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output. In this design, a noise and matching improved voltage-controlled oscillator (VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks. By good matching achieved in the charge pump and careful choice of the loop filter bandwidth, the reference spur is suppressed. A phase noise of –118.42 dBc/Hz at a frequency offset of 1 MHz, RMS jitter of 1.53 ps and reference spur of –66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement. The chip was manufactured in 0.13 μ m CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm² area.

A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks—including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU—in a 0.18 μ m CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is –60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 × 3.8 mm² including pads. oindent

A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μ m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 × 270 μ m². Experimental results show that the PSR of the LDO is –58.7 dB at a frequency of 10 Hz and –20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA.

A fully integrated cross-coupled LC tank voltage-controlled oscillator (LC-VCO) using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μ m CMOS technology of SMIC. The measured phase noise is –125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz, while the VCO core circuit draws only 640 μ W from a 0.4-V supply. The designed VCO can cover a frequency range from 2.28 to 2.48 GHz. The tuning range of the circuit is 200 MHz (8.7%) and the FOM is –195.7 dB, which is suitable for an IEEE 802.11b receiver.

To improve two shortcomings of conventional network-on-chips, i.e. low utilization rate in channels between routers and excessive interconnection lines, this paper proposes a full asynchronous self-adaptive bi-directional transmission channel. It can utilize interconnection lines and register resources with high efficiency, and dynamically detect the data transmission state between routers through a direction regulator, which controls the sequencer to automatically adjust the transmission direction of the bi-directional channel, so as to provide a flexible data transmission environment. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed bi-directional transmission channel is implemented based on SMIC 0.18 μ m standard CMOS technology. Post-layout simulation results demonstrate that this self-adaptive bi-directional channel has better performance on throughput, transmission flexibility and channel bandwidth utilization compared to a conventional single direction channel. Moreover, the proposed channel can save interconnection lines up to 30% and can provide twice the bandwidth resources of a single direction transmission channel. The proposed channel can apply to an on-chip network which has limited resources of registers and interconnection lines.

A low power and low phase noise phase-locked loop (PLL) design for low voltage (0.8 V) applications is presented. The voltage controlled oscillator (VCO) operates from a 0.5 V voltage supply, while the other blocks operate from a 0.8 V supply. A differential NMOS-only topology is adopted for the oscillator, a modified precharge topology is applied in the phase-frequency detector (PFD), and a new feedback structure is utilized in the charge pump (CP) for ultra-low voltage applications. The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power. In addition, several novel design techniques, such as removing the tail current source, are demonstrated to cut down the phase noise. Implemented in the SMIC 0.13 μ m RF CMOS process and operated at 0.8 V supply voltage, the PLL measures a phase noise of –112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166–3.383 GHz. The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply. The occupied chip area of the PFD and CP is 100 × 100 μ m². The chip occupies 0.63 mm², and draws less than 6.54 mW from a 0.8 V supply.

A novel simple dose-compensation method is developed for proximity effect correction in electron-beam lithography. The sizes of exposed patterns depend on dose factors while other exposure parameters (including accelerate voltage, resist thickness, exposing step size, substrate material, and so on) remain constant. This method is based on two reasonable assumptions in the evaluation of the compensated dose factor: one is that the relation between dose factors and circle-diameters is linear in the range under consideration; the other is that the compensated dose factor is only affected by the nearest neighbors for simplicity. Four-layer-hexagon photonic crystal structures were fabricated as test patterns to demonstrate this method. Compared to the uncorrected structures, the homogeneity of the corrected hole-size in photonic crystal structures was clearly improved.