Microcrystalline silicon films were deposited at a high rate and low temperature using jet-type inductively coupled plasma chemical vapor deposition (jet-ICPCVD). An investigation into the deposition rate and microstructure properties of the deposited films showed that a high deposition rate of over 20 nm/s can be achieved while maintaining reasonable material quality. The deposition rate can be controlled by regulating the generation rate and transport of film growth precursors. The film with high crystallinity deposited at low temperature could principally result from hydrogen-induced chemical annealing.

A new two-step phosphorous diffusion gettering (TSPDG) process using a sacrificial porous silicon layer (PSL) is proposed. Due to a decrease in high temperature time, the TSPDG (PSL) process weakens the deterioration in performances of PSL, and increases the capability of impurity clusters to dissolve and diffuse to the gettering regions. By means of the TSPDG (PSL) process under conditions of 900 ℃/60 min + 700 ℃/30 min, the effective lifetime of minority carriers in solar-grade (SOG) Si is increased to 14.3 times its original value, and the short-circuit current density of solar cells is improved from 23.5 o 28.7 mA/cm², and the open-circuit voltage from 0.534 to 0.596 V along with the transform efficiency from 8.1% to 11.8%, which are much superior to the results achieved by the PDG (PSL) process at 900 ℃ for 90 min.

p-CdTe thin films were prepared by spray pyrolysis under different ambient conditions and characterized using photoelectrochemical (PEC), X-ray diffraction (XRD), scanning electron microscopy, energy-dispersive analysis by X-ray (EDAX), and optical transmission studies. The different preparative parameters viz solution pH, solution quantity, substrate temperature and solution concentration have been optimized by the PEC technique in order to get good-quality photosensitive material. XRD analysis shows the polycrystalline nature of the film, having cubic structure with strong (111) orientation. Micrographs reveal that grains are uniformly distributed over the surface of the substrate indicating the well-defined growth of polycrystalline CdTe thin film. The EDAX study for the sample deposited at optimized preparative parameters shows the nearly stoichiometric Cd : Te ratio. Optical absorption shows the presence of direct transition with band gap energy of 1.5 eV. Deposited films exhibit the highest photocurrent of 2.3 mA, a photovoltage of 462 mV, a 0.48 fill factor and 3.4% efficiency for the optimized preparative parameters.

A homemade 7 × 2 inch MOCVD system is presented. With this system, high quality GaN epitaxial layers, InGaN/GaN multi-quantum wells and blue LED structural epitaxial layers have been successfully grown. The non-uniformity of undoped GaN epitaxial layers is as low as 2.86%. Using the LED structural epitaxial layers, blue LED chips with area of 350 × 350 μm² were fabricated. Under 20 mA injection current, the optical output power of the blue LED is 8.62 mW.

Solar cells are currently fabricated from a variety of silicon-based materials. Now the major silicon material for solar cells is the scrap of electronic grade silicon (EG-Si). But in the current market it is difficult to secure a steady supply of this material. Therefore, alternative production processes are needed to increase the feedstock. In this paper, EBM is used to purify silicon. MG-Si particles after leaching with an initial purity of 99.88% in mass as starting materials were used. The final purity of the silicon disk obtained after EBM was above 99.995% in mass. This result demonstrates that EBM can effectively remove impurities from silicon. This paper mainly studies the impurity distribution in the silicon disk after EBM.

This paper reports the dark conductivity and photoconductivity of amorphous Hg_0.78Cd_0.22Te thin films deposited on an Al₂O₃ substrate by RF magnetron sputtering. It is determined that dark conduction activation energy is 0.417 eV for the as-grown sample. Thermal quenching is absent for the as-grown sample during the testing temperature zone, but the reverse is true for the polycrystalline sample. Photosensitivity shows the maximum at 240 K for amorphous thin films, while it is higher for the as-grown sample than for polycrystalline thin films in the range from 170 to 300 K. The recombination mechanism is the monomolecular recombination process at room temperature, which is different from the low temperature range. The μτ-product is low in the range of 10^-11–10^-9 cm²/V, which indicates that some defect states exist in the amorphous thin films.

The synthesis of ZnO architecture on a fluorine-doped SnO₂ (FTO) conducting glass pre-coated with nanoporous TiO₂ film has been achieved by a one-step hydrothermal method at a temperature of 70 ℃. The effect of the reaction time on the morphology of the ZnO architecture has been investigated, and a possible growth mechanism for the formation of the ZnO architecture is discussed in detail. The morphology and phase structures of the as-obtained composite films have been investigated by field-emission scanning electron microscopy (FE-SEM) and X-ray diffraction (XRD). The results show that the growth time greatly affects the morphology of the obtained ZnO architecture. The photoelectrochemical performances of as-prepared composite films are measured by assembling them into dye sensitized solar cells (DSSCs). The DSSC based on the as-prepared composite film (2 h) has obtained the best power conversion efficiency of 1.845%.

The mass transport process in a showerhead MOCVD reactor is mathematically analyzed. The mathematical analysis shows that the vertical component velocity of a point over the substrate is only dependent on vertical distance and is independent of radial distance. The boundary layer thickness in stagnation flow is independent of the radial position too. Due to the above features, the flow field suitable for film growth can be obtained. The ceiling height of the reactor has important effects on residence time and the mass transport process. The showerhead MOCVD reactor has a short residence time and diffusion plays an important role in axial transport, while both diffusion and convection are important in radial transport.

To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator (SGOI) n-type metal–oxide–semiconductor field-effect transistors (nMOSFETs), this paper proposes a novel device called double step buried oxide (BOX) SGOI, investigates its electrical and thermal characteristics, and analyzes the effect of self-heating on its electrical parameters. During the simulation of the device, a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered. A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed. By reducing moderately the BOX thickness under the channel, the channel temperature caused by the self-heating effect can be effectively reduced. Moreover, mobility degradation, off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed. Therefore, SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.

A millimeter wave large-signal model of GaAs planar Schottky varactor diodes based on a physical analysis is presented. The model consists of nonlinear resistances and capacitances of the junction region and external parasitic parameters. By analyzing the characteristics of the diode under reverse and forward bias, an extraction procedure of all of the parameters is addressed. To validate the newly proposed model, the PSVDs were fabricated based on a planar process and were measured using an automatic network analyzer. Measurement shows that the model exactly represents the behavior of GaAs PSVDs under a wide bias condition from –10 to 0.6 V and for frequencies up to 40 GHz.

We have investigated a SiO₂/SiN_x/SiO₂ composite insulation layer structured gate dielectric for an organic thin film transistor (OTFT) with the purpose of improving the performance of the SiO₂ gate insulator. The SiO₂/SiN_x/SiO₂ composite insulation layer was prepared by magnetron sputtering. Compared with the same thickness of a SiO₂ insulation layer device, the SiO₂/SiN_x/SiO₂ composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decreased leakage current. Electrical parameters such as carrier mobility by field effect measurement have been calculated. The performances of different insulating layer devices have been studied, and the results demonstrate that when the insulation layer thickness increases, the off-state current decreases.

The effects of contact electrode size on the photo-voltaic characteristics of polycrystalline-Si p–i–n solar cells have been studied, with respect to a unit-cell pitch size of 1 μ m width. For the non-transparent Al contact electrode with a contact width of 0.05–0.2 μm, the short-circuit current is obviously reduced with increasing contact width, due to a larger area of optical reflection by the electrode. On the other hand, even when using a transparent ITO (indium-tin-oxide) electrode, a larger width of contact electrode may also cause a smaller short-circuit current, due to a larger area of optical absorption by the electrode. However, for this ITO electrode, the contact electrode of 0.05 μm width causes a smaller short-circuit current than that of 0.1 μm width, primarily ascribed to a smaller area for collecting carrier and a larger contact resistance. As a result, while using the ITO contact electrode to enhance the conversion efficiency of the solar cell, a proper width of contact electrode should be employed to optimize the photo-voltaic characteristics.

Based on the principles of metal–semiconductor–metal Schottky barrier photodetectors (MSM-PD), using the carrier rate equations, the circuit simulation model of a GaN-based MSM photovoltaic ultraviolet detector is constructed through an appropriately equivalent process. By using the Pspice analytical function of Cadence soft on the model, the relationship between the photocurrent and the terminal voltage under different UV light powers is analyzed. The result shows that under the given UV power, the photocurrent increases and tends to become saturated gradually as the terminal voltage of the device increases, and that under different UV powers, the photocurrent increases with increasing incident power. Then the analysis of the relationship between the photocurrent and the terminal voltage under the different ratios of interdigital electrode space and width is carried out when the UV power is given. The results show that when the ratio of interdigital electrode space and width (L/W) equals 1, the photocurrent tends to be at a maximum.

A novel capacitance-type relative humidity (RH) sensor based on multi-wall carbon nanotube/SiO₂ (MWCNTs/SiO₂) composite film is reported. Details of the fabrication process, possible sensing mechanism and sensing characteristics, such as linearity and sensitivity, are described. The capacitance of the MWCNTs/SiO₂ composite film shows typical concentration percolation behavior with increasing MWCNT loading. At loadings below the percolation threshold (1.842wt%), the sensor capacitance increases obviously with increasing MWCNTs. The water condensed in the MWCNTs/SiO₂ layer can lower the percolation threshold and increase the sensor capacitance. The sensor with MWCNT concentration of 1wt% has the best properties. The sensor has a humidity sensitivity of about 673 pF/% RH and a linearity correlation of 0.98428. The response time of the sensor to RH is about 40 s and the recovery time is about 2 s.

A linear voltage regulator was irradiated by ⁶⁰Coγ at high and low dose rates with two bias conditions to investigate the dose rate effect. The devices exhibit enhanced low dose rate sensitivity (ELDRS) under both biases. Comparing the enhancement factors between zero and working biases, it was found that the ELDRS is more severe under zero bias conditions. This confirms that the ELDRS is related to the low electric field in a bipolar structure. The reasons for the change in the line regulation and the maximum drive current were analyzed by combining the principle of linear voltage regulator with irradiation response of the transistors and error amplifier in the regulator. This may be helpful for designing radiation hardened devices.

We have designed an air-bridged PhC microcavity with high sensitivity and a high quality factor. The structure parameters of the microcavity are optimized by three-dimensional finite-difference time-domain method. We compare the performance of a silicon-on-insulator PhC microcavity and an air-bridged PhC microcavity, and analyze the effect of the thickness of the slab and the radius of the defect hole on the performance of the air-bridged PhC microcavity. For a thinner slab and a larger defect hole, the sensitivity is higher while the quality factor is lower. For the air-bridged photonic crystal slab, the sensitivity can reach 320-nm/RIU (refractive index unit) while the quality factor keeps a relatively high value of 120 by selecting the proper slab thickness and the defect hole radius, respectively, when the refractive index is 1.33. This is meaningful for low-detection-limit biosensing.

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC). The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom (PN) sequence injection capacitors at the ADC initialization, while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation. The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain, but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors. The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology. The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process. Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage, the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB, respectively. With the calibration, the maximum integral nonlinearity (INL) of the ADC reduces from 4.75-LSB to 0.65-LSB, while the ADC core consumes 82-mW at 3.3-V power supply.

A low power 12-bit 200-kS/s SAR ADC is proposed. This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator. The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB, respectively, with a power consumption of 72 μW at a 200-kS/s sampling rate. The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process. A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain, and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz. The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps. Design trade-offs are carefully considered in designing the baseband circuit, and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%. A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing, and the remaining offset voltage is only 1.87 mV. Implemented in a 0.13-μm SiGe technology with a 0.6-mm² die size, this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL). An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL. We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch. The chip was fabricated in a SMIC 0.13-μ m RF CMOS process with a 1.2-V power supply. The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is –89 and –118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset, respectively; and the reference frequency spur is below –77 dBc. The chip size is 0.32 mm² and the power consumption is 30.6 mW.

A speaker driver applied to class G/class I with a single phase power supply is presented. Gain expanding and compressing technology are employed in the signal processing circuit to optimize power dissipation. The circuit is implemented in 0.18 μm N-well CMOS. Experimental results show that the speaker driver has a good audio sound quality and power efficiency. Less than 0.006% THD at a low power range and less than 0.4% at a medium power range can be obtained with a 1 kHz sine wave signal. Maximum output power of 360 mW can be gained at a load of 8 Ω . The power efficiency is about twice that of a traditional class AB driver at the power range of 80 mW and shows more than 18% improvement at the higher output power range.

A resistorless CMOS current reference is presented. Temperature compensation is achieved by subtracting two sub-currents with different positive temperature coefficients. The circuit has been implemented with a Chartered 0.35 μm CMOS process. The output current is 1.5 μA, and the circuit works properly with a supply voltage down to 2 V. Measurement results show that the temperature coefficient is 98 ppm/℃, and the line regulation is 0.45%/V. The occupied chip area is 0.065 mm².

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band. A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section, which mainly consists of a low noise amplifier (LNA), a down-converter, polyphase filters and summing circuits. An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage. Also, a re-designed wideband double balance mixer is implemented in the down conversion stage, which provides better gain, noise figure and linearity performances. Using a TSMC 0.18μm 1P4M RF CMOS process, a compact 1.27 GHz/1.575 GHz dual-band GNSS frontend is realized in the proposed low-IF topology. The measurements exhibit the gains of 45 dB and 43 dB, and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands, respectively. The frontend model consumes about 11.8–13.5 mA current on a 1.8 V power supply. The core occupies 1.91 × 0.53 mm² while the total die area with ESD is 2.45 × 2.36 mm².

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology's ability to implement high speed digital and integrated high performance mixed-signal circuits. We report a 2 : 1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology. This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic (CML) with 30 transistors. The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single –5 V supply.

A new on-chip temperature compensation circuit for a GaAs-based HBT RF amplifier applied to wireless communication is presented. The simple compensation circuit is composed of one GaAs HBT and five resistors with various values, which allow the power amplifier to achieve better thermal characteristics with a little degradation in performance. It effectively compensates for the temperature variation of the gain and the output power of the power amplifier by regulating the base quiescent bias current. The temperature compensation circuit is applied to a 3-stage integrated power amplifier for wireless communication applications, which results in an improvement in the gain variation from 4.0 to 1.1 dB in the temperature range between –20 and +80℃.

A novel approach for the fabrication of a metal oxide semiconductor (MOS) structure was reported. The process comprises electrochemical deposition of aluminum and zinc layers on a base of nickel–chromium alloy. This two-layer structure was thermally oxidized at 400 ℃ for 40 min to produce thin layers of aluminum oxide as an insulator and zinc oxide as a semiconductor on a metallic substrate. Using deposition parameters, device dimensions and SEM micrographs of the layers, the device parameters were calculated. The resultant MOS structure was characterized by a C–V curve method. From this curve, the device maximum capacitance and threshold voltage were estimated to be about 0.74 nF and –2.9 V, respectively, which are in the order of model-based calculations.

A model for calculating friction torque during the chemical mechanical polishing (CMP) process is presented, and the friction force and torque detection experiments during the CMP process are carried out to verify the model. The results show that the model can well describe the feature of friction torque during CMP processing. The research results provide a theoretical foundation for the CMP endpoint detection method based on the change of the torque of the polishing head rotational spindle.