The current-voltage (I-V) characteristics and the transmission spectrums of zigzag graphene nanoribbon with different spin-configurations are investigated by using the first-principles calculations. It is shown that the current-voltage curves and the transmission spectrums strongly depend on the spin-configurations of the two sides of the ribbon. For the spin-parallel configuration structure, the curve is linear under lower bias voltage; For the spin-antiparallel configuration structure, there is a strong spin-polarization-dependent transmission which implies the ribbon can be used as a spin filter; while for other spin-configurations structures, the curve has the characteristic of semiconductor. It is found that there is a large magneto-resistance(MR) when the bias voltage is small. The impurity in the central scattering region significantly influences the spin-dependent current and the spin filter efficiency, which may lead the large MR to disappear.

We investigate a passivation scheme using hydrogenated amorphous silicon suboxide (a-SiO_x:H) film for industrial solar cell application. The a-SiO_x:H films were deposited using plasma-enhanced chemical vapor deposition (PECVD) by decomposing nitrous oxide, helium and silane at a substrate temperature of around 250 ℃. An extensive study has been carried out on the effect of thermal annealing on carrier lifetime and surface recombination velocity, which affect the final output of the solar cell. Minority carrier lifetimes for the deposited a-SiO_x:H films without and with the thermal annealing on 4 Ωcm p-type float-zone silicon wafers are 270 μs and 670 μs, respectively, correlating to surface recombination velocities of 70 cm/s and 30 cm/s. Optical analysis has revealed a distinct decrease of blue light absorption in the a-SiO_x:H films compared to the commonly used intrinsic amorphous silicon passivation used in solar cells. This paper also reports that the low cost and high quality passivation fabrication sequences employed in this study are suitable for industrial processes.

Transparent conducting antimony doped tin oxide (Sb:SnO₂) thin films have been deposited onto preheated glass substrates using a spray pyrolysis technique by varying the quantity of spraying solution. The structural, morphological, X-ray photoelectron spectroscopy, optical, photoluminescence and electrical properties of these films have been studied. It is found that the films are polycrystalline in nature with a tetragonal crystal structure having orientation along the (211) and (112) planes. Polyhedrons like grains appear in the FE-SEM images. The average grain size increases with increasing spraying quantity. The compositional analysis and electronic behaviour of Sb:SnO₂ thin films were studied using X-ray photoelectron spectroscopy. The binding energy of Sn3d_5/2 for all samples shows the Sn⁴ bonding state from SnO₂. An intensive violet luminescence peak near 395 nm is observed at room temperature due to oxygen vacancies or donor levels formed by Sb⁵ ions. The film deposited with 20 cc solution shows 70% transmittance at 550 nm leading to the highest figure of merit (2.11 × 10^-3 Ω^-1). The resistivity and carrier concentration vary over 1.22 × 10^-3 to 0.89 × 10^-3Ωcm and 5.19 × 10²⁰ to 8.52 × 10²⁰ cm^-3, respectively.

Vacancy structural defect effects on the lattice thermal conductivity of silicon thin films have been investigated with non-equilibrium molecular dynamics simulation. The lattice thermal conductivities decrease with increasing vacancy concentration at all temperatures from 300 to 700 K. Vacancy defects decrease the sample thermal conductivity, and the temperature dependence of thermal conductivity becomes less significant as the temperature increases. The molecular dynamics result is in good agreement with the theoretical analysis values obtained based on the Boltzmann equation. In addition, theoretical analysis indicates that the reduction in the lattice thermal conductivity with vacancy defects can be explained by the enhanced point-defect scattering due to lattice strain.

Vertical p-type gallium arsenide (GaAs) nanowires with pure zinc blende structure were grown on GaAs (111) B substrate by metal-organic chemical vapor deposition via a Au-catalyst vapor-liquid-solid mechanism. The p-type doping was investigated by additional diethyl zinc (DEZn). In the high II/III ratio range (II/III>9.1%), there exists a critical length beyond which kinking takes place. Two possible reasons are discussed. Zn occurrence in the nanowires was verified by energy dispersive X-ray (EDX) analysis. Corresponding to II/III = 0.2%, the doping concentration is about 8 × 10¹⁸ cm^-3.

Water-soluble cadmium telluride (CdTe) nanocrystals were synthesized in aqueous solution with thioglycolic acid (TGA) molecules as a stabilizer. A series of TGA-stabilized CdTe nanocrystals were prepared using sodium tellurite as a tellurium source, which avoids the cumbersome processes associated with H₂Te or NaHTe sources. The synthesized TGA-stabilized CdTe were characterized with X-ray diffraction, TEM and fluorescence spectrophotometer. The particles crystallized predominantly in cubic phase with narrow photoluminescence emission. The effects of reaction time, pH value, and precursor concentration on the photoluminescence properties were investigated in detail.

The resistivity, crystalline structure and effective work function (EWF) of reactive sputtered TaN has been investigated. As-deposited TaN films have an fcc structure. After post-metal annealing (PMA) at 900 ℃, the TaN films deposited with a N₂ flow rate greater than 6.5 sccm keep their fcc structure, while the films deposited with a N₂ flow rate lower than 6.25 sccm exhibit a microstructure change. The flatband voltages of gate stacks with TaN films as gate electrodes on SiO₂ and HfO₂ are also measured. It is concluded that a dipole is formed at the dielectric-TaN interface and its contribution to the EWF of TaN changes with the Ta/N ratio in TaN, the underneath dielectric layer and the PMA conditions.

This paper describes an analytical model for the bulk electron mobility in strained-Si layers as a function of strain. Phonon scattering, columbic scattering and surface roughness scatterings are included to analyze the full mobility model. Analytical explicit calculations of all the parameters to accurately estimate the electron mobility have been made. The results predict an increase in the electron mobility with the application of biaxial strain as also predicted from the basic theory of strain physics of metal oxide semiconductor (MOS) devices. The results have also been compared with the numerically reported results and show good agreement.

The characteristics of a low-voltage triggering silicon-controlled rectifier (LVTSCR) under a transmission line pulse (TLP) and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge (ESD) design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron (UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.

An analytical model of an LDMOSFET with a shield ring is established according to the 2D Poisson equation. Surface electrical field distribution along the drift region is obtained from this model and the influence of shield length and oxide thickness on the electrical field distribution is studied. The robustness of this model is verified using ISE TCAD simulation tools. The breakdown voltage of a specific device is also calculated and the result is in good agreement with experimental data.

Based on the platform of 0.35 μm PDSOI CMOS process technology, the partially depleted silicon-on-insulator dynamic threshold voltage (PDSOI DT) NMOS with an H-gate was implemented. The analog characteristics and RF characteristics of the gate-body contacted dynamic threshold voltage H-gate NMOS and conventional H-gate NMOS were performed and compared. Furthermore, the fundamental operation principle and physical mechanism of the PDSOI H-gate DTMOS compared with the conventional H-gate NMOS are analyzed in detail. The results indicate that the cutoff frequency can reach 40 GHz and the maximum oscillation frequency 29.43 GHz as V_gs = 0.7 V and V_ds = 1 V.

The physical threshold voltage model of pMOSFETs under shallow trench isolation (STI) stress has been developed. The model is verified by 130 nm technology layout dependent measurement data. The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET. The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11% improvement of average delay time. This indicates the importance of STI stress consideration in circuit design.

A transformer-based CMOS power amplifier (PA) is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter. The third harmonic of the power stage and driver stage can be cancelled out in a specific power region. The two-stage PA fabricated in a standard 0.18-μm CMOS process delivers 27.5 dBm with 27% PAE at the 1-dB compression point (P_1dB) and offers 21 dB gain. The PA achieves 5.5 % EVM and meets the spectrum mask at 20.5 dBm average power. Another conventional PA with a zero-cross-point of g_m3 bias is also fabricated and compared to prove its good linearity and efficiency.

A high power semiconductor laser diode with a tapered and cascaded active multimode interferometer (MMI) cavity was designed and demonstrated. An output power as high as 32 mW was obtained for the novel laser diode with a tapered and cascaded active MMI cavity, being much higher than the 9.8 mW output power of the conventional single ridge F–P laser with the same material structure and the same device length due to the larger active area; and also being higher than the 21.2 mW output power of the rectangular and cascaded active MMI laser diode with nearly the same structure, except for the shape of the MMI area. In addition, the tapered and cascaded active multimode interferometer laser showed stable single mode outputs up to the maximum output power.

Two closed-form formulae for the frequency-dependent resistance of rectangular cross-sectional interconnects are presented. The frequency-dependent resistance R(f) of a rectangular interconnect line or a interconnect line with a ground plane structure is first obtained by a numerical method. Based on the strict numerical results, a novel closed-form formula R(f) for a rectangular interconnect alone is fitted out using the Levenberg–Marquardt method. This R(f) can be widely used for analyzing on-chip power grid IR-drop when the frequency is changing. Compared to the previously published R(f) formula for an interconnect, the formula provided here is more accurate during the frequency transition range. Also for a bigger width to thickness ratio, this formula shows greater accuracy and robustness. In addition, this paper fits out the closed-form R(f) formula for a micro-strip-like interconnect (an interconnect with a ground plane), which is a typical structure in the on-chip or package power delivery system.

An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 2.6 mm² area and consumes 83 mW under typical work modes.

A G_m–C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage.

A wideband 8–12 GHz inline type microwave power sensor, which has both working and non-working states, is presented. The power sensor measures the microwave power coupled from a CPW line by a MEMS membrane. In order to reduce microwave losses during the non-working state, a new structure of working state transfer switches is proposed to realize the two working states. The fabrication of the power sensor with two working states is compatible with the GaAs MMIC (monolithic microwave integrated circuit) process. The experimental results show that the power sensor has an insertion loss of 0.18 dB during the non-working state and 0.24 dB during the working state at a frequency of 10 GHz. This means that no microwave power has been coupled from the CPW line during the non-working state.

This paper presents a fully integrated dual-mode 6 to 9 GHz transmitter for both WiMedia and China MB-OFDM UWB applications. The proposed transmitter consists of a dual-mode I/Q LPF, an up-conversion mixer, a two-stage power driver amplifier and a broadband high-speed frequency divider with LO buffers for I/Q LO carrier generation. The measurement results show that the gain ripple of the transmitter is within ±1.5/± 2.8 dB from 6 to 8.7/9 GHz. The output IP3 is about +13.2 dBm, the output 1dBCP is around +2.8 dBm, and the LO leakage/sideband rejection ratio is about –35/–38 dBc. The ESD protected chip is fabricated with a TSMC 0.13 μm RFCMOS process with a die size of 1.6 × 1.3 mm² and the core circuit consumes only 46 mA under a 1.2 V supply.

A fully monolithic power amplifier (PA) for multi-mode front end IC integration is presented. The PA is fabricated in an IBM 7WL 0.18 μm SiGe BiCMOS process with all the matching networks integrated on a chip. After load-pull test to find the best power stage size and layout optimization, the measured results show that the PA can obtain a 24 dBm maximum output power at 2.4 GHz, the output 1 dB compression point is 21 dBm at 5 dBm input, and the PAE is 18%. This PA is complete on-chip tested without any bonding wires and on-board matching, targeting fully power module integration in multi-mode system on chip.

This paper describes the analysis and design of a 0.13 μm CMOS tunable receiver front-end that supports 8 TDD LTE bands, covering the 1.8–2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes. The novel zero-IF receiver core consists of a tunable narrowband variable gain low-noise amplifier (LNA), a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier, an LO divider, a rough gain step variable gain pre-amplifier, a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier. The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band, eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes. The test chip is implemented in an SMIC 0.13 μm 1P8M CMOS process. The full receiver achieves 4.6 dB NF, –14.5 dBm out of band IIP3, 30–94 dB gain range and consumes 54 mA with a 1.2 V power supply.

This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application. The architecture is based on a sampling-detection module and a charge pump phase locked loop. Compared with clock recovery in conventional 13.56 MHz transponders, this circuit can recover a high-precision consecutive carrier clock from the on/off keying (OOK) signal sent by interrogators. Fabricated by a SMIC 0.18-μm EEPROM CMOS process, this chip works from a single power supply as low as 1.5 V. Measurement results show that this circuit provides 0.34% frequency deviation and 8 mV sensitivity.

SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets (SEUs) in space applications. The failure mechanism in FPGA's configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under 4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 μmW with a sensitivity of –9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 μmm CMOS technology and the chip size is 880 × 880 μm².

The non-planarity of a surface post electroplating process is usually dependent on variations of key layout characteristics including line width, line spacing and metal density. A test chip is designed and manufactured in a semiconductor foundry to test the layout dependency of the electroplating process. By checking test data such as field height, array height, step height and SEM photos, some conclusions are made. Line width is a critical factor of topographical shapes such as the step height and height difference. After the electroplating process, the fine line has a thicker copper thickness, while the wide line has the greatest step height. Three typical topographies, conformal-fill, supper-fill and over-fill, are observed. Moreover, quantified effects are found using the test data and explained by theory, which can be used to develop electroplating process modeling and design for manufacturability (DFM) research.

This work focuses on numerical modeling of hydrostatic stress, which is critical to the formation of stress-induced voiding (SIV) in copper damascene interconnects. Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry. In addition, hydrostatic stress is studied through the influences of different low-k dielectrics, barrier layers and line widths of copper lines, and the results indicate that hydrostatic stress is strongly dependent on these factors. Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%–302% compared with traditional FPGAs.

The crystal structure of InSb [111] A/B surfaces shows that this structure is polarized. This means that the surfaces of InSb [111] A and InSb [1 1 1] B contain two different crystallized directions and they have different physical and chemical properties. Experiments were carried out on the InSb [111] A/B surfaces, showing that tartaric acid etchant could create a very smooth surface on the InSb [1 1 1] B without any traces of oxides and etch pit but simultaneously create etch pit on InSb [111] A surfaces. After lapping and polishing, some particles remained on the InSb [1 1 1] B surface, they could not be removed easily by standard cleaning process and if these particles remain on the surface of the substrate, the growth layer was not uniform and some island-like regions were observed. The purpose of this work is to remove these particles on the InSb [1 1 1] B surface. Some morphology images of both surfaces, InSb [111] A/B, will be presented.

Porous silicon (PS) layers were formed on textured crystalline silicon by electrochemical etching in HF-based electrolyte. Optical and electrical properties of the TMAH textured surfaces with PS formation are studied. Moreover, the influences of the initial structures and the anodizing time on the optical and electrical properties of the surfaces after PS formation are investigated. The results show that the TMAH textured surfaces with PS formation present a dramatic decrease in reflectance. The longer the anodizing time is, the lower the reflectance. Moreover, an initial surface with bigger pyramids achieved lower reflectance in a short wavelength range. A minimum reflectance of 3.86% at 460 nm is achieved for a short anodizing time of 2 min. Furthermore, the reflectance spectrum of the sample, which was etched in 3 vol.% TMAH for 25 min and then anodized for 20 min, is extremely flat and lies between 3.67% and 6.15% in the wavelength range from 400 to 1040 nm. In addition, for a short anodizing time, a slight increase in the effective carrier lifetime is observed. Our results indicate that PS layers formed on a TMAH textured surface for a short anodization treatment can be used as both broadband antireflection coatings and passivation layers for the application in solar cells.