Increases in Si content and the calculated Raman spectra acquired from the Si_xGe_1-x alloys reveal that the frequencies of the Ge-Si and Si-Si modes are up-shifted obviously, meanwhile that of the Ge-Ge optical mode is down-shifted, which is strongly dependent on their microstructural changes. The linear decrease and increase caused by their force constant (bond lengths and bond angles) changes, which can be used as a fingerprint to identify the average Si content. The complex microstructural changes induced by increasing Si content can be clearly displayed by Raman spectra transformation.

The adsorption of a half monolayer of Mg atoms on the Si (100)-(2 × 1) surface is studied by using the self-consistent tight binding linear muffin-tin orbital method. Energies of the adsorption systems of Mg atoms on the different sites are calculated. It has been found that the adsorbed Mg atoms are more favorable on the cave site above the surface than any other sites on the Si (100)-(2 × 1) surface and a metastable shallow site also exists above the surface. This is in agreement with the experimental results. The charge transfer and the layer projected density of states are also studied.

Ni²⁺-doped ZnO nanorods with different doping concentrations are prepared via the solvothermal method. The doped ZnO nanorods are characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM), respectively. The amount of Ni²⁺ ions that enter the lattice of ZnO increases with increasing the Ni²⁺/Zn²⁺ molar ratio when the molar ratio of Ni²⁺/Zn²⁺ in the starting solution is lower than 3% and does not change obviously if the mole ratio of Ni²⁺/Zn²⁺ in the starting solution is in the range of 3-10 mol%. The effect of Ni²⁺ doping on the gas-sensing properties is investigated. The results reveal that the amount of Ni²⁺ has a great influence on the response (R_a/R_g) and the gas-sensing selectivity. The sensor based on 1 mol % Ni²⁺ doped ZnO nanorods (120 ℃, 10 h) exhibits a high response to acetic acid vapor, in particular, the responses to 0.001 ppm and 0.01 ppm acetic acid vapor reach 1.6 and 2, respectively. The response time and the recovery time for 0.001 ppm acetic acid are only 4 s and 27 s, respectively.

The electrical characterization of AlGaN/GaN interface is reported. The dependence of two-dimensional electron gas (2-DEG) density at the interface on the Al mole fraction and thickness of AlGaN layer as well as on the thickness of GaN cap layer is presented. This information can be used to design and fabricate AlGaN/GaN based MODFET (modulation doped field effect transistor) for optimum DC and RF characteristics.

The growth process of three-dimensional growth mode (3D) switching to two-dimensional growth mode (2D) is investigated when GaN films are grown on cone-shaped patterned sapphire substrates by metal-organic chemical vapor deposition. The growth condition of the 3D-2D growth process is optimized to reduce the threading dislocation density (TDD). It is found that the condition of the 3D layer is critical. The 3D layer keeps growing under the conditions of low V/III ratio, low temperature, and high pressure until its thickness is comparable to the height of the cone-shaped patterns. Then the 3D layer surrounds the cone-shaped patterns and has inclined side facets and a top (0001) plane. In the following 2D-growth process, inclined side facets coalesce quickly and the interaction of TDs with the side facets causes the TDs to bend over. As a result, the TDD of GaN films can decrease to 1 × 10⁸ cm^-2, giving full-width at half maximum values of 211 and 219 arcsec for (002) and (102) omega scans, respectively.

Polycrystalline silicon (poly-Si) seed layers were fabricated on graphite substrates by magnetron sputtering. It was found that the substrate temperature in the process of magnetron sputtering had an important effect on the crystalline quality, and 700 ℃ was the critical temperature in the formation of Si (220) preferred orientation. When the substrate temperature is higher than 700 ℃, the peak intensity of X-ray diffraction (XRD) from Si (220) increases distinctly with the increasing of substrate temperature. Moreover, the XRD measurements indicate that the structural property and crystalline quality of poly-Si seed layers are determined by the rapid thermal annealing (RTA) temperatures and time. Specifically, a higher annealing temperature and a longer annealing time could enhance the Si (220) preferred orientation of poly-Si seed layers.

Rare-earth elements (Re) Sc and Y doped Mg₂Si thermoelectric materials were made via a field-activated and pressure-assisted synthesis (FAPAS) method at 1023-1073 K, 50 MPa for 15 min. The samples created using this method have uniform and compact structures. The average grain size was about 1.5-2 μm, the micro-content of Re did not change the matrix morphology. A sample with 2500 ppm Sc obtained the best Seebeck coefficient absolute value, about 1.93 times of that belonging to non-doped Mg₂Si at about 408 K. The electric conductivity of the sample doped with 2000 ppm Y becomes 1.69 times of that of pure Mg₂Si at 468 K, while the former had a better comprehensive electrical performance. Their thermal conductivity was reduced to 70% and 84% of that of non-doped Mg₂Si. Thus, the figure of merit and ZT of these two samples were enhanced visibly, which were 3.3 and 2.4 times of the non-doped samples at 408 K and 468 K, respectively. The maximal ZT belonging to samples doped with 2500 ppm Sc went up to 0.42 at about 498 K, higher than 0.40 of sample doped with 2000 ppm Y at 528 K and 0.25 of non-doped Mg₂Si at 678 K, and the samples doped with Sc seemed to get the best thermoelectric performances at lower temperature.

The selection of solvents for SiC nanowires (NWs) in a dielectrophoretic process is discussed theoretically and experimentally. From the viewpoints of dielectrophoresis force and torque, volatility, as well as toxicity, isopropanol (IPA) is considered as a proper candidate. By using the dielectrophoretic process, SiC NWs are aligned and NW thin films are prepared. The densities of the aligned SiC NWs are 2 μm^-1, 4 μm^-1, 6 μm^-1, which corresponds to SiC NW concentrations of 0.1 μg/μL, 0.3 μg/μL and 0.5 μg/μL, respectively. Thin-film transistors are fabricated based on the aligned SiC NWs of 6 μm^-1. The mobility of a typical device is estimated to be 13.4 cm²/(V·s).

An overall analysis of the trench superjunction insulated gate bipolar transistor (SJ IGBT) is presented and a detailed comparison between a trench SJ IGBT and a trench field stop IGBT is made by simulating with Sentaurus TCAD. More specifically, simulation results show that the trench SJ IGBT exhibits a breakdown voltage that is raised by 100 V while the on-state voltage is reduced by 0.2 V. At the same time, the turn-off loss is decreased by 50%. The effect of charge imbalance on the static and dynamic characteristics of the trench SJ IGBT is studied, and the trade-off between parameters and their sensitivity versus charge imbalance is discussed.

A novel short-anoded insulated-gate bipolar transistor (SA-IGBT) with double emitters is proposed. At the on-state, the new structure shows extraordinarily high emission efficiency. Moreover, with a short-contacted anode, it further enhances the hole emission efficiency because of the crowding of the electrons. The forward voltage drop V_F of this structure is 1.74 V at a current density 100 of A/cm². Compared to the conventional NPT IGBT (1.94 V), segment-anode IGBT (SA-NPN 2.1 V), and conventional SA-IGBT (2.33 V), V_F decreased by 10%, 17% and 30%, respectively. Furthermore, no NDR has been detected comparing to the SA-IGBT. At the off-state, there is a channel for extracting excessive carriers in the drift region. The turn-off loss E_off of this proposed structure is 8.64 mJ/cm². Compared to the conventional NPT IGBT (15.3 mJ/cm²), SA-NPN IGBT (12.8 mJ/cm²), and SA-IGBT (12.1 mJ/cm^{2), E_off decreased by 43.7%, 32% and 28%, respectively.}

By way of periphery circuit design of the phase-change memory, it is necessary to present an accurate compact model of a phase-change memory cell for the circuit simulation. Compared with the present model, the model presented in this work includes an analytical conductivity model, which is deduced by means of the carrier transport theory instead of the fitting model based on the measurement. In addition, this model includes an analytical temperature model based on the 1D heat-transfer equation and the phase-transition dynamic model based on the JMA equation to simulate the phase-change process. The above models for phase-change memory are integrated by using Verilog-A language, and results show that this model is able to simulate the I-V characteristics and the programming characteristics accurately.

We demonstrate a 12.5 Gb/s carrier-injection silicon Mach-Zehnder optical modulator. Under a non-return-zero (NRZ) pre-emphasized electrical drive signal with voltage swing of 6.3 V and forward bias of 0.7 V, the eye is clearly opened with an extinction ratio of 8.4 dB. The device exhibits high modulation efficiency, with a figure of merit V_πL of 0.036 V·mm.

An analog baseband circuit for a direct conversion wireless local area network (WLAN) transceiver in a standard 0.13-μm CMOS occupying 1.26 mm² is presented. The circuit consists of active-RC receiver (RX) 4th order elliptic lowpass filters (LPFs), transmitter (TX) 3rd order Chebyshev LPFs, RX programmable gain amplifiers (PGAs) with DC offset cancellation (DCOC) servo loops, and on-chip output buffers. The RX baseband gain can be programmed in the range of -11 to 49 dB in 2 dB steps with 50-30.2 nV/√Hz input referred noise (IRN) and a 21 to -41 dBm in-band 3rd order interception point (IIP3). The RX/TX LPF cutoff frequencies can be switched between 5 MHz, 10 MHz, and 20 MHz to fulfill the multimode 802.11b/g/n requirements. The TX baseband gain of the I/Q paths are tuned separately from -1.6 to 0.9 dB in 0.1 dB steps to calibrate TX I/Q gain mismatches. By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array, the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply.

This paper investigates the noise sources in a single-ended class D amplifier (SECDA) and suggests corresponding ways to lower the noise. The total output noise could be expressed as a function of the gain and noises from different sources. According to the function, the bias voltage (V_B) is a primary noise source, especially for a SECDA with a large gain. A low noise SECDA is obtained by integrating a filter into the SECDA to lower the noise of the V_B. The filter utilizes an active resister and an 80 pF capacitance to get a 3 Hz pole. A noise test and fast Fourier transform analysis show that the noise performance of this SECDA is the same as that of a SECDA with an external filter.

A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed. This structure is based on associating two sets of two capacitors in cross series during the amplification phase. This circuit permits the common-mode voltage of the sample signal to reach full swing. Using the charge-complement technique, the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively. Simulation results show that as sample signal common-mode voltage changes, the difference between the minimum and maximum gain error is less than 0.03%. When the capacitor mismatch is increased from 0 to 0.2%, the gain error is deteriorated by 0.00015%. In all simulations, the gain of amplifier is 69 dB.

A pulse swallowing frequency divider with low power and compact structure is presented. One of the DFFs in the divided by 2/3 prescaler is controlled by the modulus control signal, and automatically powered off when it has no contribution to the operation of the prescaler. The DFFs in the program counter and the swallow counter are shared to compose a compact structure, which reduces the power consumption further. The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28 × 22 μm². The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

A 72 mW highly integrated dual-channel multimode GNSS (global navigation satellite system) receiver with a ΣΔ fractional-N synthesizer which covers GPS L1 and the Compass B1/B2/B3 band is presented. This chip was fabricated in a TSMC CMOS 0.18 μm process and packaged in a 48-pin 3 × 3 mm² land grid array chip scale package. This work achieves NF ≤qslant 5.3 dB without an external LNA, channel gain = 105 dB for channel one (Compass B2 and B3 band), and channel gain = 110 dB for channel two (GPS L1 and Compass B1 band). Image rejection (IMRR) = 36 dB, phase noise is -115.9 dBc @ 1 MHz and -108.9 dBc @ 1 MHz offset from the carrier for the two channels separately. At the low power consumption, multibands of GNSS are compatible in one chip, which is easy for consumers to use, when two different navigation signals are received simultaneously.

This paper presents a programmable gain amplifier (PGA) circuit with a digitally assisted DC offset cancellation (DCOC) scheme for a direct conversion WLAN receiver. Implemented in a standard 0.13-μm CMOS process, the PGA occupies 0.39 mm² die area and dissipates 6.5 mW power from a 1.2 V power supply. By using a single loop single digital-to-analog converter (DAC) mixed signal DC offset cancellation topology, the minimum DCOC settling time achieved is as short as 1.6 μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step. The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode, making the PGA circuit in compliance with the targeted WLAN specifications.

Two different frequency bandwidth subharmonic mixers (SHM) using planar Schottky mixing diodes are discussed and fabricated. Full-wave analysis is carried out to find the optimum diode embedding impedances with a lumped port for modeling the nonlinear junction. The SHM circuit is divided into several different parts and each part is optimized using the calculated diode impedances. The divided parts are then combined and optimized together. The exported S-parameter files of the global circuit are used for conversion loss (CL) discussion. For the 150 GHz SHM, the lowest measured CL is 10.7 dB at 153 GHz, and typical CL is 12.5 dB in the frequency range of 135-165 GHz. The lowest measured CL of the 180 GHz SHM is 5.8 dB at 240 GHz, and typical CL is 13.5 dB and 11.5 dB in the frequency range of 165-200 GHz and 210-240 GHz, respectively.

By researching the ternary flip-flop and the adiabatic Domino circuit, a novel design of low-power ternary Domino JKL flip-flop on the switch level is proposed. First, the switch-level structure of the ternary adiabatic Domino JKL flip-flop is derived according to the switch-signal theory and its truth table. Then the ternary loop operation circuit and ternary reverse loop operation circuit are achieved by employing the ternary JKL flip-flop. Finally, the circuit is simulated by using the Spice tool and the results show that the logic function is correct. The energy consumption of the ternary adiabatic Domino JKL flip-flop is 69% less than its conventional Domino counterpart.

This paper presents an embeddable SOC real-time prediction circuit and method for TDDB. When the SOC under test is fails due to TDDB, the prediction circuit is capable of issuing a warning signal. The prediction circuit, designed by using a standard CMOS process, occupies a small silicon area and does not share any signal with the circuits under test, therefore, the possibility of interference with the surrounding circuits is safely excluded.

This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter (ADC). The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic. Based on the analysis of the output codes, the calibration logic estimates the bit weight of each stage and corrects the outputs. An experimental 14-bit pipelined ADC is fabricated to verify the algorithm. The results show that INL errors drop from 20 LSB to 1.7 LSB, DNL errors drop from 2 LSB to 0.4 LSB, SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB. The linearity of the pipelined ADC is improved significantly.

This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm². Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of -12 dBm.

To achieve a constant current limit, low power consumption and high driving capability, a micro-power LDO with a piecewise voltage-foldback current-limit circuit is presented. The current-limit threshold is dynamically adjusted to achieve a maximum driving capability and lower quiescent current of only 300 nA. To increase the loop stability of the proposed LDO, a high impedance transconductance buffer under a micro quiescent current is designed for splitting the pole that exists at the gate of the pass transistor to the dominant pole, and a zero is designed for the purpose of the second pole phase compensation. The proposed LDO is fabricated in a BiCMOS process. The measurement results show that the short-circuit current of the LDO is 190 mA, the constant limit current under a high drop-out voltage is 440 mA, and the maximum load current under a low drop-out voltage is up to 800 mA. In addition, the quiescent current of the LDO is only 7 μA, the load regulation is about 0.56% on full scale, the line regulation is about 0.012%/V, the PSRR at 120 Hz is 58 dB and the drop-out voltage is only 70 mV when the load current is 250 mA.

This paper describes the design of a 14-bit 20 Msps analog-to-digital converter (ADC), implemented in 0.18 μm CMOS technology, achieving 11.2 effective number of bits at Nyquist rate. An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power. The proposed ADC consumes only 166 mW under 1.8 V supply. A fast background calibration is utilized to ensure the overall ADC linearity.

The chemical mechanical polishing/planarization (CMP) performance of an inhibitor-free alkaline copper slurry is investigated. The results of the Cu dissolution rate (DR) and the polish rate (PR) show that the alkaline slurry without inhibitors has a relatively high copper removal rate and considerable dissolution rate. Although the slurry with inhibitors has a somewhat low DR, the copper removal rate was significantly reduced due to the addition of inhibitors (Benzotriazole, BTA). The results obtained from pattern wafers show that the alkaline slurry without inhibitors has a better planarization efficacy; it can planarize the uneven patterned surface during the excess copper removal. These results indicate that the proposed inhibitor-free copper slurry has a considerable planarization capability for CMP of Cu pattern wafers, it can be applied in the first step of Cu CMP for copper bulk removal.