Electron Raman scattering (ERS) is investigated in a CdS cylindrical quantum dot (QD). The differential cross section is calculated as a function of the scattering frequency and the size of the QD. Single parabolic conduction and valence bands are assumed, and singularities in the spectrum are found and interpreted. The selection rules for the processes are also studied. The ERS studied here can be used to provide direct information about the electron band structure of these systems.

Within the effective-mass and finite-height potential barrier approximation, a theoretical study of the effects of strain and hydrostatic pressure on the exciton emission wavelength and electron-hole recombination rate in wurtzite cylindrical GaN/Al_xGa_1-xN quantum dots (QDs) is performed using a variational approach. Numerical results show that the emission wavelength with strain effect is higher than that without strain effect when the QD height is large (> 3.8 nm), but the status is opposite when the QD height is small (< 3.8 nm). The height of GaN QDs must be less than 5.5 nm for an efficient electron-hole recombination process due to the strain effect. The emission wavelength decreases linearly and the electron-hole recombination rate increases almost linearly with applied hydrostatic pressure. The hydrostatic pressure has a remarkable influence on the emission wavelength for large QDs, and has a significant influence on the electron-hole recombination rate for small QDs. Furthermore, the present numerical outcomes are in qualitative agreement with previous experimental findings under zero pressure.

Phase separations have been studied for graded-indium content In_xGa_1-xN/GaN multiple quantum wells (MQWs) with different indium contents by means of photoluminescence (PL), cathodeluminescence (CL) and time-resolved PL (TRPL) techniques. Besides the main emission peaks, all samples show another 2 peaks at the high and low energy parts of the main peaks in PL when excited at 10 K. CL images show a clear contrast for 3 samples, which indicates an increasing phase separation with increasing indium content. TRPL spectra at 15 K of the main emissions show an increasing delay of rising time with indium content, which means a carrier transferring from low indium content structures to high indium content structures.

Lead iodide single crystal was grown by physical vapor transport method. Two radiation detectors with different configurations were fabricated from the as-grown crystal. The electrical and γ-ray response properties at room temperature of the both detectors were investigated. It is found that the dark resistivity of the detectors are respectively 3×10¹⁰ Ω.cm for bias electric field parallel to crystal c-axis (E∥c) and 2×10⁸ Ω.cm for perpendicular to crystal c-axis (E⊥c). The energy spectrum response measurement shows that both detectors were sensitive to ²⁴¹Am 59.5 keV γ-rays, and achieved a good energy resolution of 16.8% for the E⊥c-axis configuration detector with a full width at half maximum of 9.996 keV.

Undoped and Mg-doped ZnO thin films were deposited on Si (111) and quartz substrates by using the sol-gel method. Microstructure, surface topography and water contact angle of the thin films have been measured by X-ray diffraction (XRD), an atomic force microscope (AFM) and water contact angle apparatus, respectively. The XRD results show that all the thin films are polycrystalline with a hexagonal structure and have a preferred orientation along the c-axis perpendicular to the substrate. With the increase of Mg concentration, the RMS roughness increases from 2.14 to 9.56 nm and the contact angle of the un-irradiated thin films decreases from 89° to 82°. The wetting behavior of the resulting films can be reversibly switched from hydrophobic to hydrophilic, through alternation of UV illumination and dark storage. The light-induced efficiency of the thin films increases with the increase of Mg concentration.

Carbon nanotube (CNT) cathodes prepared by electrophoretic deposition were treated by a combination of nickel electroplating and cathode corrosion technologies. The characteristics of the samples were measured by scanning electron microscopy, energy dispersive X-ray spectroscopy, J-E and F-N plots. After the treatment, the CNT cathodes showed improved field emission properties such as turn-on field, threshold electric field, current density, stability and luminescence uniformity. Concretely, the turn-on field decreased from 0.95 to 0.45 V/μm at an emission current density of 1 mA/cm², and the threshold electric field decreased from 0.99 to 0.46 V/μm at a current density of 3 mA/cm². The maximum current density was up to 7 mA/cm² at a field of 0.48 V/μm. In addition, the current density of the CNT cathodes fluctuated at around 0.7 mA/cm² for 20 h, with an initial current density 0.75 mA/cm². The improvement in field emission properties was found to be due to the exposure of more CNT tips, the wider gaps among the CNTs and the infiltration of nickel particles.

A new model is developed to study the microwave/mm wave characteristics of two-terminal GaN-based transfer electron devices (TEDs), namely a Gunn diode and an impact avalanche transit time (IMPATT) device. Microwave characteristics such as device efficiency and the microwave power generated are computed and compared at D-band (140 GHz center frequency) to see the potentiality of each device under the same operating conditions. It is seen that GaN-based IMPATT devices surpass the Gunn diode in the said frequency region.

An analytical model is used to predict the effects of surface recombination current on the gain and transit time of GaInP/GaAs heterojunction bipolar transistors (HBTs). The present analysis shows that consideration of the recombination current gives current gain values that are comparable to those of the experimental results. The dependence of current gain on temperature, base doping and emitter area are also analyzed, and the variation in collector current with emitter-base voltage, temperature and doping is considered.

A 680 V LDMOS on a thin SOI with an improved field oxide (FOX) and dual field plate was studied experimentally. The FOX structure was formed by an "oxidation-etch-oxidation" process, which took much less time to form, and had a low protrusion profile. A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance. An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field. Using a SimBond SOI wafer with a 1.5 μm top silicon and a 3 μm buried oxide layer, CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V, and the specific on-resistance was 8.2 Ω.mm².

A novel silicon double-RESURF LDMOS structure with an improved breakdown characteristic by substrate bias technology (SB) is reported. The P-type epitaxial layer is embedded between an N-type drift region and an N-type substrate to block the conduction path in the off-state and change the distributions of the bulk electric field. The substrate bias strengthens the charge share effect of the drift region near the source, and the vertical electric field peak under the drain is decreased, which is especially helpful in improving the vertical breakdown voltage in a lateral power device with a thin drift region. The numerical results by MEDICI indicate that the breakdown voltage of the proposed device is increased by 97% compared with a conventional LDMOS, while maintaining a low on-resistance.

Electrical stress experiments under different bias configurations for AlGaN/GaN high electron mobility transistors were performed and analyzed. The electric field applied was found to be the extrinsic cause for the device instability, while the traps were recognized as the main intrinsic factor. The effect of the traps on the device degradation was identified by recovery experiments and pulsed I-V measurements. The total degradation of the devices consists of two parts: recoverable degradation and unrecoverable degradation. The electric field induced traps combined with the inherent ones in the device bulk are mainly responsible for the recoverable degradation.

An ultra-low specific on-resistance (R_on,sp) integrated silicon-on-insulator (SOI) double-gate triple RESURF (reduced surface field) n-type MOSFET (DG T-RESURF) is proposed. The MOSFET features two structures: an integrated double gates structure (DG) that combines a planar gate with an extended trench gate, and a p-type buried layer (BP) in the n-type drift region. First, the DG forms dual conduction channels and shortens the forward current path, so reducing R_on,sp. The DG works as a vertical field plate to improve the breakdown voltage (BV) characteristics. Second, the BP forms a triple RESURF structure (T-RESURF), which not only increases the drift doping concentration but also modulates the electric field. This results in a reduced R_on,sp and an improved BV. Third, the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP. The BV of 325 V and R_on,sp of 8.6 mΩ.cm² are obtained for the DG T-RESURF by simulation. R_on,sp of DG T-RESURF is decreased by 63.4% in comparison with a planar-gate single RESURF MOSFET (PG S-RESURF), and the BV is increased by 9.8%.

We fabricated 88 nm gate-length InP-based InAlAs/InGaAs high electron mobility transistors (HEMTs) with a current gain cutoff frequency of 100 GHz and a maximum oscillation frequency of 185 GHz. The characteristics of HEMTs with side-etched region lengths (L_side) of 300, 412 and 1070 nm were analyzed. With the increase in L_side, the kink effect became notable in the DC characteristics, which resulted from the surface state and the effect of impact ionization. The kink effect was qualitatively explained through energy band diagrams, and then eased off by reducing the L_side. Meanwhile, the L_side dependence of the radio frequency characteristics, which were influenced by the parasitic capacitance, as well as the parasitic resistance of the source and drain, was studied. This work will be of great importance in fabricating high-performance InP HEMTs.

Single event gate rupture (SEGR) is a very important failure mode for power MOSFETs when used in aerospace applications, and the cell regions are widely considered to be the most sensitive to SEGR. However, experimental results show that SEGR can also happen in the gate bus regions. In this paper, we used simulation tools to estimate three structures in power MOSFETs, and found that if certain conditions are met, areas other than cell regions can become sensitive to SEGR. Finally, some proposals are given as to how to reduce SEGR in different regions.

A simple and low cost method is described which improves extraction efficiency. The indium tin oxide (ITO) textured film was fabricated by using the self-assembly method and dry-etching. The surface morphologies and surface roughness were observed by using an atomic force microscope. The I-V characteristics, output power and polar radiation pattern of the LEDs with and without textured ITO were measured for comparison. Cylinders and craters were formed on the ITO surface after the etching, the height of which increased with etching time. The output power of the devices is proportional to the etching time. Total internal reflection of light on the ITO-GaN interface is reduced due to the appearance of cylinders and craters, and their increasing height. Thus, the output power is improved.

A novel semicircular electrode metal-semiconductor-metal (SEMSM) ultraviolet detector is modeled, investigated and characterized with a self-consistent numerical calculation method. For the purpose of model and performance verification, a comprehensive comparison of the SEMSM detector and a conventional electrode MSM detector is carried out with experimental data. The results indicate that the physical models are able to predict the enhanced device features. Moreover, the structural parameters have been adjusted appropriately to optimize the SEMSM detector. The findings show that a device with a 2 μm finger radius and 3 μ m spacing exhibits outstanding characteristics in terms of a peak responsivity of 0.177 A/W at 290 nm, a maximum external quantum efficiency of over 75%, and a comparable normalized photocurrent to dark current ratio of 1.192×10¹¹ W^-1 at 0.3 V bias. These results demonstrate that the SEMSM detector has excellent performance for optoelectronic integrated circuit applications.

This study investigated the resistive switching characteristics of the Ni/HfO₂/Pt structure for nonvolatile memory application. The Ni/HfO₂/Pt device showed bipolar resistive switching (RS) without a forming process, and the formation and rupture of conducting filaments are responsible for the resistive switching phenomenon. In addition, the device showed some excellent memory performances, including a large on/off ratio (> 3×10⁵), very good data retention (> 10³ s @ 200 ℃) and uniformity of switching parameters. Considering these results, the Ni/HfO₂/Pt device has the potential for nonvolatile memory applications.

We prepared macro-porous silicon (MPS) by electrochemical corrosion in a double-tank cell on the surface of single-crystalline P-type silicon. Then, nano-WO₃ films were deposited on MPS layers by DC facing target reactive magnetron sputtering. The morphologies of the MPS and WO₃/MPS samples were investigated by using a field emission scanning electron microscope. The crystallization of WO₃ and the valence of the W in the WO₃/MPS sample were characterized by X-ray diffraction and X-ray photoelectron spectroscopy, respectively. The gas sensing properties of MPS and WO₃/MPS gas sensors were thoroughly measured at room temperature. It can be concluded that: the WO₃/MPS gas sensor shows the gas sensing properties of a P-type semiconductor gas sensor. The WO₃/MPS gas sensor exhibits good recovery characteristics and repeatability to 1 ppm NO₂. The addition of WO₃ can enhance the sensitivity of MPS to NO₂. The long-term stability of a WO₃/MPS gas sensor is better than that of an MPS gas sensor. The sensitivity of the WO₃/MPS gas sensor to NO₂ is higher than that to NH₃ and C₂H₅OH. The selectivity of the MPS to NO₂ is modified by deposited nano-WO₃ film.

We have presented an analysis of the gate leakage current of the IP3 static random access memory (SRAM) cell structure when the cell is in idle mode (performs no data read/write operations) and active mode (performs data read/write operations), along with the requirements for the overall standby leakage power, active write and read powers. A comparison has been drawn with existing SRAM cell structures, the conventional 6T, PP, P4 and P3 cells. At the supply voltage, V_DD = 0.8 V, a reduction of 98%, 99%, 92% and 94% is observed in the gate leakage current in comparison with the 6T, PP, P4 and P3 SRAM cells, respectively, while at V_DD = 0.7 V, it is 97%, 98%, 87% and 84%. A significant reduction is also observed in the overall standby leakage power by 56%, the active write power by 44% and the active read power by 99%, compared with the conventional 6T SRAM cell at V_DD = 0.8 V, with no loss in cell stability and performance with a small area penalty. The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor (CMOS) technology, t_ox = 2.4 nm, V_thn = 0.22 V, V_thp = 0.224 V, V_DD = 0.7 V and 0.8 V, at T = 300 K.

An LC-VCO with an enhanced quality factor (Q) varactor for use in a high-sensitivity GNSS receiver is presented. An enhanced A-MOS varactor is composed of two accumulation-mode MOS (A-MOS) varactors and two bias voltages, which show the improved Q and linearization capacitance-voltage (C-V) curve. The VCO gain (K_VCO) is compensated by a digital switched varactors array (DSVA) over entire sub-bands. Based on the characteristics of an A-MOS, the varactor in a DSVA is a high Q fixed capacitor as it is switched off, and a moderate Q tuning varactor when it is switched on, which keeps the maximal Q for the LC-tank. The proposed circuit is fabricated in a 0.18 μm 1P6M CMOS process. The measured phase noise is better than -122 dBc/Hz at a 1 MHz offset while the measured tuning range is 58.2% and the variation of K_VCO is close to ±21% over the whole of the sub-bands and the effective range of the control voltage. The proposed VCO dissipates less than 5.4 mW over the whole operating range from a 1.8 V supply.

A voltage-controlled oscillator (VCO) with dual stages of accumulation mode varactors for a multi-mode global navigation satellite system (GNSS) application, which adopts sigma-delta fractional-N technology in the synthesizer, is presented. The structure is selected to optimize the frequency coverage and tuning linearity, based on a general analysis of the parasitic capacitance in the coarse tuning switch bank cells, which cover the global positioning system (GPS) and Beidou (BD) bands. The VCO implemented in the 0.18 μm CMOS process can cover the GPS L1, BD B1, B2 and B3 bands with sufficient margin, and exhibits low phase noise by using this tuning curve linearization technique. The equalized K_vco characteristic behavior further offers a wide voltage tuning range and improves the stability of the closed loop.

This paper proposes a 12-bit, 40-Ms/s pipelined analog-to-digital converter (ADC) with an improved high-gain and wide-bandwidth operational amplifier (opamp). Based on the architecture of the proposed ADC, the non-ideal factors of opamps are first analyzed, which have the significant impact on the ADC's resolution. Then, the compensation techniques of the ADC's opamp are presented to restrain the negative effect introduced by the gain-boosting technique and switched-capacitor common-mode-feedback structure. After analysis and optimization, the ADC implemented in a 0.35 μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB, respectively, at a 40 MHz sample clock with over 2 Vpp input range.

A new BPSK demodulator was presented. By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator, the circuit structure of the demodulator became simpler and hence its power consumption became lower. Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system. The proposed BPSK demodulator was implemented by Global Foundries 0.35 μm CMOS technology with a 3.3 V power supply. The designed chip area is only 0.07 mm² and the power consumption is 0.5 mW. The test results show that it can work correctly.

This paper proposes a new low power structure to improve the trade-off between the bandwidth and the power consumption of a programmable gain amplifier (PGA). The PGA consists of three-stage amplifiers, which includes a variable gain amplifier and DC offset cancellation circuits. The cutoff frequency of the DC offset cancellation circuits can be changed from 4 to 80 kHz. The chip was fabricated in 0.13 μ m CMOS technology. Measurement results showed that the gain of the PGA can be programmed from -5 to 60 dB. At the gain setting of 60 dB, the bandwidth can be tuned from 1 to 10 MHz, while the power consumption can be programmed from 850 μA to 3.2 mA at a supply voltage of 1.2 V. Its in-band OIP3 result is at 14 dBm.

A new compact model has been introduced to model on-chip spiral transformers. Unlike conventional models, which are often a compound of two spiral inductor models (i.e., the combination of two coupled ∏ or 2-∏ sub-circuits), our new model only uses 12 elements to model the whole structure in the form of T topology. The new model is based on the physical meaning, and the process of model derivation is also presented. In addition, a simple parameter extraction procedure is proposed to get the elements' values without any fitting and optimization. In this procedure, a new method has been developed for the parameter extraction of the ladder circuit, which is commonly used to represent the skin effect. In order to verify the model's validity and accuracy, we have compared the simulated and measured self-inductance, quality factor, coupling coefficient and insertion loss, and an excellent agreement has been found over a broad frequency range up to the resonant frequency.

This paper studies the typical failure modes and failure mechanisms of non-wetting in an FCBGA (flip chip ball grid array) assembly. We have identified that the residual lead and tin oxide layer on the surface of the die bumps as the primary contributor to non-wetting between die bumps and substrate bumps during the chip-attach reflow process. Experiments with bump reflow parameters revealed that an optimized reflow dwell time and H₂ flow rate in the reflow oven can significantly reduce the amount of lead and tin oxides on the surface of the die bumps, thereby reducing the non-wetting failure rate by about 90%. Both failure analysis results and mass production data validate the non-wetting failure mechanisms identified by this study. As a result of the reflow process optimization, the failure rate associated with non-wetting is significantly reduced, which further saves manufacturing cost and increases capacity utilization.