The authors have reported their recent progress in the research field of ZnO materials as well as the corresponding global advance. Recent results regarding(1) the development of high-quality epitaxy techniques,(2) the defect physics and the Te/N co-doping mechanism for p-type conduction, and(3) the design, realization, and properties of the ZnMgO/ZnO hetero-structures have been shown and discussed. A complete technology of the growth of high-quality ZnO epi-films and nano-crystals has been developed. The co-doping of N plus an iso-valent element to oxygen has been found to be the most hopeful path to overcome the notorious p-type hurdle. High mobility electrons have been observed in low-dimensional structures utilizing the polarization of ZnMgO and ZnO. Very different properties as well as new physics of the electrons in 2DEG and 3DES have been found as compared to the electrons in the bulk.

Tin sulfide(Sn_xS_y) thin films were prepared by a spray ultrasonic technique on glass substrate at 300℃. The influence of deposition time t=2, 4, 6, 8 and 10 min on different properties of thin films, such as(XRD), photoluminescence(PL) and(UV) spectroscopy visible spectrum and four-point were investigated. X-ray diffraction showed that thin films crystallized in SnS₂, SnS, and Sn₂S₃ phases, but the most prominent one is SnS₂. The results of the(UV) spectroscopy visible spectrum show that the film which was deposited at 4 min has a large transmittance of 60% in the visible region. The photoluminescence spectra exhibited the luminescent peaks in the visible region, which shows its potential application in photovoltaic devices. The electrical resistivity(ρ) values of Sn_xS_y films have changed from 8.1×10^-4 to 1.62Ω·cm with deposition time.

We apply the Heyd-Scuseria-Ernzerhof hybrid functional calculation to study the(2, 3) nanotube co-doped with various compositions of nitrogen and boron atoms. We find that the bandgaps and other properties of doped nanotubes oscillate with the doped compositions. Our study should shed light on the understanding of the properties of doped small nanotubes. This might have potential in designing new nano electronic-devices.

The effect of relaxation on the energetics and electronic structure of clean Ag₃PO₄(111) surface has been studied, carried out using first-principles density functional theory(DFT) incorporating the GGA+U formalism. After atomic relaxation of the Ag₃PO₄(111) surface, it is found that O atoms are exposed to the outermost surface, due to an inward displacement of more than 0.06 nm for the two threefold-coordinated Ag atoms and an outward displacement of about 0.004 nm for three O atoms in the sublayer. The atomic relaxations result in a large transfer of surface charges from the outermost layer to the inner layer, and the surface bonds have a rehybridization, which makes the covalence increase and thus causes the surface bonds to shorten. The calculated energy band structures and density of states of the Ag₃PO₄(111) surface present that the atomic relaxation narrows the valence band width 0.15 eV and increases the band gap width 0.26 eV. Meantime, the two surface peaks for the unrelaxed structure disappear at the top of the valence band and the bottom of the conduction band after the relaxed structure, which induces the transformation from a metallic to a semi-conducting characteristic.

The tungsten trioxide(WO₃) thin films were firstly prepared by spin-coating-pyrolysis methods using the ammonium metatungstate((NH₄)₆H₂W₁₂O₄₀) DMF/water solution, and successfully applied as the efficient compact layers for the planar perovskite solar cells. The influence of the WO₃ film thickness and the rinsing treatment of CH₃NH₃PbI₃ thin film with isopropanol on the photovoltaic performance of the corresponding perovskite solar cells was systematically investigated. The results revealed that the perovskite solar cell with a 62 nm thick WO₃ compact layer achieved a photoelectric conversion efficiency of 5.72%, with a short circuit photocurrent density of 17.39 mA/cm², an open circuit voltage of 0.58 V and a fill factor of 0.57. The photoelectric conversion efficiency was improved from 5.72% to 7.04% by the isopropanol rinsing treatment.

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.

A new 22-element small signal equivalent circuit model for the AlGaN/GaN high electron mobility transistor(HEMT) is presented. Compared with the traditional equivalent circuit model, the gate forward and breakdown conductions(G_gsf and G_gdf) are introduced into the new model to characterize the gate leakage current. Additionally, for the new gate-connected field plate and the source-connected field plate of the device, an improved method for extracting the parasitic capacitances is proposed, which can be applied to the small-signal extraction for an asymmetric device. To verify the model, S-parameters are obtained from the modeling and measurements. The good agreement between the measured and the simulated results indicate that this model is accurate, stable and comparatively clear in physical significance.

Radiation-induced 1/f noise degradation in the LM117 bipolar linear voltage regulator is studied. Based on the radiation-induced degradation mechanism of the output voltage, it is suggested that the band-gap reference subcircuit is the critical component which leads to the 1/f noise degradation of the LM117. The radiation makes the base surface current of the bipolar junction transistors of the band-gap reference subcircuit increase, which leads to an increase in the output 1/f noise of the LM117. Compared to the output voltage, the 1/f noise parameter is more sensitive, it may be used to evaluate the radiation resistance capability of LM117.

Silicon junction field effect transistors(JFETs) have been exposed to Co⁶⁰ γ-rays to study radiation-induced effects on their dc characteristics and noise. The devices have been irradiated and measured at room temperature up to an accumulated 100 krad(Si) dose of γ radiation at a dose rate of 0.1 rad(Si)/s. During irradiation, the generation-recombination(g-r) noise increase has been observed while the dc characteristics of the transistors were kept unchanged. The increasing of the density of the same type point defects and their probability of trapping and detrapping carriers caused by irradiation have been used to explain the g-r noise amplitude increase, while the g-r noise characteristic frequency has only a slight change.

HfGdO high-k gate dielectric thin films were deposited on Ge substrates by radio-frequency magnetron sputtering. The current transport properties of Al(Pt)/HfGdO/Ge MOS structures were investigated at room temperature. The results show that the leakage currents are mainly induced by Frenkel-Poole emissions at a low electric field. At a high electric field, Fowler Nordheim tunneling dominates the current. The energy barriers were obtained by analyzing the Fowler Nordheim tunneling characteristics, which are 1.62 eV and 2.77 eV for Al/HfGdO and Pt/HfGdO, respectively. The energy band alignments for metal/HfGdO/Ge capacitors are summarized together with the results of current-voltage and the x-ray photoelectron spectroscopy.

We present a single-mode laser on a p-InP substrate suitable for bonding on silicon-on-insulator(SOI) wafer. The laser can realize single mode lasing with etching perturbing slots by standard photolithography and an inductively coupled-plasma(ICP) etching technique without any regrowth steps. The parameters were designed using the simulation tool "cavity modeling framework"(CAMFR). The single mode of 1539 nm wavelength at the threshold current of 130 mA with the maximum output power of 3.9 mW was obtained at 10℃ in continuous-wave operation. The simple technology, low cost and the single-mode characteristics make the broad area slotted single-mode FP laser a promising light source on the silicon-based optical interconnection applications.

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

A 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) without dedicated front-end sample-and-hold amplifier(SHA) is presented. In addition to elaborate matching of the sampling network in the first stage, a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18-μm CMOS technology, the presented ADC occupies a chip area of 12 mm², and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-dB signal-to-noise and distortion ratio(SNDR), an 85.4-dB spurious-free dynamic range(SFDR), a maximum differential nonlinearity(DNL) of 0.22 LSB and a maximum integral nonlinearity(INL) of 1.4 LSB.

A 16-bit 170 MS/s pipelined ADC implemented in 0.18μm CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 dBFS, an SFDR of 97.6 dBc for a 10 MHz input signal, while preserving an SFDR>80 dBc up to 300 MHz input frequency. The ADC consumes 430 mW from a 1.8 V supply and occupies a 17 mm² active area.

A 2.5 GS/s 14-bit D/A converter(DAC) with 8 to 1 MUX is presented. This 14-bit DAC uses a "5+9" segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT(process, source voltage and temperature) corner is also presented. The 8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a "5-31" decoder is used to improve the DAC's dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer(DDS) chip, and is implemented in a 0.18μm CMOS technology, occupies 4.86×2.28 mm² including bond pads(DAC only), and the measured performance is SFDR>40 dB(with and without DEM) for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure(means return-to-zero or quad-switch structure is unutilized), this paper DAC's clock frequency(2.5 GHz) and higher output frequency SFDR(>40 dB, up to 1 GHz) has some competition.

This paper presents a transmit physical coding sublayer(PCS) circuit for 100G Ethernet. Based on the 4×25 Gb/s architecture according to the IEEE P802.3ba and IEEE P802.3bm^TM/D1.1 standards, this PCS circuit is designed using a semi-custom design method and consists of 4 modules including 64B/66B encoder, scrambler, multiple lanes distribution and 66:8 gearbox. By using the pipeline structure and several optimization techniques, the working speed of the circuit is increased significantly. The parallel scrambling combined with logic optimization also improve the performance. In addition, a kind of phase-independent structure is employed in the design of the gearbox to ensure it can work stably and reliably at high frequency. This PCS circuit has been fabricated based on 0.18μm CMOS technology and the total area is 1.7×1.7 mm². Measured results show that the circuit can work properly at 100 Gb/s and the power consumption is about 284 mW with a 1.8 V supply.

Based on ANSYS and Icepak softwares, the numerical analysis method is used to build up the thermal analysis model of the 2.5D package, which contains a high power CPU chip. The focus of the research is on the determination of the contributing factors and their effects on the thermal resistance and heat distribution of the package. The parametric analysis illustrates that the substrate conductivity, TIM conductivity and fin height are more crucial for heat conduction in the package. Furthermore, these major parameters are compared and analyzed by orthogonal tests, and the optimal solution for 2.5D integration is proposed. The factors' influence patterns on thermal resistance, obtained in this article, could be utilized as a thermal design reference.

An abrasive free chemical mechanical planarization(AFCMP) of semi-polar(11$\bar{2}$2) AlN surface has been demonstrated. The effect of slurry pH, polishing pressure, and platen velocity on the material removal rate(MRR) and surface quality(RMS roughness) have been studied. The effect of polishing pressure on the AFCMP of the(11$\bar{2}$2) AlN surface has been compared with that of the(11$\bar{2}$2) AlGaN surface. The maximum MRR has been found to be ~562 nm/h for the semi-polar(11$\bar{2}$2) AlN surface, under the experimental conditions of 38 kPa pressure, 90 rpm platen velocity, 30 rpm carrier velocity, slurry pH 3 and 0.4 M oxidizer concentration. The best root mean square(RMS) surface roughness of ~1.2 nm and ~0.7 nm, over a large scanning area of 0.70×0.96 mm², has been achieved on AFCMP processed semi-polar(11$\bar{2}$2) AlN and(AlGaN) surfaces using optimized slurry chemistry and processing parameters.

Molecular dynamic simulation is performed to study the process of material annealing caused by a 266 nm pulsed laser. A micro-mechanism describing behaviors of silicon and impurity atoms during the laser annealing at a non-melt regime is proposed. After ion implantation, the surface of the Si wafer is acted by a high energy laser pulse, which loosens the material and partially frees both Si and impurity atoms. While the residual laser energy is absorbed by valence electrons, these atoms are recoiled and relocated to finally form a crystal. Energy-related movement behavior is observed by using the molecular dynamic method. The non-melt laser anneal appears to be quite sensitive to the energy density of the laser, as a small excess energy may causes a significant impurity diffusion. Such a result is also supported by our laser anneal experiment.

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