Two kinds of continuous-wave GaN-based ultraviolet laser diodes (LDs) operated at room temperature and with different emission wavelengths are demonstrated.The LDs epitaxial layers are grown on GaN substrate by metalorganic chemical vapor deposition, with a 10×600 μm2 ridge waveguide structure.The electrical and optical characteristics of the ultraviolet LDs are investigated under direct-current injection at room temperature. The stimulated emission peak wavelength of first LD is 392.9 nm, the threshold current density and voltage is 1.5 kA/cm2 and 5.0 V, respectively.The output light power is 80 mW under the 4.0 kA/cm2 injection current density. The stimulated emission peak wavelength of second LD is 381.9 nm, the threshold current density the voltage is 2.8 kA/cm2 and 5.5 V, respectively.The output light power is 14 mW under a 4.0 kA/cm2 injection current density.
The effect of annealing on vertically aligned TiO2 NWs deposited by glancing angle deposition (GLAD) method on Si substrate using pressed and sintered TiO2 pellets as source material is studied.The FE-SEM images reveal the retention of vertically aligned NWs on Si substrate after annealing process.The EDS analysis of TiO2 NWs sample annealed at 600 ℃ in air for 1 h shows the higher weight percentage ratio of ~2.6(i.e., 72.27% oxygen and 27.73% titanium).The XRD pattern reveals that the polycrystalline nature of anatase TiO2 dominates the annealed NWs sample.The electrical characteristics of Al/TiO2-NWs/TiO2-TF/p-Si (NW device) and Al/TiO2-TF/p-Si (TF device) based on annealed samples are compared.It is riveting to observe a lower leakage current of ~1.32×10-7 A/cm2 at+1 V with interface trap density of ~6.71×1011 eV-1cm-2 in NW device compared to ~2.23×10-7 A/cm2 in TF device.The dominant leakage mechanism is investigated to be generally Schottky emission; however Poole-Frenkel emission also takes place during high reverse bias beyond 4 V for NWs and 3 V for TF device.
Zinc oxide thin films have been grown by electrodeposition technique onto Cu and ITO-coated glass substrates from an aqueous zinc nitrate solution with addition of sodium thiosulfate at 90℃.The effects of sodium thiosulfate on the electrochemical deposition of ZnO were investigated by cyclic voltammetry and chronoamperometry techniques.Deposited films were obtained at-0:60 V vs.SCE and characterized by XRD, SEM, FTIR, optical, photoelectrochemical and electrical measurements.Thickness of the deposited film was measured to be 357 nm.X-ray diffraction results indicated that the synthesized ZnO has a pure hexagonal wurtzite structure with a marked preferential orientation along (002) plane.FTIR results confirmed the presence of ZnO films at peak 558 cm-1.SEM images showed uniform, compact morphology without any cracks and films composed of large flower-like ZnO agglomerates with star-shape.Optical properties of ZnO reveal a high optical transmission (>80%) and high absorption coefficient (α>105 cm-1) in visible region.The optical energy band gap was found to be 3.28 eV.Photoelectrochemical measurements indicated that the ZnO films had n-type semiconductor conduction.Electrical properties of ZnO films showed a low electrical resistivity of 6.54 Ω·cm, carrier concentration of-1.3×1017cm-3 and mobility of 7.35 cm2V-1s-1.
Carbon nanotubes have potential applications in flexible and stretchable devices due to their remarkable electromechanical properties. Flexible and stretchable strain sensors of multi-walled carbon nanotubes (MWCNTs) with aligned or random structures were fabricated on poly-dimethylsiloxane (PDMS) substrate with different techniques. It was observed that the spraycoatedtechniquebased strain sensor fabricated on PDMS substrate showed higher sensitivity higher stretchability, better linearity and excellent longer time stability than the sensor fabricated with other methods presented in this work. The scanning electron microscopy images indicated the spray coating technique can produce a better uniform and compact CNT network, which is the important role affecting the performance of CNT-based flexible strain sensors.
Co-Pi and FeOOH cocatalysts were in-situ deposited on the surface of nanoporous BiVO4 photoelectrodes. The FeOOH cocatalyst has little effect on the BiVO4 samples'morphologies, while the electrodeposited Co-Pi cocatalyst seems to affect the surface of BiVO4.The impedance intensity modulated photocurrent spectroscopy (IMPS), Mott-Schottky (M-S) techniques characterize BiVO4 samples photoelectrochemical performance with the deposition of Co-Pi and FeOOH.The Co-Pi/BiVO4 shows better photoelectrochemical performance than the FeOOH/BiVO4, but the FeOOH/BiVO4 exhibited the better stabilities.The flat band potential and slope of M-S plotof FeOOH/BiVO4 have little variations compared with BiVO4.In contrast, Co-Pi/BiVO4 exhibited the down shifted flat band potential, which is beneficial for the photoelectrochemical water oxidation.The electron transfer measurements revealed that the deposition of FeOOH and Co-Pi onto BiVO4 significantly enhanced the photoelectrochemical performance via reducing the interface resistance and promoting the electron transport.Furthermore, Co-Pi cocatalysts can further pin the transport-limiting traps and significantly facilitate the electron transport.
The temperature coefficient of resistance (abbreviated as TCR) of thin film resistors on some sensor chips, such as thermal converters, should be less than several ppm/℃.However, the TCR of reported thin films is larger than 5 ppm/℃.In this paper, Ni24.9Cr72.5Si2.6 films are deposited on silicon dioxide film by DC and RF magnetron sputtering.Then as-deposited films are annealed at 450℃ under different durations in N2 atmosphere. The sheet resistance of thin films with various thickness and annealing time are measured by the four probe resistivity test system at temperature of 20, 50, 100, 150, and 200℃ and then the TCR of thin films are calculated. Experimental results show that the film with the TCR of only-0.86 ppm/℃ can be achieved by RF magnetron sputtering and appropriate annealing conditions.
A parametric study for a series of technological and geometrical parameters affecting rise time of Al/a-SiC/c-Si (p)/c-Si (n+)/Al thyristor-like switches, is presented here for the first time, using two-dimensional simulation techniques.By varying anode current values in simulation procedure we achieved very good agreement between simulation and experimental results for the rising time characteristics of the switch.A series of factors affecting the rising time of the switches are studied here.Two factors among all others studied here, exerting most significant influence, of more than one order of magnitude on the rising time, are a-SiC and c-Si (p) region widths, validating our earlier presented model for device operation.The above widths can be easily varied on device manufacture procedure.We also successfully simulated the rising time characteristics of our earlier presented simulated improved switch, with forward breakover voltage VBF=11 V and forward voltage drop VF=9.5 V at the ON state, exhibiting an ultra low rise time value of less than 10 ps, which in conjunction with its high anode current density values of 12 A/mm2 and also cheap and easy fabrication techniques, makes this switch appropriate for ESD protection as well as RF MEMS and NEMS applications.
A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor (SG-JLTFET) has been reported which shows excellent dc characteristics at low power supply operation. This device has a thin uniformly n-type doped channel of GaSb i.e. gallium antimonide which is grown epitaxially over silicon substrate. The DC performance parameters such as ION, ION/IOFF, average and point subthreshold slope as well as device parameters for analog applications viz. transconductance gm, transconductance generation efficiency gm/ID, various capacitances and the unity gain frequency fT are studied using a device simulator. Along with examining its endurance to short channel effects, the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET (DG-JLTFET). The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.
The Au/Ti/n-GaAs structures with and without Al2O3 interfacial layer have been fabricated.The Al2O3 interfacial layer has been formed on the GaAs substrate by atomic layer deposition.The effects of the interfacial layer on the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the devices have been investigated in the temperature range of 60-300 K.It has been seen that the carrier concentration from C-V characteristics for the MIS (metal/insulating layer/semiconductor) diode with Al2O3 interfacial layer has a higher value than that for the reference diode without the Al2O3 interfacial layer (MS).Such a difference in the doping concentration has been attributed not to doping variation in the semiconductor bulk but to the presence of the Al2O3 interfacial layer because both diodes have been made on the pieces cut from the same n-type GaAs wafer.The temperaturedependent I-V characteristics of the MIS diode do not obey the thermionic emission current theory because of the presence of the Al2O3 layer.An electron tunneling factor, aδ (χ)1/2, value of 20.64 has been found from the I-V-T data of the MIS diode.An average value of 0.627 eV for the mean tunneling barrier height, χ, presented by the Al2O3 layer has been obtained.
The thermal characteristics of high-power AlGaAs/GaAs laser diodes (LDs) at high current (2-10 A) are studied with electrical transient method. The temperature rise increases linearly with the current. The thermal resistance of chip is the largest proportion of total thermal resistance. By increasing the width of the chip from 500 to 800 μm, the temperature rise and thermal resistance decrease by 8.5% and 8.8%, respectively.
We put forward an n-ZnO/p-Si heterojunction solar cell model based on AFORS-HET simulations and provide experimental support in this article. ZnO:B (B-doped ZnO) thin films deposited by metal-organic chemical vapor deposition (MOCVD) are planned to act as electrical emitter layer on p-type c-Si substrate for photovoltaic applications. We investigate the effects of thickness, buffer layer, ZnO:B affinity and work function of electrodes on performances of solar cells through computer simulations using AFORS-HET software package. The energy conversion efficiency of the ZnO:B (n)/ZnO/c-Si (p) solar cell can achieve 17.16% (Voc: 675.8 mV, Jsc:30.24 mA/cm2, FF: 83.96%) via simulation. On a basis of optimized conditions in simulation, we carry out some experiments, which testify that the ZnO buffer layer of 20 nm contributes to improving performances of solar cells. The influences of growth temperature, thickness and diborane (B2H6) flow rates are also discussed. We achieve an appropriate condition for the fabrication of the solar cells using the MOCVD technique. The obtained conversion efficiency reaches 2.82% (Voc: 294.4 mV, Jsc: 26.108 mA/cm2, FF: 36.66%).
Pre-strained nanomembranes with four embedded quantum wells (QWs) are rolled up into three dimensional (3D) tubular QW infrared photodetectors (QWIPs), which are based on the QW intersubband transition (ISBT).A redshift of~0.42 meV in photocurrent response spectra is observed and attributed to two strain contributions due to the rolling of the pre-strained nanomembranes.One is the overall strain that mainly leads to a redshift of~0.5 meV, and the other is the strain gradient which results in a very tiny variation.The blue shift of the photocurrent response spectra with the external bias are also observed as quantum-confined Stark effect (QCSE) in the ISBT.
We present the design of a diffractive grating structure and get the optimal parameters which can achieve more than 75% coupling efficiency (CE) between single-mode fiber and silicon-on-insulator (SOI) waveguide through 2D finite-different time-domain (FDTD) simulation. The proposed architecture has a uniform structure with no bottom reflection element or silicon overlay. The structure, including grating couplers, adiabatic tapers and interconnection waveguides can be fabricated on the SOI waveguide with only a single electron-beam lithography (ICP) step, which is CMOS-compatible. A relatively high coupling efficiency of 47.2% was obtained at a wavelength of 1562 nm.
A high performance 3 inch 0.5 μm InP DHBT technology with three interconnecting layers has been developed. The epitaxial layer structure and geometry parameters of the device were carefully studied to get the required performances. The 0.5×5 μm2 InP DHBTs demonstrated ft=350 GHz, fmax=532 GHz and BVCEO=4.8 V, which were modeled using Agilent-HBT large signal model. As a benchmark circuit, a dynamic frequency divider operating from 110 to 220 GHz has been designed, fabricated and measured with this technology. The ultra-high-speed 0.5 μm InP DHBT technology offers a combination of ultra-high-speed and high breakdown voltage, which makes it an ideal candidate for next generation 100 GHz+ mixed signal integrated circuits.
A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive VTH shift within 0.4 V and negative VTH shift within-1.2 V and it is robust and promising for high-resolution display.
A common-gate bootstrapped CMOS rectifier dedicated for VHF (very high frequency) isolated DC-DC converter is proposed.It uses common-gate bootstrapped technique to compensate the power loss due to the threshold voltage, and to solve the reflux problem in the conventional rectifier circuit.As a result, it improves the power conversion efficiency (PCE) and voltage conversion ratio (VCR).The design saves almost 90% of the area compared to a previously reported double capacitor structure.In addition, we compare the previous rectifier with the proposed common-gate bootstrapped rectifier in the case of the same area; simulation results show that the PCE and VCR of the proposed structure are superior to other structures.The proposed common-gate bootstrapped rectifier was fabricated by using CSMC 0.5 μm BCD process.The measured maximum PCE is 86% and VCR achieves 77% at the operating frequency of 20 MHz.The average PCE is about 79% and average VCR achieves 71% in the frequency range of 30-70 MHz.Measured PCE and VCR have been improved compared to previous results.
The electromagnetic shielding film has drawn much attention due to its wide applications in the integrated circuit package, which demands a high surface quality of epoxy resin. However, gaseous Cu will splash and adhere to epoxy resin surface when the Cu layer in PCB receives enough energy in the process of laser cutting, which has a negative effect on the quality of the shielding film. Laser polishing technology can solve this problem and it can effectively improve the quality of epoxy resin surface. The paper studies the mechanism of Cu powder spraying on the compound surface by 355 nm ultraviolet (UV) laser, including the parameters of laser polishing process and the remains of Cu content on compound surface. The results show that minimal Cu content can be realized with a scanning speed of 700 mm/s, a laser frequency of 50 kHz and the distance between laser focus and product top surface of -1.3 mm. This result is important to obtain an epoxy resin surface with high quality.
In this paper, the etching characteristics of the ultra-high resistivity silicon (UHRS) by using the Bosch process were investigated. The experimental results indicated that the sulfur hexafluoride flux, the temperature of the substrate, the platen power and the etching intermittence had important influence on the etching rate and the etching morphology of the UHRS. The profiles and morphologies of sidewall were characterized with scanning electron microscopy (SEM). By using an improved three-stage Bosch process, 380-μm deep through holes were fabricated on the UHRS with the average etching rate of about 3.14 μm/min. Meanwhile, the fabrication mechanism of deep through holes on the UHRS by using the three-stage Bosch process was illustrated on the basis of the experimental results.
