Magnetic tunnel junction (MTJ) based spin transfer torque magnetic random access memory (STT-MRAM) has been gaining tremendous momentum in high performance microcontroller (MCU) applications. As eFlash-replacement type MRAM approaches mass production, there is an increasing demand for non-volatile RAM (nvRAM) technologies that offer fast write speed and high endurance. In this work, we demonstrate highly reliable 4 Mb nvRAM type MRAM suitable for industry and auto grade-1 applications. This nvRAM features retention over 10 years at 125 °C, endurance of 1 × 10¹² cycles with 20 ns write speed, making it ideal for applications requiring both high speed and broad temperature ranges. By employing innovative MTJ materials, process engineering, and a co-optimization of process and design, reliable read and write performance across the full temperature range between −40 to 125 °C, and array yield that meets sub-1 ppm error rate was significantly improved from 0 to above 95%, a concrete step toward applications.

Besides the common short-channel effect (SCE) of threshold voltage (V_th) roll-off during the channel length (L) downscaling of InGaZnO (IGZO) thin-film transistors (TFTs), an opposite V_th roll-up was reported in this work. Both roll-off and roll-up effects of V_th were comparatively investigated on IGZO transistors with varied gate insulator (GI), source/drain (S/D), and device architecture. For IGZO transistors with thinner GI, the SCE was attenuated due to the enhanced gate controllability over the variation of channel carrier concentration, while the V_th roll-up became more noteworthy. The latter was found to depend on the relative ratio of S/D series resistance (R_SD) over channel resistance (R_CH), as verified on transistors with different S/D. Thus, an ideal S/D engineering with small R_SD but weak dopant diffusion is highly expected during the downscaling of L and GI in IGZO transistors.

In recent years, as the dimensions of the conventional semiconductor technology is approaching the physical limits, while the multifunction circuits are restricted by the relatively fixed characteristics of the traditional metal−oxide−semiconductor field-effect transistors, reconfigurable devices that can realize reconfigurable characteristics and multiple functions at device level have been seen as a promising method to improve integration density and reduce power consumption. Owing to the ultrathin structure, effective control of the electronic characteristics and ability to modulate structural defects, two-dimensional (2D) materials have been widely used to fabricate reconfigurable devices. In this review, we summarize the working principles and related logic applications of reconfigurable devices based on 2D materials, including generating tunable anti-ambipolar responses and demonstrating nonvolatile operations. Furthermore, we discuss the analog signal processing applications of anti-ambipolar transistors and the artificial intelligence hardware implementations based on reconfigurable transistors and memristors, respectively, therefore highlighting the outstanding advantages of reconfigurable devices in footprint, energy consumption and performance. Finally, we discuss the challenges of the 2D materials-based reconfigurable devices.

One of the core semiconductor devices is the electrostatic chuck. It has been widely used in plasma-based and vacuum-based semiconductor processing. The electrostatic chuck plays an important role in adsorbing and cooling/heating wafers, and has technical advantages on non-edge exclusion, high reliability, wafer planarity, particles reduction and so on. This article extracts key design elements from the existing knowledge and techniques of electrostatic chuck by the method proposed by Paul and Beitz, and establishes a design space systematically. The design space is composed of working objects, working principles and working structures. The working objects involve electrostatic chuck components and materials, classifications, and relevant properties; the working principles involve clamping force, residual force, and temperature control; the working structures describe how to compose an electrostatic chuck and to fulfill the overall functions. The systematic design space exhibits the main issues during electrostatic chuck design. The design space will facilitate and inspire designers to improve the design quality and shorten the design time in the conceptual design.

A two-way K/Ka-band series Doherty-PA(SDPA) with a distributed impedance inverting network (IIN) for millimeter wave applications is presented in this article. The proposed distributed IIN contributes to achieve wideband linear and power back-off (PBO) efficiency enhancement. Implemented in 65nm bulk CMOS technology, this work realizes a measured 3 dB bandwidth of 15.5 GHz with 21.2 dB peak small-signal gain at 34.2 GHz. Under 1-V power supply, it achieves OP_1dB over 13.4 dBm and P_sat over 16 dBm between 21 to 30 GHz. The measured maximum P_sat, OP_1dB, peak/OP_1dB/6dB_PBO PAE results are 17.5 dBm, 14.7 dBm, and 28.2%/23.2%/13.2%. Without digital pre-distortion (DPD) and equalization, EVMs are lower than −25.2 dB for 200 MHz 64-QAM signals. Besides, this work achieves −33.35, −23.52, and −20 dB EVMs for 100 MHz 256-QAM, 600 MHz 64-QAM and 2 GHz 16-QAM signals at 27 GHz without DPD and equalization.

Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

A 4H−SiC superjunction (SJ) MOSFET (SJMOS) with integrated high−K gate dielectric and split gate (HKSG−SJMOS) is proposed in this paper. The key features of HKSG−SJMOS involve the utilization of high−K (HK) dielectric as the gate dielectric, which surrounds the source−connected split gate (SG) and metal gate. The high−K gate dielectric optimizes the electric field distribution within the drift region, creating a low−resistance conductive channel. This enhancement leads to an increase in the breakdown voltage (BV) and a reduction in the specific on resistance (R_on,sp). The introduction of split gate surrounded by high−K dielectric reduces the gate−drain capacitance (C_gd) and gate−drain charge (Q_gd), which improves the switching characteristics. The simulation results indicate that compared to conventional 4H−SiC SJMOS, the HKSG−SJMOS exhibits a 110.5% enhancement in figure of merit (FOM, FOM = BV²/R_on,sp), a 93.6% reduction in the high frequency figure of merit (HFFOM) of R_on,sp · C_gd, and reductions in turn−on loss (E_on) and turn−off loss (E_off) by 38.3% and 31.6%, respectively. Furthermore, the reverse recovery characteristics of HKSG−SJMOS has also discussed, revealing superior performance compared to conventional 4H−SiC SJMOS.

Optical network-on-chip (ONoC) systems have emerged as a promising solution to overcome limitations of traditional electronic interconnects. Efficient ONoC architectures rely on optical routers, enabling high-speed data transfer, efficient routing, and scalability. This paper presents a comprehensive survey analyzing optical router designs, specifically microring resonators (MRRs), Mach−Zehnder interferometers (MZIs), and hybrid architectures. Selected comparison criteria, chosen for their critical importance, significantly impact router functionality and performance. By emphasizing these criteria, valuable insights into the strengths and limitations of different designs are gained, facilitating informed decisions and advancements in optical networking. While other factors contribute to performance and efficiency, the chosen criteria consistently address fundamental elements, enabling meaningful evaluation. This work serves as a valuable resource for beginners, providing a solid foundation in understanding ONoC and optical routers. It also offers an in-depth survey for experts, laying the groundwork for further exploration. Additionally, the importance of considering design constraints and requirements when selecting an optimal router design is highlighted. Continued research and innovation will enable the development of efficient optical router solutions that meet the evolving needs of modern computing systems. This survey underscores the significance of ongoing advancements in the field and their potential impact on future technologies.

Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

Since the invention of amorphous indium–gallium–zinc–oxide (IGZO) based thin-film transistors (TFTs) by Hideo Hosono in 2004, investigations on the topic of IGZO TFTs have been rapidly expanded thanks to their high electrical performance, large-area uniformity, and low processing temperature. This article reviews the recent progress and major trends in the field of IGZO-based TFTs. After a brief introduction of the history of IGZO and the main advantages of IGZO-based TFTs, an overview of IGZO materials and IGZO-based TFTs is given. In this part, IGZO material electron travelling orbitals and deposition methods are introduced, and the specific device structures and electrical performance are also presented. Afterwards, the recent advances of IGZO-based TFT applications are summarized, including flat panel display drivers, novel sensors, and emerging neuromorphic systems. In particular, the realization of flexible electronic systems is discussed. The last part of this review consists of the conclusions and gives an outlook over the field with a prediction for the future.