The absence of large-size gallium nitride (GaN) substrates with low dislocation density remains a primary bottleneck for advancing GaN-based devices. Here, we demonstrate the achievement of 8-inch freestanding GaN substrates grown by hydride vapor phase epitaxy. Critical to this achievement is the improvement in gas-flow uniformity, which ensures exceptional thickness homogeneity and enables the crack-free growth of GaN. After laser lift-off (LLO) separation, the freestanding GaN substrate exhibits superior crystal quality, evidenced by full width at half maximum values of 68 and 54 arcsec for X-ray diffraction rocking curves of (002) and (102) planes, alongside a low dislocation density of 1.6 × 10⁶ cm⁻². This approach establishes a robust pathway for the production of large-size GaN substrates, which are essential for advancing next-generation power electronics and high-efficiency photonics.

Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

The kinetics process and control process of chemical mechanical high precision finishing for material surfaces were studied. According to the experiments, the seven kinetics process for chemical mechanical polishing (CMP)was generalized.Through investigating the CMP process of ULSI silicon substrate，we found that the chemical process was the CMP control process under the same mechanical action condition, which was determined by emperature. The key factor influencing the chemical reactions was effectively settled, which will be advantageous for ireproving the CMP removal rate for other materials.

As a type of charge-balanced power device, the performance of super-junction MOSFETs (SJ-MOS) is significantly influenced by fluctuations in the fabrication process. To overcome the relatively narrow process window of conventional SJ-MOS, an optimized structure "vertical variable doping super-junction MOSFET (VVD-SJ)" is proposed. Based on the analysis using the charge superposition principle, it is observed that the VVD-SJ, in which the impurity concentration of the P-pillar gradually decreases while that of the N-pillar increases from top to bottom, improves the electric field distribution and mitigates charge imbalance (CIB). Experimental results demonstrate that the optimized 600 V VVD-SJ achieves a 35.90% expansion of the process window.

Halide perovskites have attracted great interest as active layers in optoelectronic devices. Among perovskites with diverse compositions, α-FAPbI₃ is of utmost importance with great optoelectronic properties and a decent bandgap of 1.48 eV. However, the α-phase suffers an irreversible transition to the photo-inactive δ-phase, whereas the δ-phase is usually regarded as useless phase with poor optoelectronic properties. Therefore, it is commonly accepted that the thermodynamic stable δ-FAPbI₃ greatly limits the application of FAPbI₃. Every coin has two sides, although the δ-phase is difficult to apply as photoelectrical active layers, it is possible to combine δ-FAPbI₃ with α-FAPbI₃ to realize functional applications. Firstly, this review analyzes the cause of the contrasting properties between α- and δ-FAPbI₃, where the stronger electron−phonon coupling in 1D hexagonal δ-FAPbI₃ restricts its internal carrier and phonon transport. Secondly, the factors affecting the phase transitions and strategies to control phase transition between α- and δ-FAPbI₃ are presented. Finally, some functional applications of δ-FAPbI₃ in combination with α-FAPbI₃ are given according to previous reports. By and large, we hope to introduce δ-FAPbI₃ from another perspective and give some insights into its unique properties, hopefully providing new strategies for the subsequent advances to FAPbI₃.

The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control circuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-, double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Meanwhile, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.

This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices. Owing to the 3D wrapped gate structure, MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region. As the Si CMOS technology pioneers to sub-10 nm nodes, the process challenges in terms of lithography capability, process integration controversies, performance variability etc. were also discussed in this work. Due to the severe self-heating effect in the MuGFETs, the ballistic transport and reliability characteristics were investigated. Future alternatives for the current Si MuGFET technology were discussed at the end of the paper. More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.