Currently, the global 5G network, cloud computing, and data center industries are experiencing rapid development. The continuous growth of data center traffic has driven the vigorous progress in high-speed optical transceivers for optical interconnection within data centers. The electro-absorption modulated laser (EML), which is widely used in optical fiber communications, data centers, and high-speed data transmission systems, represents a high-performance photoelectric conversion device. Compared to traditional directly modulated lasers (DMLs), EMLs demonstrate lower frequency chirp and higher modulation bandwidth, enabling support for higher data rates and longer transmission distances. This article introduces the composition, working principles, manufacturing processes, and applications of EMLs. It reviews the progress on advanced indium phosphide (InP)-based EML devices from research institutions worldwide, while summarizing and comparing data transmission rates and key technical approaches across various studies.

Two essential blocks for the PLLs based on CP, a phase-frequency detector (PFD) and an improved current steering charge-pump (CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354 ° to 354 ° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

Analog in-memory computing (AIMC) has attracted significant attention as an energy-efficient computing paradigm for data-intensive workloads. However, its practical deployment is fundamentally limited by various non-idealities across multiple abstraction levels, which degrade computational accuracy and reliability. This paper presents a comprehensive review of non-idealities in AIMC systems from a cross-layer perspective. A common computational representation is introduced to illustrate how diverse physical non-idealities may manifest as weight perturbations, multiplicative distortions, nonlinear transfer effects, additive errors, and quantization or accumulation errors. From this perspective, we review design techniques across device, array, circuit, data-conversion, and system levels, and discuss how errors are generated, transformed, and accumulated throughout the computation flow. Furthermore, algorithm-hardware co-design strategies are discussed as an effective approach to mitigate cross-layer errors and enhance system robustness. By providing a structured overview of error generation, transformation, and propagation, this work highlights the importance of cross-layer co-design and offers insights into the design trade-offs among accuracy, efficiency, and scalability in AIMC systems.

With rapid advancement and deep integration of artificial intelligence and the internet-of-things, artificial intelligence of things has emerged as a promising technology changing people’s daily life. Massive growth of data generated from the devices challenges the AIoT systems from information collection, storage, processing and communication. In the review, we introduce volatile threshold switching memristors, which can be roughly classified into three types: metallic conductive filament-based TS devices, amorphous chalcogenide-based ovonic threshold switching devices, and metal-insulator transition based TS devices. They play important roles in high-density storage, energy efficient computing and hardware security for AIoT systems. Firstly, a brief introduction is exhibited to describe the categories (materials and characteristics) of volatile TS devices. And then, switching mechanisms of the three types of TS devices are discussed and systematically summarized. After that, attention is focused on the applications in 3D cross-point memory technology with high storage-density, efficient neuromorphic computing, hardware security (true random number generators and physical unclonable functions), and others (steep subthreshold slope transistor, logic devices, etc.). Finally, the major challenges and future outlook of volatile threshold switching memristors are presented.

This paper describes a large tuning range low phase noise voltage-controlled ring oscillator (ring VCO) based on a different cascade voltage logic delay cell with current-source load to change the current of output node. The method for optimization is presented. Furthermore, the analysis of performance of the proposed ring VCO is confirmed by the measurement results. The three-stage proposed ring VCO was fabricated in the 180-nm CMOS process of SMIC. The measurement results show that the oscillator frequency of the ring VCO is from 0.770 to 5.286 GHz and the phase noise is 97.93 dBc/Hz at an offset of 1 MHz from 5.268 GHz with a total power of 15.1 mW from a 1.8 V supply while occupying only 0.00175 mm² of the core die area.

In DSP-based SerDes application, it is essential for AFE to implement a pre-ADC equalization to provide a better signal for ADC and DSP. To meet the various equalization requirements of different channel and transmitter configurations, this paper presents a 112 Gbps DSP-Based PAM4 SerDes receiver with a wide band equalization tuning AFE. The AFE is realized by implementing source degeneration transconductance, feedforward high-pass branch and inductive feedback peaking TIA. The AFE offers a flexible equalization gain tuning of up to 17.5 dB at Nyquist frequency without affecting the DC gain. With the proposed AFE, the receiver demonstrates eye opening after digital FIR equalization and achieves 6 × 10⁻⁹ BER with a 29.6 dB insertion loss channel.