The formation of an electric dipole at the high-k/SiO₂ interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO₂ interface are explained by the dielectric contact induced gap states (DCIGS). The charge neutrality level (CNL) of the DCIGS, which represents a distribution of high-k and SiO₂ contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO₂ is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO₂ systems based on this model are in good agreement with the experimental data.

The characteristics of TDDB (time-dependent dielectric breakdown) and SILC (stress-induced leakage current) for an ultra-thin SiO₂/HfO₂ gate dielectric stack are studied. The EOT (equivalent-oxide-thickness) of the gate stack (Si/SiO₂/HfO₂/TiN/TiAl/TiN/W) is 0.91 nm. The field acceleration factor (γ) extracted in TDDB experiments is 1.59 s·cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the breakdown behavior. The trap energy levels can be calculated by the SILC peaks:one SILC peak is most likely to be caused by the neutral oxygen vacancy (V_O) in the HfO₂ bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Furthermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.

Currently, the global 5G network, cloud computing, and data center industries are experiencing rapid development. The continuous growth of data center traffic has driven the vigorous progress in high-speed optical transceivers for optical interconnection within data centers. The electro-absorption modulated laser (EML), which is widely used in optical fiber communications, data centers, and high-speed data transmission systems, represents a high-performance photoelectric conversion device. Compared to traditional directly modulated lasers (DMLs), EMLs demonstrate lower frequency chirp and higher modulation bandwidth, enabling support for higher data rates and longer transmission distances. This article introduces the composition, working principles, manufacturing processes, and applications of EMLs. It reviews the progress on advanced indium phosphide (InP)-based EML devices from research institutions worldwide, while summarizing and comparing data transmission rates and key technical approaches across various studies.

In this paper, a high-gain inductorless LNA (low-noise amplifier) compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed. A composite resistor−capacitor feedback structure is employed to achieve a wide bandwidth matching range and good gain flatness. A second stage with a Darlington pair is used to increase the overall gain of the amplifier, while the gain of the first stage is reduced to reduce the overall noise. The amplifier is based on a 0.25 μm SiGe BiCMOS process, and thanks to the inductorless circuit structure, the core circuit area is only 0.03 mm². Test results show that the lowest noise figure (NF) in the operating band is 1.99 dB, the power gain reaches 29.7 dB, the S₁₁ and S₂₂ are less than −10 dB, the S₁₂ is less than −30 dB, the IIP3 is 0.81dBm, and the OP_1dB is 10.27 dBm. The operating current is 31.18 mA at 3.8 V supply.

Two-dimensional (2D) bismuth, bismuthene, is an emerging pnictogen family member that has received increasing research attention in the past few years, which could yield exotic electrical, thermal, and optical properties due to unique band structure. This review provides a holistic view of recent research advances on 2D bismuth material synthesis and device applications in complementary metal oxide semiconductor (CMOS) technology. Firstly, the atomic and band structure of bismuthene is reviewed as the fundamental understanding of its physical properties. Then, it highlights material synthesis of 2D bismuth atomic sheets with emphasis on physical vapor deposition method with accurate layer controllability and process compatibility with CMOS technology. Moreover, it will survey latest applications of 2D bismuth in terms of electronic, optic, thermoelectric, spintronic and magnetic nanodevices. 2D bismuth derivatives (Bi–X, X = Sb, Te, Se) will also be mentioned as a promising strategy to further improve device performance. At last, it concludes with a brief summary on the current challenges and future prospects in 2D bismuth and its derivatives for innovative electronics, sensors and other devices compatible with CMOS techniques.

Ex situ characterization techniques in molecular beam epitaxy (MBE) have inherent limitations, such as being prone to sample contamination and unstable surfaces during sample transfer from the MBE chamber. In recent years, the need for improved accuracy and reliability in measurement has driven the increasing adoption of in situ characterization techniques. These techniques, such as reflection high-energy electron diffraction, scanning tunneling microscopy, and X-ray photoelectron spectroscopy, allow direct observation of film growth processes in real time without exposing the sample to air, hence offering insights into the growth mechanisms of epitaxial films with controlled properties. By combining multiple in situ characterization techniques with MBE, researchers can better understand film growth processes, realizing novel materials with customized properties and extensive applications. This review aims to overview the benefits and achievements of in situ characterization techniques in MBE and their applications for material science research. In addition, through further analysis of these techniques regarding their challenges and potential solutions, particularly highlighting the assistance of machine learning to correlate in situ characterization with other material information, we hope to provide a guideline for future efforts in the development of novel monitoring and control schemes for MBE growth processes with improved material properties.

Chemical mechanical polishing (CMP) serves as an indispensable process for achieving global planarization in semiconductor manufacturing, especially as integrated circuit (IC) technology advances to sub-7 nm nodes, where atomic-level surface flatness becomes crucial. Silica abrasives, which account for over 90% of the abrasive market in advanced CMP processes, operate not through simple mechanical grinding but through a key "chemical-mechanical synergistic" mechanism: chemically softening the wafer surface, then mechanically removing the softened layer to expose a new surface, which is further softened and removed, repeating this cycle to produce a smooth wafer. Despite their prevalence, conventional silica abrasives still face challenges, including relatively low material removal rate (MRR), a tendency to agglomerate, leading to poor dispersion and surface defects, and limitations in achieving ultimate surface uniformity. Significant progress has been made to address these issues. Development has progressed from simple spherical particles to complex structural designs (such as mesoporous, hollow, and raspberry-shaped structures) to enhance slurry transport and mechanical action. Surface chemical modifications (e.g., using amino or polymer groups) can improve dispersion stability and reduce scratching. Furthermore, composites with other materials (e.g., ceria, polymers) and precise control of particle size distribution are key to enhancing performance. These innovative approaches have yielded significant performance gains. State-of-the-art slurries have demonstrated the ability to achieve surface roughness below 0.1 nm RMS. The development of silica abrasives is increasingly focused on sustainability and smart manufacturing. A prominent direction is the design of biodegradable abrasives that disintegrate after use, thereby simplifying post-chemical mechanical polishing (CMP) cleanup and minimizing environmental impact—an approach fully aligned with green manufacturing principles. This review systematically summarizes the progress of silica abrasives for CMP over the past 60 years. This summary provides theoretical insights and forward-looking strategies to overcome the current limitations of abrasive technology. We believe this review will be helpful in advancing the field of CMP abrasives towards next-generation semiconductor manufacturing.

This paper demonstrates a monolithically integrated current reference and current mirror based on p-GaN gate HEMT technology, designed for high-temperature applications. The p-GaN current reference is composed of one D-mode and two E-mode devices. The generated reference current is independent of supply voltage since the proposed circuit incorporates a bias circuit capable of providing a supply-voltage-insensitive bias voltage. Moreover, under the zero-temperature coefficient (ZTC) bias voltage condition, the variation in the generated reference current at 200 °C is reduced by 15.4%, compared to a conventional p-GaN current reference with a bias voltage of 5 V. Experimental results indicate that the generated reference current slightly reduced from 2.53 to 1.70 mA over a broad temperature range of 25−200 °C. In addition, a current mirror circuit based on p-GaN HEMT technology was designed to imitate a reference current. The influence of temperature on the output current of the current mirror is mitigated, which could be realised by biasing the gate-to-source voltage at the zero-temperature coefficient voltage. This design sustains the current mirror mismatch error with small variation across a temperature range from room temperature to 200 °C. These results indicate that the GaN current reference and current mirror under zero-temperature coefficient bias voltage can ensure stable output current across different temperatures, facilitating the application of fully GaN integrated circuits in high-temperature environments.