The fabrication of a dynamic threshold-2T0C (DT-2T0C) DRAM cell incorporating a ZnO charge-trap layer in the write transistor has been successfully achieved, addressing the negative hold voltage (VHOLD) issue of conventional 2T0C DRAM cells using oxide channel layers. The proposed device facilitates dynamic modulation of turn-on voltage (VON) through an additional SET operation, allowing VON to shift above 0 V. The retention time in SET operation was extended to 104 s by optimizing the tunneling layer deposition conditions. The device characterization revealed a significant correlation between VON and both the WRITE speed and the retention properties of the DT-2T0C, verifying the trade-off between WRITE time and retention time. A long retention time over 1000 s was achieved, even under VHOLD of 0 V.
Ferroelectric hysteresis loop measurement under high driving frequency generally faces great challenges. Parasitic factors in testing circuits such as leakage current and RC delay could result in abnormal hysteresis loops with erroneous remnant polarization (Pr) and coercive field (Ec). In this study, positive-up-negative-down (PUND) measurement under a wide frequency range was performed on a 10-nm thick Hf0.5Zr0.5O2 ferroelectric film. Detailed analysis on the leakage current and RC delay was conducted as the polarization switching occurs in the FE capacitor. After considering the time lag caused by RC delay, reasonable calibration of current response over the voltage pulse stimulus was employed in the integral of polarization current over time. In such a method, rational P–V loops measured at high frequencies (>1 MHz) was successfully achieved. This work provides a comprehensive understanding on the effect of parasitic factors on the polarization switching behavior of FE films.
Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.
Fifteen periods of Si/Si0.7Ge0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si0.7Ge0.3 features the best crystal quality and no defects are observed. Stacked Si0.7Ge0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.
Since the invention of amorphous indium–gallium–zinc–oxide (IGZO) based thin-film transistors (TFTs) by Hideo Hosono in 2004, investigations on the topic of IGZO TFTs have been rapidly expanded thanks to their high electrical performance, large-area uniformity, and low processing temperature. This article reviews the recent progress and major trends in the field of IGZO-based TFTs. After a brief introduction of the history of IGZO and the main advantages of IGZO-based TFTs, an overview of IGZO materials and IGZO-based TFTs is given. In this part, IGZO material electron travelling orbitals and deposition methods are introduced, and the specific device structures and electrical performance are also presented. Afterwards, the recent advances of IGZO-based TFT applications are summarized, including flat panel display drivers, novel sensors, and emerging neuromorphic systems. In particular, the realization of flexible electronic systems is discussed. The last part of this review consists of the conclusions and gives an outlook over the field with a prediction for the future.
The finding of the robust ferroelectricity in HfO2-based thin films is fantastic from the view point of both the fundamentals and the applications. In this review article, the current research status of the future prospects for the ferroelectric HfO2-based thin films and devices are presented from fundamentals to applications. The related issues are discussed, which include: 1) The ferroelectric characteristics observed in HfO2-based films and devices associated with the factors of dopant, strain, interface, thickness, defect, fabrication condition, and more; 2) physical understanding on the observed ferroelectric behaviors by the density functional theory (DFT)-based theory calculations; 3) the characterizations of microscopic and macroscopic features by transmission electron microscopes-based and electrical properties-based techniques; 4) modeling and simulations, 5) the performance optimizations, and 6) the applications of some ferroelectric-based devices such as ferroelectric random access memory, ferroelectric-based field effect transistors, and the ferroelectric tunnel junction for the novel information processing systems.
One of the core semiconductor devices is the electrostatic chuck. It has been widely used in plasma-based and vacuum-based semiconductor processing. The electrostatic chuck plays an important role in adsorbing and cooling/heating wafers, and has technical advantages on non-edge exclusion, high reliability, wafer planarity, particles reduction and so on. This article extracts key design elements from the existing knowledge and techniques of electrostatic chuck by the method proposed by Paul and Beitz, and establishes a design space systematically. The design space is composed of working objects, working principles and working structures. The working objects involve electrostatic chuck components and materials, classifications, and relevant properties; the working principles involve clamping force, residual force, and temperature control; the working structures describe how to compose an electrostatic chuck and to fulfill the overall functions. The systematic design space exhibits the main issues during electrostatic chuck design. The design space will facilitate and inspire designers to improve the design quality and shorten the design time in the conceptual design.
Memristors are now becoming a prominent candidate to serve as the building blocks of non-von Neumann in-memory computing architectures. By mapping analog numerical matrices into memristor crossbar arrays, efficient multiply accumulate operations can be performed in a massively parallel fashion using the physics mechanisms of Ohm’s law and Kirchhoff’s law. In this brief review, we present the recent progress in two niche applications: neural network accelerators and numerical computing units, mainly focusing on the advances in hardware demonstrations. The former one is regarded as soft computing since it can tolerant some degree of the device and array imperfections. The acceleration of multiple layer perceptrons, convolutional neural networks, generative adversarial networks, and long short-term memory neural networks are described. The latter one is hard computing because the solving of numerical problems requires high-precision devices. Several breakthroughs in memristive equation solvers with improved computation accuracies are highlighted. Besides, other nonvolatile devices with the capability of analog computing are also briefly introduced. Finally, we conclude the review with discussions on the challenges and opportunities for future research toward realizing memristive analog computing machines.
In DSP-based SerDes application, it is essential for AFE to implement a pre-ADC equalization to provide a better signal for ADC and DSP. To meet the various equalization requirements of different channel and transmitter configurations, this paper presents a 112 Gbps DSP-Based PAM4 SerDes receiver with a wide band equalization tuning AFE. The AFE is realized by implementing source degeneration transconductance, feedforward high-pass branch and inductive feedback peaking TIA. The AFE offers a flexible equalization gain tuning of up to 17.5 dB at Nyquist frequency without affecting the DC gain. With the proposed AFE, the receiver demonstrates eye opening after digital FIR equalization and achieves 6 × 10−9 BER with a 29.6 dB insertion loss channel.
This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm2.
