This work fabricates a vertical channel-all-around indium−gallium−zinc-oxide field-effect transistor(CAA IGZO FET) through reasonable etching process and annealing optimization. The resulting device exhibits has a normalized on-current (I_ON) of 87.1 μA/μm, and a subthreshold swing (SS) of approximately 66.98 mV/Dec. These performance parameters are twice as good as similar work obtained in previous experiments, which is sufficient to meet the requirements for manufacturing 2T0C DRAM units. Moreover, with the double-layer stacking of this structure, the feasibility and scalability of manufacturing DRAM units with CAA IGZO FET is verified.

Currently, the global 5G network, cloud computing, and data center industries are experiencing rapid development. The continuous growth of data center traffic has driven the vigorous progress in high-speed optical transceivers for optical interconnection within data centers. The electro-absorption modulated laser (EML), which is widely used in optical fiber communications, data centers, and high-speed data transmission systems, represents a high-performance photoelectric conversion device. Compared to traditional directly modulated lasers (DMLs), EMLs demonstrate lower frequency chirp and higher modulation bandwidth, enabling support for higher data rates and longer transmission distances. This article introduces the composition, working principles, manufacturing processes, and applications of EMLs. It reviews the progress on advanced indium phosphide (InP)-based EML devices from research institutions worldwide, while summarizing and comparing data transmission rates and key technical approaches across various studies.

In DSP-based SerDes application, it is essential for AFE to implement a pre-ADC equalization to provide a better signal for ADC and DSP. To meet the various equalization requirements of different channel and transmitter configurations, this paper presents a 112 Gbps DSP-Based PAM4 SerDes receiver with a wide band equalization tuning AFE. The AFE is realized by implementing source degeneration transconductance, feedforward high-pass branch and inductive feedback peaking TIA. The AFE offers a flexible equalization gain tuning of up to 17.5 dB at Nyquist frequency without affecting the DC gain. With the proposed AFE, the receiver demonstrates eye opening after digital FIR equalization and achieves 6 × 10⁻⁹ BER with a 29.6 dB insertion loss channel.

Analog in-memory computing (AIMC) has attracted significant attention as an energy-efficient computing paradigm for data-intensive workloads. However, its practical deployment is fundamentally limited by various non-idealities across multiple abstraction levels, which degrade computational accuracy and reliability. This paper presents a comprehensive review of non-idealities in AIMC systems from a cross-layer perspective. A common computational representation is introduced to illustrate how diverse physical non-idealities may manifest as weight perturbations, multiplicative distortions, nonlinear transfer effects, additive errors, and quantization or accumulation errors. From this perspective, we review design techniques across device, array, circuit, data-conversion, and system levels, and discuss how errors are generated, transformed, and accumulated throughout the computation flow. Furthermore, algorithm-hardware co-design strategies are discussed as an effective approach to mitigate cross-layer errors and enhance system robustness. By providing a structured overview of error generation, transformation, and propagation, this work highlights the importance of cross-layer co-design and offers insights into the design trade-offs among accuracy, efficiency, and scalability in AIMC systems.

Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

The computational cost of TCAD simulations is becoming prohibitively high with the complexity of advanced process technologies, making simulation acceleration a critical research priority. While end-to-end surrogate models mapping process recipes to device structures and characteristics offer a promising alternative, their application is often limited by poor generalizability and explainability. In this work, we present MPNet, a modular deep learning surrogate modeling framework for process TCAD. MPNet comprises distinct surrogate models for individual process modules, which are assembled into an integrated framework. These modular models employ a novel UNet-attention feature evolution method to capture the complex evolutions of device geometry and doping profiles. Each module can be trained separately on its individual process, after which the modules are cascaded and jointly fine-tuned to minimize error accumulation throughout the cascade. The efficacy of the proposed MPNet framework is demonstrated through a MOSFET integrated process TCAD case study. Results show that MPNet achieves a computational speedup of over 10³ times compared to conventional TCAD, while maintaining predictive fidelity exceeding 98%. Finally, to illustrated the application of the proposed framework, MPNet is coupled with a PSO algorithm, showcasing its utility for fast process optimization to meet specific process targets.