Er-doped silicon-rich silicon nitride (SRN) films were deposited on silicon substrate by an RF magnetron reaction sputtering system. After high temperature annealing, the films show intense photoluminescence in both the visible and infrared regions. Besides broad-band luminescence centered at 780 nm which originates from silicon nanocrystals, resolved peaks due to transitions from all high energy levels up to 2H11/2 to the ground state of Er3+ are observed. Raman spectra and HRTEM measurements have been performed to investigate the structure of the films, and possible excitation processes are discussed.

Ferromagnetism in undoped and cobalt-doped high-k HfO2 films was investigated. No ferromagnetism was observed in stoichiometric HfO2 films, but we observed weak ferromagnetism in highly oxygen-deficient HfO2 films. Undoped and cobalt doped films were treated by alternate annealing in vacuum and oxygen atmospheres. From the experiments, both the lack of oxygen vacancies and the increase of oxygen species in bulk (e.g. interstitial oxygen) will degrade the magnetic ordering. Additionally, it is believed that cobalt doping has no obvious relationship with the observed intrinsic d0 magnetism.

The influence of annealed ohmic contact metals on the electron mobility of a two dimensional electron gas (2DEG) is investigated on ungated AlGaN/GaN heterostructures and AlGaN/GaN heterostructure field effect transistors (AlGaN/GaN HFETs). Current–voltage (I–V) characteristics for ungated AlGaN/GaN heterostructures and capacitance–voltage (C–V) characteristics for AlGaN/GaN HFETs are obtained, and the electron mobility for the ungated AlGaN/GaN heterostructure is calculated. It is found that the electron mobility of the 2DEG for the ungated AlGaN/GaN heterostructure is decreased by more than 50% compared with the electron mobility of Hall measurements. We propose that defects are introduced into the AlGaN barrier layer and the strain of the AlGaN barrier layer is changed during the annealing process of the source and drain, causing the decrease in the electron mobility.

A high temperature AlN template was grown on sapphire substrate by metalorganic chemical vapor deposition. AFM results showed that the root mean square of the surface roughness was just 0.11 nm. Optical transmission spectrum and high resolution X-ray diffraction (XRD) characterization both proved the high quality of the AlN template. The XRD (002) rocking curve full width at half maximum (FWHM) was about 53.7 arcsec and (102) FWHM was about 625 arcsec. The densities of screw threading dislocations (TDs) and edge TDs were estimated to be ～ 6 E6 cm-2 and ～ 4.7E9 cm-2. AlGaN of Al composition 80.2% was further grown on the AlN template. The RMS of the surface roughness was about 0.51 nm. XRD reciprocal space mapping was carried out to accurately determine the Al composition and relaxation status in the AlGaN epilayer. The XRD (002) rocking curve FWHM of the AlGaN epilayer was about 140 arcsec and (102) FWHM was about 537 arcsec. The density of screw TDs was estimated to be ～4E7 cm-2 and that of edge TDs was ～3.3E9 cm-2. These values all prove the high quality of the AlN template and AlGaN epilayer.

Based on the physical vapor transport (PVT) method, the growth of large-size CdS crystals inside a vertical semi-closed tube is studied. Firstly, in order to ensure 1D diffusion-advection transport, multi-thin tubes are used in the growth tube. The XRD spectra of the CdS crystal grown in this configuration indicates that the crystal quality has clearly been improved, where the FWHM is 58.5 arcsec. Secondly, theoretical and experimental growth rates under different total pressures are compared; the results show that the experiential growth rate equation is valid for our semi-tube growth, and it could be used to estimate the growth rate and maximum growth time under different total pressures.

A series of high dielectric material Er2O3 thin films with different thicknesses were deposited on p-type Si (100) substrate by pulse laser deposition at different temperatures. Phase structures of the films were determined by means of X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM). Leakage current density was measured with an HP4142B semiconductor parameter analyzer. The XRD and HRTEM results reveal that Er2O3 thin films deposited below 400 ℃ are amorphous, while films deposited from 400 to 840 ℃ are well crystallized with (111)-preferential crystallographic orientation. I–V curves show that, for ultrathin crystalline Er2O3 films, the leakage current density increases by almost one order of magnitude from 6.20E-5 to 6.56 E-4 A/cm2, when the film thickness decreases by only 1.9 nm from 5.7 to 3.8 nm. However the leakage current density of ultrathin amorphous Er2O3 films with a thickness of 3.8 nm is only 1.73E-5 A/cm2. Finally, analysis of leakage current density showed that leakage of ultrathin Er2O3 films at high field is mainly caused by Fowler–Nordheim tunneling, and the large leakage of ultrathin crystalline Er2O3 films could arise from impurity defects at the grain boundary.

Abstract: Hole mobility changes under uniaxial and combinational stress in different directions are characterized and analyzed by applying additive mechanical uniaxial stress to bulk Si and SiGe-virtual-substrate-induced strained-Si (s-Si) p-MOSFETs (metal-oxide-semiconductor field-effect transistors) along <110> and <110> channel directions. In bulk Si, a mobility enhancement peak is found under uniaxial compressive strain in the low vertical field. The combination of <110> direction uniaxial tensile strain and substrate-induced biaxial tensile strain provides a higher mobility relative to the <110> direction, opposite to the situation in bulk Si. But the combinational strain experiences a gain loss at high field, which means that uniaxial compressive strain may still be a better choice. The mobility enhancement of SiGe-induced strained p-MOSFETs along the <110> direction under additive uniaxial tension is explained by the competition between biaxial and shear stress.

MOS capacitors with hafnium oxynitride (HfON) gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method. A large amount of fixed charges and interface traps exist at the Ge/HfON interface. HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing. A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier. Using this method, well behaved capacitance–voltage and current–voltage characteristics were obtained. Finally hystereses are compared under different process conditions and possible causes are discussed.

A novel structure for designing and fabricating a power static induction transistor (SIT) with excellent high breakdown voltage performance is presented. The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance, and to avoid the parallel-current effect in particular. Three ring-shape junctions (RSJ) are arranged around the gate junction to reduce the electric field intensity. It is important to achieve maximum gate–source breakdown voltage BVGS, gate–drain breakdown voltage BVGD and blocking voltage for high power application. A number of technological methods to increase BVGD and BVGS are presented. The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V, and the performance of the power SIT has been greatly improved. The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.

The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators. The total heat and lattice temperature distributions along the Si–SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail. The influence of structure parameters on peak lattice temperature is also discussed, which is useful for designers to optimize the parameters of LDMSO for better ESD performance.

A measuring technique based on the CP (charge pumping) method for hot-carrier degradation measurement of high voltage N-LDMOS is researched in depth. The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail. At the same time, the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed. The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.

A terminating type MEMS microwave power sensor based on the Seebeck effect and compatible with the GaAs MMIC process is presented. An electrothermal model is introduced to simulate the thermal time constant. An analytical result, about 160 ms, of the thermal time constant from the non-stationary Fourier heat equations for the structure of the sensor is also given. The sensor measures the microwave power jumping from 15 to 20 dBm at a constant frequency 15 GHz, and the experimental thermal time constant result is 180 ms. The frequency is also changed from 20 to 10 GHz with a constant power 20 dBm, and the result is also 180 ms. Compared with the analytical and experimental results, the model is verified.

A novel shielding scheme is developed by inserting a concave shield between a metal–insulator–metal (MIM) capacitor and the silicon substrate. Chip measurements reveal that the concave shield improves the quality factor by 11% at 11.8 GHz and 14% at 18.8 GHz compared with an unshielded MIM capacitor. It also alleviates the effect on shunt capacitance between the bottom plate of the MIM capacitor and the shield layer. Moreover, because the concave shields simplify substrate modeling, a simple circuit model of the MIM capacitor with concave shield is presented for radio frequency applications.

According to Lambert’s law, a novel structure of photodetectors, namely photodetectors in silicon-on-insulator, is proposed. By choosing a certain thickness value for the SOI layer, the photodetector can absorb blue/violet light effectively and affect the responsivity of the long wavelength in the visible and near-infrared region, making a blue/violet filter unnecessary. The material of the SOI layer is high-resistivity floating-zone silicon which can cause the neutral N type SOI layer to become fully depleted after doping with a P type impurity. This can improve the collection efficiency of short-wavelength photogenerated carriers. The device structure was optimized through numerical simulation, and the results show that the photodiode is a kind of high performance photodetector in the blue/violet region.

This paper presents a new CMOS LC-VCO with a 2.95–3.65 GHz tuning range. The large tuning range is achieved by tuning curve compensation using a novel varactor configuration, which is mainly composed of four accumulation-mode MOS varactors (A-MOS) and two bias voltages. The proposed varactor has the advantages of optimizing quality factor and tuning range simultaneously, linearizing the effective capacitance and thus greatly reducing the amplitude-to-phase modulation (AM-PM) conversion. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Measured phase noise is lower than –91 dBc at 100 kHz offset from a 3.15 GHz carrier while measured tuning range is 21.5% as the control voltage varies from 0 to 1.8 V. The VCO including buffers consumes 2.8 mA current from a 1.8 V supply.

Nucleation layer formation is a key factor for high quality gallium nitride (GaN) growth on a sapphire substrate. We found that the growth rate substantially affected the nucleation layer morphology, thereby having a great impact on the crystal quality, surface morphology and electrical properties of AlGaN/GaN heterostructures on sapphire substrates. A nucleation layer with a low growth rate of 2.5 nm/min is larger and has better coalescence than one grown at a high growth rate of 5 nm/min. AlGaN/GaN heterostructures on a nucleation layer with low growth rate have better crystal quality, surface morphology and electrical properties.

This paper shows the design of a second-order multi-bit △Σ modulator with hybrid structure for ADSL applications. A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12% of the time from PH1, which relaxes the speed of OTAs, comparators and the DEMblock. The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder. The chip is designed and fabricated in UMC 0.18 μm CMOS technology. Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz, the modulator can achieve 79 dB dynamic range, 71.3 dB SNDR, 11 mW power consumption from a 1.8 V power supply. The FOM is 1.47 pJ/step.

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18 μm CMOS process. This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz. A fully differential OTA with source degeneration is used to provide sufficient linearity. Furthermore, a ring CCO based frequency tuning scheme is proposed to reduce frequency variation. The measured results show that in narrow-band mode the image rejection ratio (IMRR) is 35 dB, the filter dissipates 0.8 mA from the 1.8 V power supply, and the out-of-band rejection is 50 dB at 6 MHz offset. In wide-band mode, IMRR is 28 dB and the filter dissipates 3.2 mA. The frequency tuning error is less than ±2%.

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 Ω, and the average input noise current spectral density is 9.7 pA/√Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

A high-speed SiGe BiCMOS direct digital frequency synthesizer (DDS) is presented. The design integrates a high-speed digital DDS core, a high-speed differential current-steering mode 10-bit D/A converter, a serial/parallel interface, and clock control logic. The DDS design is processed in 0.35 μm SiGe BiCMOS standard process technology and worked at 1 GHz system frequency. The measured results show that the DDS is capable of generating a frequency-agile analog output sine wave up to 400+ MHz.

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter. Design details and measurement results for the whole chip are presented for a TSMC 0.18 μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz. The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz, the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB, a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz. The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1 × 2 mm2.

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fabricated based on the ϕ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simulation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm2 . The whole chip has an area of 1511 × 666 μm2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950 × 1910 μm2 and the measured results demonstrate an input dynamic range of 34 dB (10–500 mVpp) with constant output swing of 500 mVpp.

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic integrated receiver based on a metal–semiconductor–metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photogenerated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM photodetector’s low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to –3 dB frequency.

This paper proposes an area-saving dual-path loop filter (LPF) for low-voltage integrated phase-locked loops (PLLs). With this LPF, output current of the lowpass-path charge-pump (CP) is B times (B > 1) as great as that of the integration-path CP. By adding voltages across these two paths, the zero-capacitance is magnified B times equivalently. As a result, the chip size is greatly reduced. Based on this LPF, a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18 μm RFCMOS technology. Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that, at a frequency of 3.20 GHz, phase noise is –120.2 dBc/Hz at 1 MHz offset, reference spur is –72 dBc, and power is 24 mW.

To meet the demands for a number of LEDs, a novel charge pump circuit with current mode control is proposed. Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier. In the steady state, the input current from power voltage retains constant, so reducing the noise induced on the input voltage source and improving the output voltage ripple. The charge pump small-signal model is used to describe the device’s dynamic behavior and stability. Analytical predictions were verified by Hspice simulation and testing. Load driving is up to 800 mA with a power voltage of 3.6 V, and the output voltage ripple is less than 45 mV. The output response time is less than 8 s, and the load current jumps from 400 to 800 mA.

A fully-differential charge pump (FDCP) with perfect current matching and low output current noise is realized for phase-locked loops (PLLs). An easily stable common-mode feedback (CMFB) circuit which can handle high input voltage swing is proposed. Current mismatch and current noise contribution from the CMFB circuit is minimized. In order to optimize PLL phase noise, the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle. The calculation result agrees well with the simulation. Based on the noise analysis, many methods to lower output current noise of the FDCP are discussed. The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18 μm process. The measured output reference spur is –64 dBc to –69 dBc. The in-band and out-band phase noise is –95 dBc/Hz at 3 kHz frequency offset and –123 dBc/Hz at 1 MHz frequency offset respectively.

A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of –99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

The post-silicide of dopant segregation process for adjusting NiSi/n-Si SBH (Schottky barrier height) is described. Adopting the analysis of the I–V characteristic curve and extrapolating the SBH of NiSi/n-Si Schottky junction diodes (NiSi/n-Si SJDs), the effects of different of process parameters dopant segregation, including segregation anneal temperature and dopant implant dose, on the properties of the NiSi/n-Si SJDs have been studied, and the corresponding mechanisms are discussed.

Inverse lithography technology (ILT), a promising resolution enhancement technology (RET) used in next generations of IC manufacture, has the capability to push lithography to its limit. However, the existing methods of ILT are either time-consuming due to the large layout in a single process, or not accurate enough due to simply block merging in the parallel process. The seamless-merging-oriented parallel ILT method proposed in this paper is fast because of the parallel process; and most importantly, convergence enhancement penalty terms (CEPT) introduced in the parallel ILT optimization process take the environment into consideration as well as environmental change through target updating. This method increases the similarity of the overlapped area between guard-bands and work units, makes the merging process approach seamless and hence reduces hot-spots. The experimental results show that seamless-merging-oriented parallel ILT not only accelerates the optimization process, but also significantly improves the quality of ILT.

A new wafer-level 3D packaging structure with Benzocyclobutene (BCB) as interlayer dielectrics (ILDs) for multichip module fabrication is proposed for application in the Ku-band wave. The packaging structure consists of two layers of BCB films and three layers of metallized films, in which the monolithic microwave IC (MMIC), thin film resistors, striplines and microstrip lines are integrated. Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components. BCB layers cover the components and serve as ILDs for interconnections. Gold bumps are used as electric interconnections between different layers, which eliminates the need to prepare vias by costly dry etching and deposition processes. In order to get high-quality BCB films for the subsequent chemical mechanical planarization (CMP) and multilayer metallization processes, the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm. The thermal, mechanical and electrical properties of the packaging structure are investigated. The thermal resistance can be controlled below 2 ℃/W. The average shear strength of the gold bumps on the BCB surface is around 70 N/mm2. The performances of MMIC and interconnection structure at high frequencies are optimized and tested. The S-parameters curves of the packaged MMIC shift slightly showing perfect transmission character. The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than –8 dB from 10 to 15 GHz.