Calculations were performed on the band edge levels of (111)-biaxially strained Si on relaxed Si1-xGex alloy using the k·p perturbationmethod coupled with deformation potential theory. The results show that the conduction band (CB) edge is characterized by six identicalvalleys, that the valence band (VB) edge degeneracies are partially lifted, and that both the CB and VB edge levels move up in electron energy as the Ge fraction (x) increases. In addition, the dependence of the indirect bandgap and the VB edge splitting energy on x was obtained. Quantitative data from the results supply valuable references for Si-based strained device design.

Based on the Lindemann melting model, a model related to gold nanoparticle size and melting temperature for VLS grown silicon nanowire is proposed. Eutectic temperatures of Au–Si with different gold sizes have been calculated using the model and are in agreement with the experimental results. This model has been demonstrated to be reasonable, and it can be used to determine the growth temperature of silicon nanowire.

This paper mainly describes fabrication of two-dimensional GaAs-based photonic crystals with low nanometer scale air-hole arrays using an inductively coupled plasma (ICP) etching system. The sidewall profile and surface characteristics of the photonic crystals are systematically investigated as a function of process parameters including ICP power, RF power and pressure. Various ICP powers have no significant effect on the verticality of air-hole sidewall and surface smoothness. In contrast, RF power and chamber pressure play a remarkable role in improving sidewall verticality and surface characteristics of photonic crystals indicating different etching mechanisms for low nanometer scale photonic crystals. The desired photonic crystals have been achieved with hole diameters as low as 130 nm with smooth and vertical profiles by developing a suitable ICP processes. The influence of the ICP parameters on this device system are analyzed mainly by scanning electron microscopy. This fabrication approach is not limited to GaAs material, and may be efficiently applied to the development of most two-dimensional photonic crystal slabs.

The electronic structure of the heterojunction is the foundation of the study on its working mechanism. Models of the heterojunctions formed by an (8, 0) boron nitride nanotube and an (8, 0) carbon nanotube with C–B or C–N interface have been established. The structures of the above heterojunctions were optimized with first-principle calculations based on density functional theory. The rearrangements of the heterojunctions concentrate mainly on their interfaces. The highest occupied molecular orbital and the lowest unoccupied molecular orbital of the heterojunctions distribute in the carbon nanotube section. As the band offsets of the above heterojunctions are achieved with the average bond energy method, the band structure is plotted.

To suppress the extension of the photo-sensitive area of a planar-type InGaAs detector, the structure of the detector was modified, and the small-diffusion-area diffusion method, circle-type covering contact and guard-ring were introduced. The laser-beam-induced-current (LBIC) technique was used to study the photo responsive characteristics of the photo-sensitive area of different detector structures. It was indicated that, by modifying the size of the diffusion area, the width of the circle-type covering contact, the distance between the guard-ring and the photo-sensitive area and the working status of the guard-ring, extension of the photo-sensitive area could be effectively suppressed, and the detector photo-sensitive area could be exactly defined.

The large signal RF power transmission characteristics of an advanced InGaP HBT in an RF power amplifier are investigated and analyzed experimentally. The realistic RF powers reflected by the transistor, transmitted from the transistor and reflected by the load are investigated at small signal and large signal levels. The RF power multiple frequency components at the input and output ports are investigated at small signal and large signal levels, including their effects on RF power gain compression and nonlinearity. The results showthat the RF power reflections are different between the output and input ports. At the input port the reflected power is not always proportional to input power level; at large power levels the reflected power becomes more serious than that at small signal levels, and there is a knee point at large power levels. The results also showthe effects of the powermultiple frequency components on RF amplification.

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.

The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power transistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

With Shockley's approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier (OPA) was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz1/2, and current noise of less than 0.05 pA/Hz1/2.

A novel method for fabricating an athermal AWG is proposed, using a unique apparatus for ITU-T center wavelength adjustment and optical coupling of two cut-parts. UV adhesive or sticky gel is applied into the gap between the cut-elements and the alignment base substrate by capillary infiltration. The spectrum profiles are almost the same as those of the original chip state, and no deterioration is observed resulting from athermalization. Flat-top athermal AWG modules of 100 GHz×40 ch are fabricated. Over a temperature range of -40 to 85 ℃, the center wavelength shift is ±22 pm, and the insertion loss change is less than ±0.11 dB.

By theoretical simulation of two grid patterns that are often used in concentrator solar cells, we give a detailed and comprehensive analysis of the influence of the metal grid dimension and various losses directly associated with it during optimization of grid design. Furthermore, we also perform the simulation under different concentrator factors, making the optimization of the front contact grid for solar cells complete.

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of –94 dBc/Hz and –114.4 dBc/Hz at frequency offsets of 10 kHz and 1MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of –63 dB with the second order passive low pass filter.

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

An X-band four-way combined GaN solid-state power amplifier module is fabricated based on a self-developed AlGaN/GaN HEMT with 2.5-mm gate width technology on SiC substrate. The module consists of an AlGaN/GaN HEMT,Wilkinson power hybrids, a DC-bias circuit and microstrip matching circuits. For the stability of the amplifier module, special RC networks at the input and output, a resistor between the DC power supply and a transistor gate at the input and 3/4 Wilkinson power hybrids are used for the cancellation of low frequency self-oscillation and crosstalk of each amplifier. Under Vds = 27 V，Vgs = -4.0V, CW operating conditions at 8 GHz, the amplifier module exhibits a line gain of 5 dB with a power added efficiency of 17.9%, and an output power of 42.93 dBm; the power gain compression is 2 dB. For a four-way combined solid-state amplifier, the power combining efficiency is 67.5%. It is concluded that the reduction in combining efficiency results from the non-identical GaN HMET, the loss of the hybrid coupler and the circuit fabricating errors of each one-way amplifier.

This paper presents a 2.4 GHz power amplifier (PA) designed and implemented in 0.35 m SiGe BiCMOS technology. Instead of chip grounding through PCB vias, a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB, improving the stability and the gain of the circuit. In addition, a low-pass network for output matching is designed to improve the linearity and power capability. At 2.4 GHz, a P1dB of 15.7 dBm has been measured, and the small signal gain is 27.6 dB with S11 < -7 dB, and S22 < -15 dB.

This investigation explores a low-noise amplifier (LNA) with a coplanar waveguide (CPW) structure, in which a two-stage amplifier is associated with a cascade schematic circuit, implemented in 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) technology in a Ka-band (26.5–40.0 GHz) microwave monolithic integrated circuit (MMIC). The experimental results demonstrate that the proposed LNA has a peak gain of 12.53 dB at 30 GHz and a minimum noise figure of 3.3 dB at 29.5 GHz, when biased at a Vds of 2 V and a Vgs of –0.6 V with a drain current of 16 mA in the circuit. The results show that the millimeter-wave LNA with coplanar waveguide structure has a higher gain and wider bandwidth than a conventional circuit. Finally, the overall LNA characterization exhibits high gain and low noise, indicating that the LNA has a compact circuit and favorable RF characteristics. The strong RF character exhibited by the LNA circuit can be used in millimeter-wave circuit applications.

A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220×320 μm2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0–60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.

The quantization noise leakage of the first stage in a MASH21 sigma–delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion. The relationship between DC gain and leakage is modeled and conclusions on design criteria are reached. As an example, a MASH21 modulator for a digital audio application is realized. This modulator, fabricated in an 0.18 μm mixed signal process, achieves an SNDR of 91 dB with 1.8 V supply, which verifies the analysis and design criteria.

Based on the SinoMOS 1 μm 40 V CMOS process, a novel power factor corrention (PFC) converter with a low-power variable frequency function is presented. The circuit introduces a multi-vector error amplifier and a programmable oscillator to achieve frequency modulation, which provides a rapid dynamic response and precise output voltage clamping with low power in the entire load. According to the external load variation, the system can modulate the circuit operating frequency linearly, thereby ensuring that the PFC converter can work in frequency conversion-mode.Measured results show that the normal operating frequency of the PFC converter is 5–6 kHz, the start-up current is 36 μA, the stable operating current is only 2.43 mA, the efficiency is 97.3%, the power factor (PF) is 0.988, THD is 3.8%, the load adjust rate is 3%, and the linear adjust rate is less than 1%. Both theoretical and practical results reveal that the power consumption of the whole supply system is reduced efficiently, especially when the load varies. The active die area of the PFC converter chip is 1.61×1.52 mm2.

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 A from the power supply. This circuit is suitable for low power applications.

A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to VTlnT realized by utilizing voltage to current converters and the voltage current characteristics of a base–emitter junction, is presented. Experiment results of the proposed bandgap reference implemented with the CSMC 0.5-μm CMOS process demonstrate that a temperature coefficient of 3.9 ppm/℃ is realized at 3.6 V power supply, a power supply rejection ratio of 72 dB is achieved, and the line regulation is better than 0.304 mV/V dissipating a maximum supply current of 42 μA.