On the condition of electric-longitudinal-optical (LO) phonon strong coupling in both two- and three-dimensional parabolic quantum dots (QDs), we obtain the eigenenergies of the ground state (GS) and the first excited state (ES), the eigenfunctions of the GS and the first ES by using a variational method of Pekar type. This system in QD may be employed as a quantum system–quantum bit (qubit). When the electron is in the superposition state of the GS and the first ES, we obtain the time evolution of the electron density. The relations of both the electron probability density and the period of oscillation with the electric-LO phonon coupling strength and confinement length are discussed.

The binding energies of bound polarons near the interface of a strained wurtzite GaN/AlxGa1-xN heterojunction are studied by using a modified LLP variational method and a simplified coherent potential approximation under hydrostatic pressure and an external electric field. Considering the biaxial strain due to lattice mismatch or epitaxial growth, the uniaxial strain effects and the influences of the electron–phonon interaction as well as impurity–phonon interaction including the effects of interface-optical phonon modes and half-space phonon modes, the binding energies as functions of pressure, the impurity position, areal electron density and the phonon effect on the Stark energy shift are investigated. The numerical result shows that the contributions from the interface optical phonon mode with higher frequency and the LO-like half space mode to the binding energy and the Stark energy shift are important and obviously increase with increasing hydrostatic pressure, whereas the interface optical phonon mode with lower frequency and the TO-like half space mode are extremely small and are insensitive to the impurity position and hydrostatic pressure. It is also shown that the conductive band bending should not be neglected.

A theoretical model has been developed to study nonlinear behaviors in a GaAs/AlGaAs heterostructure. We show that the system can exhibit chaotic oscillations under transverse magnetic fields and an electric field. The time-delayed feedback method was applied to stabilize the unstable periodic orbits (UPOs) embedded in the chaotic attractor. A bifurcation specified by a successive decrease in the number of UPOs with delayed time and feedback strength was revealed, indicating the stabilization of UPOs under feedback control. Noticeably, the introduction of a feedback perturbation will sometimes induce chaotic states that do not exist in the unperturbed system.

There are several diffusion processes with different temperatures in modern semiconductor technology. The impurity distribution after these diffusion processes is analyzed and a simple expression for describing the distribution is given. It is found that the impurity distribution after multiple diffusion processes can be characterized with an effective diffusion length. The relation between this effective diffusion length and the diffusion lengths of each diffusion process is given and shows itself to be very simple and instructive. The results of the expression agree well with numerical simulations by using SUPREM Ⅳ. An example of the application of the expression is also shown.

Sol–gel derived nanostructured CeO2 film was deposited on glass substrate using by dip-coating technique with annealing at 650 ℃. X-ray diffraction (XRD), scanning electron microscopy (SEM), Fourier transform infrared (FTIR), UV/vis and photoluminescence (PL) spectroscopy studies were employed to analyze the structural and optical properties of the sol–gel derived nanostructured CeO2 film. The average crystallite size was estimated from the XRD pattern using by Scherrer equation as about 3–4 nm. An SEM micrograph shows that the film was porous in nature and crack free. The UV-visible absorption spectroscopic measurement results showed that the products had conspicuous quantum size effects. The absorption spectrum indicates that the sol–gel derived nanostructured CeO2 film has a direct bandgap of 3.23 eV and the photoluminescence spectra of the film show a strong band at 378 nm: it may have a promising application as an optoelectronic material.

A novel three-dimensional lattice model of tetrapod-like zinc oxide whisker (T-ZnOw) resin matrix composite with a coordination number of 12 is constructed based on the special structure of T-ZnOw; the percolation phenomenon of the system is simulated by theMonte Carlo method, and the percolation threshold is obtained at 23.2%. The critical mixing ratio of T-ZnOw is calculated by considering the practical factors, and the result basically agrees with the reported one. Theoretical calculation shows that the critical mixing ratio mainly depends on the L/D ratio of T-ZnOw, and is also related to the size of T-ZnOw as well as the preparation method of the composite. The microwave absorbing mechanism of T-ZnOw composite is discussed, and conductivity loss and point discharge caused by the polarization effect are regarded to be two important means of energy dissipation.

Five-period AlGaSb/GaSb multiple quantum wells (MQW) are grown on a GaSb buffer. Through optimizing the AlSb nucleation layer, the low threading dislocation density of the MQW is found to be (2.50±0.91)E8 cm-2 in 1- μm GaSb buffer, as determined by plan-view transmission election microscopy (TEM) images. High reso-lution TEM clearly shows the presence of 90° misfit dislocations with an average spacing of 5.4 nm at the AlSb/GaAs interface, which effectively relieve most of the strain energy. In the temperature range from T D 26 K to 300 K, photoluminescence of the MQW is dominated by the ground state electron to ground state heavy hole (e1–hh1) transition, while a high energy shoulder clearly seen at T > 76 K can be attributed to the ground state electron to ground state light hole (e1–lh1) transition.

Mercury cadmium telluride films were grown by the RF magnetron sputtering technique at different sputtering powers. In experiment, X-ray diffraction (XRD) and atomic forcemicroscopy (AFM) have been used to characterize the microstructure of HgCdTe films. The experimental results showed that when the growth power increased, the growth rate of HgCdTe films increased; when the growth power was less than 30 W, the HgCdTe film deposited by RF magnetron sputtering was amorphous; when the growth power was more than 30 W, the films exhibited polycrystalline structure. Films deposited at different growth rates were found to have characteristically different formations and surface morphologies; as observed through AFM, the surface morphology is composed of longitudinal islands forming a maze-like pattern in the high deposition rate. AFM analysis also illustrated that a significant reduction in the areal density of large islands and characteristically smoother films was achieved using a low deposition rate.

This paper reports the experimental results for the humidity dependent properties of an organic field effect transistor. The organic field effect transistor was fabricated on thoroughly cleaned glass substrate, in which the junction between the metal gate and the organic channel plays the role of gate dielectric. Thin films of organic semiconductor copper phthalocynanine (CuPc) and semitransparent Al were deposited in sequence by vacuum thermal evaporation on the glass substrate with preliminarily deposited Ag source and drain electrodes. The output and transfer characteristics of the fabricated device were performed. The effect of humidity on the drain current, drain current-drain voltage relationship, and threshold voltage was investigated. It was observed that humidity has a strong effect on the characteristics of the organic field effect transistor.

A thin film of blended poly-N-epoxypropylcarbazole (PEPC) (25 wt.%), nickel phthalocyanine (NiPc) (50 wt.%) and ZnO nano-powder (25 wt.%) in benzene (5 wt.%) was spin-coated on a glass substrate with silver electrodes to produce a surface-type Ag/PEPC/NiPc/ZnO/Ag capacitive and resistive sensor. Sensors with two different PEPC/NiPc/ZnO film thicknesses (330 and 400 nm) were fabricated and compared. The effects of humidity on capacitance and resistance of the Ag/PEPC/NiPc/ZnO/Ag sensors were investigated at two frequencies of the applied voltage: 120 Hz and 1 kHz. It was observed that at 120 Hz under humidity of up to 95% RH the capacitance of the sensors increased by 540 times and resistance decreased by 450 times with respect to humidity conditions of 50% RH. It was found that the sensor with a thinner semiconducting film (330 nm) was more sensitive than the sensor with a thicker film (400 nm). The sensitivity was improved when the sensor was used at a lower frequency as compared with a high frequency. It is assumed that the humidity response of the sensors is associated with absorption of water vapors and doping of water molecules in the semiconductor blend layer. This had been proven by simulation of the capacitance–humidity relationship.

The influence of gate-head and gate-source-spacing on the performance of AlGaN/GaN HEMTs was studied. Suggestions are then made to improve the performance of high frequency power AlGaN/GaN HEMTs by optimizing the gate-structure. Reducing the field-plate length can effectively enhance gain, current gain cutoff frequency and maximum frequency of oscillation. By reducing the field-plate length, devices with 0.35 μm gate length have exhibited a current gain cutoff frequency of 30 GHz and a maximum frequency of oscillation of 80 GHz. The maximum frequency of oscillation can be further optimized either by increasing the gate–metal thickness, or by using a τ-shape gate (the gate where the gate-head tends to the source side). Reducing the gate–source spacing can enhance the maximum drain-current and breakdown voltage, which is beneficial in enhancing the maximum output power of AlGaN/GaN HEMTs.

The total-dose response and annealing effect of p-channel metal oxide semiconductor field-effect transistors (PMOSFETs) were investigated at various dose rates and biasing conditions. The results show that the shift of threshold voltage is more obvious when the dose rate is decreased. Under the various dose rates and biasing conditions, some have exhibited a time-dependent effect and others showed enhanced low-dose-rate sensitivity (ELDRS). Finally, using the subthreshold-separating method, the threshold-voltage shift is separated into shifts due to interface states and oxide-trapped charges, and the underlying mechanisms of the observed effects are discussed. It has been indicated that the ELDRS effect results from the different quantities of the interface states generated at high and low dose rates.

The dispersion equations of bulk modes and surface modes in a rectangular waveguide of semiconductor metamaterial are derived by a modified “Marcatili’s method”. The cutoff frequencies of the lowest TM bulk mode are discussed, and the Brillouin diagrams of different bulk modes are drawn. They demonstrate that different heights correspond to different guidance frequency ranges which have no superposition with each other and a waveguide with a larger height possesses a wider passband of light. In addition, tendencies of degeneracy for different modes are observed. Finally, the existence of surface modes is verified by a graphical method.

A novel MEMS accelerometer with grid strip capacitors is developed. The mechanical and electrical noise can be reduced greatly for the novel structure design. ANSOFT-Maxwell software was used to analyze the fringing electric field of the grid strip structure and its effects on the designed accelerometer. The effects of the width, thickness and overlapping width of the grid strip on the sensing capacitance are analyzed by using the ANSOFT-Maxwell software. The results show that the parameters have little effect on the characteristics of the presented accelerometer. The designed accelerometer was fabricated based on deep RIE and silicon–glass bonding processes. The preliminary tested sensitivities are 0.53 pF/g and 0.49 pF/g in the x and y axis directions, respectively. A resonator with grid strip structure was also fabricated whose tested quality factor is 514 in air, which proves that the grid strip structure can reduce mechanical noise.

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented. The LNA is fabricated in a 0.18-μm SiGe BiCMOS process, covering the 2.1 to 6 GHz frequency band. After optimized noise modeling and circuit design, the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point (IIP3) is –8 dBm at 6 GHz, and the noise figure is from 2.3 to 3.8 dB in the operating band. The overall power consumption is 8 mW at 2.5 V voltage supply.

A wide-dynamic-range CMOS image sensor (CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion (FD) of a five-transistor active pixel is proposed. With optimized pixel operation, the response curve is compressed and a wide dynamic range image is obtained. A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18 μm CIS process. With the double exposure time 2.4 ms and 70 ns, the dynamic range of the proposed sensor is 80 dB with 30 frames per second (fps). The proposed CMOS image sensor meets the demands of applications in security surveillance systems.

This paper presents a 1.1 mW 87 dB dynamic range third order ΔΣ modulator implemented in 0.18 μm CMOS technology for audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed. A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.

A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented. The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area. Implemented in the 0.18-µm mixed-signal CMOS process, the divider operates over a wide range of 1–7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is –125.3 dBc/Hz at an offset of 100 kHz. The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2. The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.

This paper presents a variable gain low-noise amplifier (VG-LNA) for 5 GHz applications. The effect of the input parasitic capacitance on the inductively degenerated common source LNA’s input impedance is analyzed in detail. A new ESD and LNA co-design method was proposed to achieve good performance. In addition, by using a simple feedback loop at the second stage of the LNA, continuous gain control is realized. The measurement results of the proposed VG-LNA exhibit 25 dB ((-3.3 dB to 21.7 dB) variable gain range, 2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain, while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.

A single-loop fourth-order sigma–delta interface circuit for a closed-loop micromachined accelerometer is presented. Two additional electronic integrators are cascaded with the micromachined sensing element to form a fourth-order loop filter. The three main noise sources affecting the overall system resolution of a sigma–delta accelerometer, mechanical noise, electronic noise and quantization noise, are analyzed in detail. Accurate mathematical formulas for electronic and quantization noise are established. The ASIC is fabricated in a 0.5 μm two-metal two-poly n-well CMOS process. The test results indicate that the mechanical noise and electronic noise are 1 μg/Hz1/2 and 8 μV/Hz1/2 respectively, and the theoretical models of electronic and quantization noise agree well with the test and simulation results.

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metal–oxide–semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 μm CMOS technology. This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current–voltage characteristics. At the same time it can realize a modulation effect by the third terminal. Based on the MOS-NDR transistor, a flexible logic circuit is realized in this work, which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor. It turns out that MOS- NDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed. Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL. An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit. Through integrating the D-latch with ‘OR’ logic for dual-modulus operation, the delays associated with both the ‘OR’ and D-flip-flop (DFF) operations are reduced, and the complexity of the circuit is also decreased. The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model. The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system. The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only –101.52 dBc/Hz. The circuit exhibits a low RMS jitter of 3.3 ps. The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.

A high-performance low-power ΣΔ analog-to-digital converter (ADC) for digital audio applications isdescribed. It consists of a 2-1 cascaded ΣΔ modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2, which dissipates only 2.1 mA quiescent current in the analog circuits.

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm–C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog base- band circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mWfor Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to 40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth- order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

Two different scalable models developed based on enhanced 1-π and 2-π topologies are presented for on-chip spiral inductor modeling. All elements used in the two topologies for accurately predicting the characteristics of spiral inductors at radio frequencies are constructed in geometry-dependent equations for scalable modeling. Then a comparison between the 1-π and 2-π scalable models is made from the following aspects: the complexity of equivalent circuit models and parameter-extraction procedures, scalable rules and the accuracy of scalable models. The two scalable models are further verified by the excellent match between the measured and simulated results on extracted parameters up to self-resonant frequency (SRF) for a set of spiral inductors with different L, R and N, which are fabricated by employing 0.18-μm 1P6M RF CMOS technology.

To improve the power sequencing performance of the system-on-a-chip (SOC), a novel embedded soft-start circuit is presented. A seamless soft-start reference voltage is obtained with 7 bits DAC, which can not only restrain the turning point overshoot, but also improve the output accuracy and the poor loading capability, reduce the pin number and save PCB area. The whole DC–DC converter has been fabricated in a 0.35 μm CMOS process. The measurement results show that the chip starts up successfully with 250 μs soft-start time under conditions of 400 kHz switching frequency, 2.5 V DC–DC output and 1.8 V LDO output. Stable operation after soft-start is also shown.

Bymeans of analyzing the I–V characteristic curve of NiSi/n-Si Schottky junction diodes (NiSi/n-Si SJDs), abstracting the effective Schottky barrier height (φB, eff) and the ideal factor of NiSi/n-Si SJDs and measuring the sheet resistance of NiSi films (RNiSi), we study the effects of different dopant segregation process parameters, including impurity implantation dose, segregation annealing temperature and segregation annealing time, on theφB, eff of NiSi/n-Si SJDs and the resistance characteristic of NiSi films. In addition, the changing rules of φB, eff and RNiSi are discussed.

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.