Impurities and their influence on the properties of InAs single crystals have been studied by combining the results of glow discharge mass spectrometry (GDMS), Hall measurements, Raman scattering and infrared absorption. The results indicate that carbon is a major impurity in LEC-InAs single crystals and exhibits a significant influence on the electrical and optical properties.

The feasibility of a new fabrication route for N and Ga codoped p-type ZnO thin films on glass substrates, consisting of DC sputtering deposition of Zn3N2:Ga precursors followed by in situ oxidation in high purity oxygen, has been studied. The effects of oxidation temperature on the structural, optical and electrical properties of the samples were investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM), optical transmittance and Hall effect measurements. The results were compared to a control film without Ga. XRD analyses revealed that the Zn3N2 films entirely transformed into ZnO films after annealing Zn3N2 films in oxygen over 500 ℃ for 2 h. Hall effect measurements confirmed p-type conduction in N and Ga codoped ZnO films with a low resistivity of 19.8 Ω?cm, a high hole concentration of 4.6E18 cm3 and a Hall mobility of 0.7 cm2/(V s). These results demonstrate a promising approach to fabricate low resistivity p-type ZnO with high hole concentration.

An optically transparent electrode, indium tin oxide (ITO) film is fabricated by vacuum E-beam evaporation. The thermal annealing effects on the ITO/GaP contact have been investigated by means of the transmission line model method. Under 435 ℃, with rapid thermal annealing for 40 s in N2 ambient, the ITO contact resistance reaches the minimized value of 4.3 × 10^-3 Ω·cm². The results from Hall testing and Auger spectra analysis indicate that the main reasons for the change of the contact resistance are the difference in the concentration of carriers and the diffusion of In, Ga, O. Furthermore, the reliability of AlGaInP LEDs with a 300-nm thickness transparent conducting ITO film is studied. The increase of LED chip voltage results from the degradation of ITO film. Moreover the difference between the thermal expansion coefficient of GaP and ITO results in the invalidation of the LED chip.

Ti/WSi/Ni contact to n-type SiCN was investigated using the circular transmission line method. Current–voltage characteristics, X-ray diffraction and X-ray photoelectron spectroscopy were used to characterize the contacts before and after annealing. It is shown that the conducting behavior of the contacts is dependent on the annealing temperature. After annealing at 900 ℃ or above, ohmic contacts with specific contact resistivity were achieved. The 1000-℃-annealed contact exhibits the lowest specific contact of 3.07 × 10^-5 Ω·cm². The formation of ohmic contact with low specific contact resistivity was discussed.

An optically controlled SiC/SiCGe lateral power transistor based on superjunction structure has been proposed, in which n-SiCGe/p-SiC superjunction structure is employed to improve device figure of merit. Performance of the novel optically controlled power transistor was simulated using Silvaco Atlas tools, which has shown that the device has a very good response to the visible light and the near infrared light. The optoelectronic responsivities of the device at 0.5 μm and 0.7 μm are 330 mA/W and 76.2 mA/W at 2 V based voltage, respectively.

The exponential dependence of the potential barrier height f_c on the biased voltages of the inorganic/organic static induction transistor (SIT/OSIT) through a normalized approach in the low-current regime is presented. It shows a more accurate description than the linear expression of the potential barrier height. Through the verification of the numerical calculated and experimental results, the exponential dependence of f_c on the applied biases can be used to derive the I–V characteristics. For both SIT and OSIT, the calculated results, using the presented relationship, are agreeable with the experimental results. Compared to the previous linear relationship, the exponential description of f_c can contribute effectively to reduce the error between the theoretical and experimental results of the I–V characteristics.  

The fabrication of AlGaN/GaN double-channel high electron mobility transistors on sapphire substrates is reported. Two carrier channels are formed in an AlGaN/GaN/AlGaN/GaN multilayer structure. The DC performance of the resulting double-channel HEMT shows a wider high transconductance region compared with single-channel HEMT. Simulations provide an explanation for the influence of the double-channel on the high transconductance region. The buffer trap is suggested to be related to the wide region of high transconductance. The RF characteristics are also studied.

The microwave dynamic load line characteristics of an advanced InGaP HBT are investigated experimentally and analyzed at small signal level and at large signal level for microwave power amplification. Investigation results show that the dynamic load curves are not always like an elliptic curve, and the current extreme points do not locate at voltage extreme points. The dynamic load curve current extreme point lines sit at the small signal load line up to the P-3dB point, and the lines show a constant slope from a small signal up to the saturation power point. A method to calculate the realistically delivered power to load is presented which fits the test result well.

The response of a bipolar transistor (BJT) under a square-wave electromagnetic pulse (EMP) with different injecting voltages is investigated. Adopting the curve fitting method, the relationship between the burnout time, the damage energy and the injecting voltage is obtained. Research shows that the damage energy is not a constant value, but changes with the injecting voltage level. By use of the device simulator Medici, the internal behavior of the burned device is analyzed. Simulation results indicate that the variation of the damage energy with injecting voltage is caused by the distribution change of hot spot position under different injection levels. Therefore, the traditional way to evaluate the trade-off between the burnout time and the injecting voltage is not comprehensive due to the variation of the damage energy.

This paper extends the flux scattering method to study the carrier transport property in nanoscale MOSFETs with special emphasis on the low-field mobility and the transport mechanism transition. A unified analytical expression for the low-field mobility is proposed, which covers the entire regime from drift-diffusion transport to quasi-ballistic transport in 1-D, 2-D and 3-D MOSFETs. Two key parameters, namely the long-channel low-field mobility (μ0) and the low-field mean free path (λ0), are obtained from the experimental data, and the transport mechanism transition in MOSFETs is further discussed both experimentally and theoretically. Our work shows that λ0 is available to characterize the inherent transition of the carrier transport mechanism rather than the low-field mobility. The mobility reduces in the MOSFET with the shrinking of the channel length; however, λ0 is nearly a constant, and λ0 can be used as the “entry criterion”to determine whether the device begins to operate under quasi-ballistic transport to some extent.

Total dose effects and annealing behavior of domestic n-channel VDMOS devices under different bias conditions were investigated. The dependences of typical electrical parameters such as threshold voltage, breakdown voltage, leakage current, and on-state resistance upon total dose were discussed. We also observed the relationships between these parameters and annealing time. The experiment results show that: the threshold voltage negatively shifts with the increasing of total dose and continues to decrease at the beginning of 100 ℃ annealing; the breakdown voltage under the drain bias voltage has passed through the pre-irradiation threshold voltage during annealing behaving with a “rebound” effect; there is a latent interface-trap buildup (LITB) phenomenon in the VDMOS devices; the leakage current is suppressed; and on-state resistance is almost kept constant during irradiation and annealing. Our experiment results are meaningful and important for further improvements in the design and processing.

A new NI (nC charge islands) high voltage device structure based on E-SIMOX (epitaxy-the separation by implantation of oxygen) substrate is proposed. It is characterized by equidistant high concentration nC-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field (EV/ are located in the spacing of two neighboring nC-regions on the interface by the force from lateral electric field (EL/ and the compositive operation of Coulomb’s forces with the ionized donors in the undepleted nC-regions. This effectively enhances the electric field of dielectric buried layer (EI/ and increases breakdown voltage (VB/. An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology (E-SIMOX).

A novel empirical model for large-signal modeling of an RF-MOSFET is proposed. The proposed model is validated in the DC, AC, small-signal and large-signal characteristics of a 32-finger nMOSFET fabricated in SMIC’s 0.18 μm RF CMOS technology. The power dissipation caused by self-heating is described. Excellent agreement is achieved between simulation and measurement for DC, S-parameters (50 MHz–40 GHz), and power characteristics, which shows that our model is accurate and reliable.

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q–V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs.This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The –3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.

A novel low temperature solid state electric field sensor is demonstrated as a promising sensor. The sensor is a type of constant voltage Wheatstone bridge whose resistors are four direct gate SOI MOSFET devices. It is demonstrated in theory that the output voltage signal is proportional to the electric field E, the temperature drift is about zero when the temperature is in the range from 200 to 400 K, and the doping concentration is in the range from 1E14 to 1E16 cm-3. The experiment results indicate that the resolution of the sensor is about 3.27 mV for a 1000 V/m electric field at 300 K, and the voltage drift by an amount is about 47 V/m field signal when the degree temperature is in the range from 300 to 370 K, which is much smaller than the current drift of a single MOSFET which is about 10000 V/m field signal.

A high speed sampler for a sub-sampling impulse radio UWB receiver is presented. In this design, the sampler uses a time-interleaved topology with a single track and hold circuit, full custom clock generator, and offset cancelled comparator. These three main blocks are also discussed and analyzed. The circuit was fabricated in 0.13 μm CMOS technology. Measurement results indicate that the sampler achieves a maximum 3 GS/s sampling rate. The power consumption of the sampler is 27 mW under a supply voltage of 1.2 V. The total chip area including pads is 1.4×0.97 mm2.

A differential power amplifier (PA), designed using the linear-phase filter model, for a BPSK modulated ultra-wideband (UWB) system operating in the 3–5 GHz frequency range is presented. The proposed PA was fabricated using 0.18 μm SMIC CMOS technology. To achieve sufficient linearity and efficiency, this PA operates in the class-AB region, delivering an output power of 8.5 dBm at an input-1 dB compression point of –0.5 dBm. It consumes 28.8 mW, realizing a flat gain of 9.11±0.39 dB and a very low group delay ripple of ±8 ps across the whole band of operation.

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210×180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.

Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power overheads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.

An LED driving circuit in accurate proportional current sampling mode is designed and fabricated based on CSMC 0.5 μm standard CMOS technology. It realizes accurate sensing of sampling current variation with output driving current. A better constant output current characteristic is achieved by using an amplifier to clamp the drain voltage of both the sampling MOSFET and power MOSFET to the same value with feedback control. Small signal equivalent circuit analysis shows that the small signal output resistance in the accurate proportional current sampling mode circuit is much larger than that in a traditional proportional current sampling mode circuit, and circuit stability could be assured. Circuit simulation and chip testing results show that when the LED driving current is 350 mA and the power supply is 6 V with ±10% variation, the stability of the output constant current of the accurate proportional current sampling mode LED driving IC will show 41% improvement over that of a traditional proportional current sampling mode LED driving IC.

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.

Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closed-form expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.

A new mixed-integrator-based bi-quad cell is proposed. An alternative synthesis mechanism of complex poles is proposed compared with source-follower-based bi-quad cells which is designed applying the positive feedback technique. Using the negative feedback technique to combine different integrators, the proposed bi-quad cell synthesizes complex poles for designing a continuous time filter. It exhibits various advantages including compact topology, high gain, no parasitic pole, no CMFB circuit, and high capability. The fourth-order Butterworth lowpass filter using the proposed cells has been fabricated in 0.18 μm CMOS technology. The active area occupied by the filter with test buffer is only 200×170 μm2. The proposed filter consumes a low power of 201 μW and achieves a 68.5 dB dynamic range.

This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically??20 dBc up to 44 GHz. The MMIC works at VDD = 3.5 V, VSS =-3.5 V, Id = 200 mA and the chip size is 1.5×1.8 mm2.