Terahertz (THz) technology can be used in information science, biology, medicine, astronomy, and environmental science. THz sources are the key devices in THz applications. The author gives a brief review of THz semiconductor sources, such as GaAs_1-xN_x Gunn-like diodes, quantum wells (QWs) negative-effective-mass (NEM) THz oscillators, and the THz quantum cascade lasers (QCLs). THz current self-oscillation in doped GaAs_1-xN_x diodes driven by a DC electric field was investigated. The current self-oscillation is associated with the negative differential velocity effect in the highly nonparabolic conduction band of this unique material system. The current self-oscillations and spatiotemporal current patterns in QW NEM p⁺pp⁺ diodes was studied by considering scattering contributions from impurities, acoustic phonons, and optic phonons. It is indicated that both the applied bias and the doping concentration strongly influence the patterns and self-oscillating frequencies. The NEM p⁺pp⁺ diode may be used as an electrically tunable THz source. Meanwhile, by using the Monte Carlo method, the device parameters of resonant-phonon THz QCLs were optimized. The results show that the calculated gain is more sensitive to the injection barrier width, the doping concentration, and the phonon extraction level separation, which is consistent with the experiments.

HfO₂ films were deposited by atomic layer deposition through alternating pulsing of Hf[N(C₂H₅)(CH₃)]₄ and H₂O₂. A trace amount of nitrogen was incorporated into the HfO₂ through ammonia annealing. The composition, the interface stability of the HfO₂/Si stack and the optical properties of the annealed films were analyzed to investigate the property evolution of HfO₂ during thermal treatment. With a nitrogen concentration increase from 1.41 to 7.45%, the bandgap of the films decreased from 5.82 to 4.94 eV.

We investigate the recombination mechanism in an a-Si/c-Si interface, and analyze the key factors that influence the interface passivation quality, such as Q_s, δ_p/δ_n and D_it. The polarity of the dielectric film is very important to the illustration level dependent passivation quality; when nδ_n=pδ_p and the defect level E_t equal to E_i (c-Si), the defect states are the most effective recombination center, AFORS-HET simulation and analysis indicate that emitter doping and a-Si/c-Si band offset modulation are effective in depleting or accumulating one charged carrier. Interface states (D_it) severely deteriorate V_oc compared with J_sc for a-Si/c-Si HJ cell performance when D_it is over 1 × 10¹⁰ cm^-2·eV^-1. For a c-Si(P)/a-Si(P⁺) structure, φ_BSF in c-Si and φ₀ in a-Si have different performances in optimization contact resistance and c-Si(P)/a-Si(P⁺) interface recombination.

A physics-based analytical model for symmetrically biased double-gate (DG) MOSFETs considering quantum mechanical effects is proposed. Schrödinger's and Poisson's equations are solved simultaneously using a variational approach. Solving the Poisson and Schrödinger equations simultaneously reveals quantum mechanical effects (QME) that influence the performance of DG MOSFETs. The inversion charge and electrical potential distributions perpendicular to the channel are expressed in closed forms. We systematically evaluated and analyzed the potentials and inversion charges, taking QME into consideration, in Si based double gate devices. The effect of silicon thickness variation in inversion-layer charge and potentials are quantitatively defined. The analytical solutions provide good physical insight into the quantization caused by quantum confinement under various gate biases.

We study, by means of numerical simulation, the impact of doping and traps on the performance of the “solar blind” ultraviolet Schottky detector based on AlGaN. We implemented physical models and AlGaN material properties taken from the literature, or from the interpolation between the binary materials (GaN and AlN) weighted by the mole fractions. We found that doping and traps highly impact the spectral response of the device, and in particular a compromise in the doping concentration must be reached in order to optimize the spectral response of the detector. These results give us a powerful tool to quantitatively understand the impact of elaboration and processing conditions on photodetector characteristics, and thus identify the key issues for the development of the technology.

AlGaN/GaN HEMTs with 0.2 μm V-gate recesses were developed. The 0.2 μm recess lengths were shrunk from the 0.6 μm designed gate footprint length after isotropic SiN deposition and anisotropic recessed gate dry etching. The AlGaN/GaN HEMTs with 0.2 μm V-gate recesses on sapphire substrates exhibited a current gain cutoff frequency f_t of 35 GHz and a maximum frequency of oscillation f_max of 60 GHz. At 10 GHz frequency and 20 V drain bias, the V-gate recess devices exhibited an output power density of 4.44 W/mm with the associated power added efficiency as high as 49%.

A novel lateral IGBT with a second gate on the emitter portion is presented. A PMOS transistor, driven by the proposed device itself, is used to short the PN junction at the emitter while turned off. Low on state voltage and fast turn off speed are obtained without side-effects such as snapback I-V characteristics and difficulties of process complexity. Numerical simulation results show a drop of fall time from 120 to 12 ns and no increase of on state voltage.

A physical drain current model of polysilicon thin-film transistors based on the charge-sheet model, the density of trap states and surface potential is proposed. The model uses non-iterative calculations, which are single-piece and valid in all operation regions above flat-band voltage. The distribution of the trap states, including both Gaussian deep-level states and exponential band-tail states, is also taken into account, and parameter extraction of trap state distribution is developed by the optoelectronic modulation spectroscopy measurement method. Comparisons with the available experimental data are accomplished, and good agreements are obtained.

This paper presents a new phenomenon, where the holding-voltage of a silicon-controlled rectifier acts as an electrostatic-discharge protection drift in diverse film thicknesses in silicon-on-insulator (SOI) technology. The phenomenon was demonstrated through fabricated chips in 0.18 μm SOI technology. The drift of the holding voltage was then simulated, and its mechanism is discussed comprehensively through ISE TCAD simulations.

SRAM-based FPGA devices are irradiated by ⁶⁰Coγ rays at various dose rates to investigate total dose effects and the evaluation method. The dependences of typical electrical parameters such as static power current, peak-peak value, and delay time on total dose are discussed. The experiment results show that the static power current of the devices reduces rapidly at room temperature (25 ℃) and high temperature (80 ℃) annealing after irradiation. When the device is irradiated at a low dose rate, the delay time and peak-peak value change unobviously with an increase in the accumulated dose. In contrast, the function parameters completely fail at 2.1 kGy(Si) when the dose rate increases to 0.71 Gy(Si)/s.

A simple method has been developed for the fabrication of a silicon microlens array with a 100% fill factor and a smooth configuration. The microlens array is fabricated by using the processes of photoresist (SU8-2005) spin coating, thermal reflow, thermal treatment and reactive ion etching (RIE). First, a photoresist microlens array on a single-polished silicon substrate is fabricated by both thermal reflow and thermal treatment technologies. A typical microlens has a square bottom with size of 25 μm, and the distance between every two adjacent microlenses is 5 μm. Secondly, the photoresist microlens array is transferred to the silicon substrate by RIE to fabricate the silicon microlens array. Experimental results reveal that the silicon microlens array could be formed by adjusting the quantities of the reactive ion gases of SF₆ and O₂ to proper values. In this paper, the quantities of SF₆ and O₂ are 60 sccm and 50 sccm, respectively, the corresponding etch ratio of the photoresist and the silicon substrate is 1 to1.44. The bottom size and height of a typical silicon microlens are 30.1 μm and 3 μm, respectively. The focal lengths of the microlenses ranged from 15.4 to 16.6 μm.

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

This paper presents a single-ended input differential output low-noise amplifier intended for GPS applications. We propose a method to reduce the gain/amplitude and phase imbalance of a differential output exploiting the inductive coupling of a transformer or center-tapped differential inductor. A detailed analysis of the theory of imbalance reduction, as well as a discussion on the principle of choosing the dimensions of a transformer, are given. An LNA has been implemented using TSMC 0.18 μm technology with ESD-protected. Measurement on board shows a voltage gain of 24.6 dB at 1.575 GHz and a noise figure of 3.2 dB. The gain imbalance is below 0.2 dB and phase imbalance is less than 2 degrees. The LNA consumes 5.2 mA from a 1.8 V supply.

A low noise distributed amplifier consisting of 9 gain cells is presented. The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor (PHEMT) technology from Win Semiconductor of Taiwan. A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB. A novel cascode structure is adopted to extend the output voltage and bandwidth. The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of ±1 dB in the 2-20 GHz band. The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz. The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point (IIP3), which demonstrates the excellent performance of linearity. The power consumption is 300 mW with a supply of 5 V, and the chip area is 2.36 × 1.01 mm².

This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13 μm CMOS technology. The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter. A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration. Pulse-swallow topology with a multistage noise shaping ΔΣ modulator is adopted in the frequency divider design. The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes. Measurement results show that the phase noise of the synthesizer achieves -91.3 dBc/Hz and -117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset, separately. The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm².

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, -7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply.

An 800 × 600 pixel organic light-emitting diode-on-silicon (OLEDoS) driving circuit is proposed. The pixel cell circuit utilizes a subthreshold-voltage-scaling structure which can modulate the pixel current between 170 pA and 11.4 nA. In order to keep the voltage of the column bus at a relatively high level, the sample-and-hold circuits adopt a ping-pong operation. The driving circuit is fabricated in a commercially available 0.35 μm two-poly four-metal 3.3 V mixed-signal CMOS process. The pixel cell area is 15 × 15 μm² and the total chip occupies 15.5 × 12.3 mm². Experimental results show that the chip can work properly at a frame frequency of 60 Hz and has a 64 grayscale (monochrome) display. The total power consumption of the chip is about 85 mW with a 3.3V supply voltage.

For low-power low total harmonic distortion (THD), based on the CSMC 0.5 μm BCD process, a novel boost power factor correction (PFC) converter in critical conduction mode is discussed and analyzed. Feedforward compensation design is introduced in order to increase the PWM duty cycle and supply more conversion energy near the input voltage zero-crossing points, thus regulating the inductor current of the PFC converter and compensating the system loop gain change with ac line voltage. Both theoretical and practical results reveal that the proposed PFC converter with feedforward compensation cell has better power factor and THD performance, and is suitable for low-power low THD design applications. The experimental THD of the boost PFC converter is 4.5%, the start-up current is 54 μA, the stable operating current is 3.85 mA, the power factor is 0.998 and the efficiency is 95.2%.

By virtue of the negative electric parameter concept, i.e. negative lumped resistance, inductance, conductance and capacitance (N-RLGC), the lumped equivalent models of transmission line systems, including the circuit model, two-port π-network and T-network, are given. We start from the N-segment-ladder-like equivalent networks composed distributed parameters, and achieve the input impedance in the form of a continued fraction. Utilizing the continued fraction theory, the expressions of input impedance are obtained under three kinds of extreme cases, i.e. the load impedances are equal to zero, infinity and characteristic impedance, respectively. When the number of segment N is limited to infinity, they are transformed to lumped elements. Comparison between the distributed model and lumped model of transmission lines, the expression of tanh γd, which is the key term in the transmission line equations, are obtained by RLGC, furthermore, according to input admittance, admittance matrix and ABCD matrix of transmission lines, the lumped equivalent circuit models, π-networks and T-networks have been given. The models are verified in the frequency and time domain, respectively, showing that the models are accurate and efficient.

a low-power register file is designed by using a low-swing strategy and modified NAND address decoders. The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power. This method contains two parts: WRITE and READ strategy. In the WRITE low-swing scheme, the modified memory cell is used to support low-swing WRITE. The modified NAND decoder not only dissipates less power, but also enables a great deal of area reduction. Compared with the conventional single-ended register file, the low-swing strategy saves 34.5% and 51.15% bit-line power in WRITE and READ separately. The post simulation results indicate a 39.4% power improvement when the twelve ports are all busy.

A register file (RF) with 32 × 32 capacity and 4-read 2-write (4R2W) ports is presented and analyzed in detail. A new output structure using a MUX and a latch is proposed. It eliminates any dynamic or analog circuit in the read path, and thus it can improve robustness and reduce power at the same time. We also simplify the timing sequence due to the output scheme. The simplified timing circuit not only cuts down the power but also improves the robustness. In addition, less power is achieved when successive read of “0” or “1” is performed. The RF has been fabricated in TSMC 65 nm technology, and the chip test demonstrates that it can operate at 0.8 GHz, consuming 7.2 mW at 1.2 V.

Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO₂ interface trimming. The within-the-wafer ILD thickness non-uniformity can reach 4.19% with a wafer edge exclusion of 5 mm. SEM results indicated that there was little “dish effect” on the 0.4 μm gate-stack structure and finally achieved a good planarization profile on the whole substrate. The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.

Different-dose phosphorus ion implantation into 4H-SiC followed by high-temperature annealing was investigated. AlN/BN and graphite post-implantation annealing for ion-implanted SiC at 1650 ℃ for 30 min was conducted to electrically activate the implanted P⁺ ions. Ni contacts to the P⁺-implanted 4H-SiC layers were examined by transmission line model and Hall measurements fabricated on P-implanted (0001). The results indicated that a high-quality ohmic contact and specific contact resistivity of 1.30 × 10^-6 Ω·cm² was obtained for the P⁺-implanted 4H-SiC layers. The ρ_C values of the Ni-based implanted layers decreased with increasing P doping concentrations, and a weaker temperature dependence was observed for different samples in the 200-500 K temperature range.

Nickel fully silicided (Ni-FUSI) gate material has been fabricated on a HfO₂ surface to form a Ni-FUSI gate/HfO₂/Si/Al (MIS) structure by using an ultra-high vacuum e-beam evaporation (EBV) method followed by a one step rapid thermal annealing (RTA) treatment. X-ray diffraction (XRD) and Raman spectroscopy were used to reveal the microstructures and electrical properties of the MIS structure. Results show that a one step post RTA treatment is enough to promote the full reaction of nickel silicide, compared with multiple RTA treatments. Furthermore, the HfO₂ gate dielectric film is sensitive to heat treatment, and multiple RTA treatments can damage the electrical properties of the HfO₂ film rather than improve them. By optimization of the sample fabrication technique, the MIS capacitor produces good high-frequency capacitance-voltage curves with a hysteresis of 30 mV, a work function of about 5.44-5.53 eV and leakage current density of only 1.45 × 10^-8 A/cm² at -1 V gate bias.