We present both theoretical and experimental investigation on significantly enhanced transmission through (Ag/Au) double-layered metallic aperture arrays with sub-skin-depth Ag film due to the coupling role of a surface plasmon polariton at the Ag/Au interface by evanescent waves. The results indicate that the enhanced transmittance is highly dependent on the Ag film thickness. When the Ag film thickness increases, the peak transmittance firstly increases and then decreases. Moreover, other metal material properties are also discussed. The highest peak transmittance is obtained when the Ag film thickness is 4 nm. The finite-difference time-domain simulations agree well with the experimental results. This finding provides an effective way to control the enhanced transmission for double-layered metallic aperture arrays, which has potential applications in designing a high-performance plasmonic thermal emitter.

Volume optimization was performed to obtain the theoretical lattice constants by using the generalized gradient approximation (GGA). The electronic and magnetic properties of Heusler alloys Co_{2}CrZ (Z = Ga, Ge, As) were investigated by using local spin density approximation (LSDA). Amongst the systems under investigation, Co_{2}CrGe and Co_{2}CrGa give 100% spin polarization at the Fermi level (*E*_{F}). Co_{2}CrGe and Co_{2}CrGa are the most stable half-metallic ferromagnets (HMFs); their *E*_{F} lie exactly at the gap of 0.24 eV and 0.38 eV, respectively, in the spin-down channel. Even though Co_{2}CrAs gives a distinct and bigger gap as compared to Co_{2}CrGa and Co_{2}CrGe, its *E*_{F} is not located at the middle of the gap in the spin-down channel. We have also found that the total magnetic moments increase as the Z goes from Ga to As. The calculated density of states and band structures show the HMF character for Co_{2}CrGe and Co_{2}CrGa.

When a material is irradiated, it becomes more electrically conductive due to the absorption of the electromagnetic radiation. As a result, the number of free electrons and holes changes and raises its electrical conductivity. A simple but interesting phenomenon to characterise a fabricated n^{+}p photodetector in order to determine its linearity (photoresponse) and photoconductance was employed. Using the transient decay when the irradiation source is switched off, the minority carrier concentration, effective lifetime and surface recombination velocity present at the surface of the detector were measured.

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_{0.83}In_{0.17}N and narrowband GaN layers, along with high-*k* Al_{2}O_{3} as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (*V*_{t}), *I*_{on}/*I*_{off} ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, *I*_{on}, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the *I*_{off} and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

An In_{0.53}Ga_{0.47}As/AlAs resonant tunneling diode (RTD) with a high doping emitter is designed and fabricated using air bridge technology. The RTD exhibits a high peak-to-valley current ratio (PVCR) of more than 40 at room temperature, with a peak current density of 24 kA/cm^{2}. The extraction of device parameters from DC and microwave measurements is presented together with an RTD equivalent circuit. The high PVCR RTD with small intrinsic capacitance is favorable for microwave/THz applications.

A model of subthreshold characteristics for both undoped and doped double-gate (DG) MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson's equation using variable separation technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thickness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations' results and found very good agreement.

The charge transfer efficiency improvement method is introduced by optimizing the electrical potential distribution under the transfer gate along the charge transfer path. A non-uniform doped transfer transistor channel is introduced to provide an ascending electrical potential gradient in the transfer transistor channel. With the adjustments to the overlap length between the R1 region and the transfer gate, the doping dose of the R1 region, and the overlap length between the anti-punch-through (APT) implantations and transfer gate, the potential barrier and potential pocket in the connecting region of transfer transistor channel and the pinned photodiode (PPD) are reduced to improve the electrical potential connection. The simulation results show that the percentage of residual charges to total charges drops from 1/10^{4} to 1/10^{7}, and the transfer time is reduced from 500 to 110 ns. This means the charge transfer efficiency is improved.

This paper aims to obtain some "universal method and result" to quantitatively analyze the influence of contact resistance (CR) on OTFTs, which has not been reported up to now. This is partly achieved by means of the simulated method and the introduction of *R*_{c}/*R*_{ch0} (the value of CR/on state channel resistance). To do this, the OTFT formula from the Brown model is extended, and the parameter errors (carrier mobility *μ*, saturation voltage *V*_{Dsat}, etc.) caused by *R*_{c} are analyzed in detail. Then, the *R*_{c}/*R*_{ch0} test method is emphatically demonstrated, and some meaningful conclusions are drawn. Based on the conclusion, it is the first time that a "universal method" of estimating the errors caused by *R*_{c} has been put forward. Experimental results further prove that the method is correct.

To improve the full well capacity (FWC) of a small size backside illuminated (BSI) CMOS image sensor (CIS), the effect of photodiode capacitance (*C*_{PD}) on FWC is studied, and a reformed pinned photodiode (PPD) structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e- to 6390e-, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency (QE) is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.

A radio frequency (RF) receiver frontend for single-carrier ultra-wideband (SC-UWB) is presented. The front end employs direct-conversion architecture, and consists of a differential low noise amplifier (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers.The proposed LNA employs source inductively degenerated topology. First, the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target *S*_{11} is given. Then, a noise figure optimization strategy under gain and power constraints is proposed, with consideration of the integrated gate inductor, the bond-wire inductance, and its variation. The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band, and has two gain modes to obtain a higher receiver dynamic range. The mixer uses a double balanced Gilbert structure. The front end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.43 mm^{2}. In high and low gain modes, the measured maximum conversion gain are 42 dB and 22 dB, input 1 dB compression points are -40 dBm and -20 dBm, and *S*_{11} is better than -18 dB and -14.5 dB. The 3 dB IF bandwidth is more than 500 MHz. The doublesideband noise figure is 4.7 dB in high gain mode. The total power consumption is 65 mW from a 1.8 V supply.

This paper presents a single chip CMOS power amplifier with neutralization capacitors for Zigbee^{TM} system according to IEEE 802.15.4. A novel structure with digital interface is adopted, which allows the output power of a PA to be controlled by baseband signal directly, so there is no need for DAC. The neutralization capacitors will increase reverse isolation. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed power amplifier has a 13.5 dB power gain, 3.48 dBm output power and 35.1% PAE at P_{ 1dB} point. The core area is 0.73 × 0.55 mm^{2}.

A high linearity current mode multiplier/divider (CMM/D) with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature and device parameters of the fabrication process. Furthermore, no extra bias current for all input signals is required and thus power saving is realized. With proper selection of establishing the input terminal, the proposed circuit can perform as a multifunction circuit to be operated as a multiplier/divider, without changing its topology. The proposed circuit is implemented in a 0.25 μm BCD process and the chip area is 0.26 × 0.24 mm^{2}. The simulation and measurement results show that the maximum static linearity error is ±1.8% and the total harmonic distortion is 0.4% while the input current ranges from 0 to 200 μA.

This paper presents a 5th-order Chebyshev-I active RC complex filter for multi-mode multi-band global navigation satellite systems (GNSS) RF receivers. An improved passive compensation technique is used to cancel the excess phase lag of the integrators, thus ensuring the in-band flatness of the frequency response over various ambient conditions. The filter has a programmable gain from 0 to 42 dB with a 6 dB step, a tunable center frequency at either 6.4 MHz or 16 MHz, and a bandwidth from 2 to 20 MHz with less than 3% frequency uncertainty. Implemented in a 0.18 μm CMOS process, the whole filter consumes 7.8 mA from a 1.8 V supply voltage and occupies a die area of 0.4 mm^{2}.

An analysis illustrates the loop nonlinear performance in a bang-bang PLL. A third-order equivalent model is deduced to give an approximate evaluation of the loop parameters. The architecture of the proposed phase detector is composed of four master-slave DFFs and two XORs based on the current mode logic circuit. A no-load architecture is introduced in the XOR design. The oscillator is designed with an LC VCO implementation for the jitter requirement. A simple voltage-to-current converter is proposed to drive the loop filter. The loop filter design is described in detail, which is important to ensure the nonlinear loop stability. The chip is fabricated in a 0.18 μm CMOS technology. The experimental results show that it can achieve the frequency range of 2.995 to 3.35 GHz, and a phase noise of -118.38 dBc/Hz at 1 MHz offset. The frequency to voltage gain is 270 MHz/V. The chip consumes less than 81 mW with 1.8 V supply voltage, and it occupies a 0.5 mm^{2} area.

This paper presents a pixel circuit with reduced switching leakage for OLED microdisplays. A self-referenced feedback loop is designed to track the node voltages for leakage reduction during the holding period. A longer holding time using a smaller storage capacitor can be achieved using the leakage reduction technique. An experimental system based on a 60 × 80 pixel matrix is fabricated in a 0.35-μm CMOS process. The area of the pixel circuit is only 15 × 15 μm^{2}. According to the measured results, the pixel circuit achieves a holding time of longer than 500 ms and the system exhibits a satisfied accuracy and linearity within a pixel current range from 100 pA to 3 nA.

A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF (power factor) with lower total harmonic distortion, and a faster dynamic response with the change of the input voltage or load current. For a certain system, based on the current system state parameters, the prediction algorithm can estimate the track of the output voltage and the inductor current at the next switching cycle and get a set of optimized control sequences to perfectly track the trajectory of input voltage. The proposed prediction algorithm is verified at different conditions, and computer simulation and experimental results under multi-situations confirm the effectiveness of the prediction algorithm. Under the circumstances that the input voltage is in the range of 90-265 V and the load current in the range of 20%-100%, the PF value is larger than 0.998. The startup and the recovery times respectively are about 0.1 s and 0.02 s without overshoot. The experimental results also verify the validity of the proposed method.

The problem of yield estimation merely from performance test data of qualified semiconductor devices is studied. An empirical formula is presented to calculate the yield directly by the sample mean and standard deviation of singly truncated normal samples based on the theoretical relation between process capability indices and the yield. Firstly, we compare four commonly used normality tests under different conditions, and simulation results show that the Shapiro-Wilk test is the most powerful test in recognizing singly truncated normal samples. Secondly, the maximum likelihood estimation method and the empirical formula are compared by Monte Carlo simulation. The results show that the simple empirical formulas can achieve almost the same accuracy as the maximum likelihood estimation method but with a much lower amount of calculations when estimating yield from singly truncated normal samples. In addition, the empirical formula can also be used for doubly truncated normal samples when some specific conditions are met. Practical examples of yield estimation from academic and IC test data are given to verify the effectiveness of the proposed method.

When the voltage of an analog input signal is equal to the supply voltage, it is difficult for a conventional successive approximation ADC to correctly convert the analog signal into digital signal. This paper introduces an improved successive approximation ADC, which can convert the rail-to-rail input range and reduce sampling time through a track-and-hold circuit. Comparator offset cancellation and capacitor self-calibration techniques are used in this ADC. Measurement results show that the peak SNDR of this ADC reaches 72 dB and the signal effective bandwidth is up to 1.25 MHz. It consumes 1 mW in the test, and the figure of merit is 123 fJ/conversion-step.

A low power process/temperature variation-tolerant CMOS received signal strength indicator (RSSI) and limiter amplifier are designed using SMIC 0.13 μm CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration. The RSSI has a dynamic range of more than 60 dB, and the RSSI linearity error is within ±0.5 dB for an input power from -65 to -8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature independence and robustness against process variation characteristics. The RSSI with an integrated AGC loop draws 1.5 mA (*I* and *Q* paths) from a 1.2 V single supply.

A CMOS low-noise amplifier (LNA) operating at 31.7 GHz with a low input return loss (*S*_{11}) and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to generate more than one *S*_{11} dip below -10 dB level. The principle of the matching circuit is analyzed and the critical factors with significant effect on the input impedance (*Z*_{in}) are determined. The relationship between the input impedance and the load configuration is explored in depth, which is seldom concentrated upon previously. In addition, the noise of the input stage is modeled using a cascading matrix instead of conventional noise theory. In this way *Z*_{in} and the noise figure can be calculated using one uniform formula. The linearity analysis is also performed in this paper. Finally, an LNA was designed for demonstration purposes. The measurement results show that the proposed LNA achieves a maximum power gain of 9.7 dB and an input return loss of < -10 dB from 29 GHz to an elevated frequency limited by the measuring range. The measured input-referred compression point and the third order inter-modulation point are -7.8 and 5.8 dBm, respectively. The LNA is fabricated in a 90-nm RF CMOS process and occupies an area of 755 × 670 μm^{2} including pads. The whole circuit dissipates a DC power of 24 mW from one 1.3-V supply.