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Volume 26, Issue 4, Apr 2005


  • Temperature Dependent Raman Scattering of Phonon Modes and Defect Modes in GaN and p-Type GaN Films

    Wang Ruimin, Chen Guangde,Lin J Y,and Jang H X

    Chin. J. Semicond.  2005, 26(4): 635

    Abstract PDF

    Raman spectra of undoped GaN and Mg-doped GaN films grown by metal-organic chemical-vapor deposition on sapphire are investigated between 78 and 573K.A peak at 247cm-1 is observed in both Raman spectra of GaN and Mg-doped GaN.It is suggested that the defect-induced scattering is origin of the mode.The electronic Raman scattering mechanism and Mgrelated local vibrational mode are excluded.Furthermore,the differences of E2 and A1(LO) modes in two samples are also discussed.The stress relaxation is observed in Mg-doped GaN.

  • Growth of Strained Si1-xGex Layer by UV/UHV/CVD

    Hu Huiyong, Zhang Heming, Dai Xianying, Li Kaicheng, Wang Wei, Zhu Yonggang, Wang Shunxiang, Cui Xiaoying, and Wang Xiyuan

    Chin. J. Semicond.  2005, 26(4): 641

    Abstract PDF

    Strained Si1-xGex and Si materials are successfully grown on Si substrate by ultraviolet light chemical vapor deposition under ultrahigh vacuum at a low substrate temperature of 450℃ and 480℃,respectively.At such low temperature,autodoping effects from the substrate and interdiffusion effects at each interface could be suppressed efficiently.The strained Si1-xGex and multilayer Si1-xGex /Si structures are examined by X-ray diffraction,SMIS,etc.,and it is found that the materials have good crystallinity and the rising and falling edges are steep.The technique has a capability of growing highquality Si1-xGex /Si strained layers.

  • Twinning in Low-Temperature MOCVD Grown GaN on (001) GaAs Substrate

    Shen Xiaoming, Wang Yutian, Wang Jianfeng, Liu Jianping, Zhang Jicai, Guo Liping, Jia Quanjie, Jiang Xiaoming, Hu Zhengfei, Y

    Chin. J. Semicond.  2005, 26(4): 645

    Abstract PDF

    GaN buffer layers (thickness ~60nm) grown on GaAs(001) by low-temperature MOCVD are investigated by X-ray diffraction pole figure measurements using synchrotron radiation in order to understand the heteroepitaxial growth features of GaN on GaAs(001) substrates.In addition to the epitaxially aligned crystallites,their corresponding twins of the first and the second order are found in the Xray diffraction pole figures.Moreover,{111} φ scans with χ at 55°reveal the abnormal distribution of Bragg diffractions.The extra intensity maxima in the pole figures shows that the process of twinning plays a dominating role during the growth process.It is suggested that the polarity of {111} facets emerged on (001) surface will affect the growth twin nucleation at the initial stages of GaN growth on GaAs(001) substrates.It is proposed that twinning is prone to occurring on {111}B,Nterminated facets.

  • Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

    Zhong Xinghua, Wu Junfeng, Yang Jianjun, and Xu Qiuxia

    Chin. J. Semicond.  2005, 26(4): 651

    Abstract PDF

    Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm= N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.

  • Off-State Breakdown Characteristics of Body-Tied Partial-Depleted SOI nMOS Devices

    Wu Junfeng, Zhong Xinghua, Li Duoli, Kang Xiaohui, Shao Hongxu, Yang Jianjun, Hai Chaohe, and Han Zhengsheng

    Chin. J. Semicond.  2005, 26(4): 656

    Abstract PDF

    Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.

  • 10Gb/s EML Module Based on Identical Epitaxial Layer Scheme

    Sun Changzheng, Xiong Bing, Wang Jian, Cai Pengfei, Tian Jianbo, Luo Yi, Liu Yu, Xie Liang, Zhang Jiabao,and Zhu Ninghua

    Chin. J. Semicond.  2005, 26(4): 662

    Abstract PDF

    A 10Gb/s transmitter module containing an electroabsorption modulator monolithically integrated with a distributed feedback (DFB) semiconductor laser is fabricated using the identical epitaxial layer scheme.Gain-coupling mechanism is employed to improve the single mode yield of the DFB laser,while inductively coupled plasma dry etching technique is utilized to reduce the modulator capacitance.The integrated device exhibits a threshold current as low as 12mA and an extinction ratio over 15dB at -2V bias.The small signal modulation bandwidth is measured to be over 10GHz.The transmission experiment at 10Gb/s indicates a power penalty less than 1dB at a bit-error-rate of 1e-12 after transmission through 35km single mode fiber.

  • Compact Threshold Voltage Model for FinFETs

    Zhang Dawei, Tian Lilin,and Yu Zhiping

    Chin. J. Semicond.  2005, 26(4): 667

    Abstract PDF

    A 2D analytical electrostatics analysis for the cross-section of a FinFET (or tri-gate MOSFET) is performed to calculate the threshold voltage.The analysis results in a modified gate capacitance with a coefficient H introduced to model the effect of trigates and its asymptotic behavior in 2D is that for double-gate MOSFET.The potential profile obtained analytically at the cross-section agrees well with numerical simulations.A compact threshold voltage model for FinFET,comprising quantum mechanical effects,is then proposed.It is concluded that both gate capacitance and threshold voltage will increase with a decreased height,or a decreased gate-oxide thickness of the top gate,which is a trend in FinFET design.

  • Elevated Source/Drain Engineering by Novel Technology for FullyDepleted SOI CMOS Devices and Circuits

    Lian, Jun, and, Hai, Chaohe

    Chin. J. Semicond.  2005, 26(4): 672

    Abstract PDF

    0.35μm thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.

  • Bandwidth Design for CMOS Monolithic Photoreceiver

    Nian Hua, Mao Luhong, Li Wei,Chen Hongda,and Jia Jiuchun

    Chin. J. Semicond.  2005, 26(4): 677

    Abstract PDF

    A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth design method of a monolithic photoreceiver is presented.An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail.A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0.6μm CMOS process and the test result is given.

  • Improving Detectability of Resistive Shorts in FPGA Interconnects

    Gao Haixia, Dong Gang,and Yang Yintang

    Chin. J. Semicond.  2005, 26(4): 683

    Abstract PDF

    The behavior of resistive short defects in FPGA interconnects is investigated through simulation and theoretical analysis.The results show that these defects result in timing failures and even Boolean faults for small defect resistance values.The best detection situations for large resistance defect happen when the path under test makes a v-to-v′ transition and another path causing short faults remains at value v.Small defects can be detected easily through static analysis.Under the best test situations,the effects of supply voltage and temperature on test results are evaluated.The results verify that lower voltage helps to improve detectability.If short material has positive temperature coefficient,low temperature is better;otherwise,high temperature is better.

  • A Signal-Flow Driven Automatic Physical Synthesis Methodology for Analog Circuits

    Long Di, Hong Xianlong, and Dong Sheqin

    Chin. J. Semicond.  2005, 26(4): 689

    Abstract PDF

    This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signalflow,complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement,and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.

  • Al含量对GaN/AlxGa1-xN量子点中激子态的影响

    戴宪起, 黄凤珍, 郑冬梅

    Chin. J. Semicond.  2005, 26(4): 697

    Abstract PDF


  • 稀土钕离子对立方晶型FeS2结构及光性能的影响

    徐金宝, 郑毓峰, 李锦, 孙言飞, 吴荣

    Chin. J. Semicond.  2005, 26(4): 702

    Abstract PDF


  • GaAs图形衬底上InAs量子点生长停顿的动力学蒙特卡罗模拟

    何为, 郝智彪, 罗毅

    Chin. J. Semicond.  2005, 26(4): 707

    Abstract PDF


  • In掺杂对ZnO薄膜结构及光学特性的影响

    朋兴平, 王印月, 方泽波, 杨映虎

    Chin. J. Semicond.  2005, 26(4): 711

    Abstract PDF


  • 氩氧气氛下沉积的CdTe薄膜及太阳电池的性质

    冯良桓, 张静全, 蔡伟, 黎兵, 蔡亚平, 武莉莉, 李卫, 郑家贵, 蔡道林

    Chin. J. Semicond.  2005, 26(4): 716

    Abstract PDF

    研究了在氩氧气氛下近空间升华沉积CdTe的技术.发展了在表面十分平整的玻璃衬底上沉积优质CdTe薄膜的方法,对比了在玻璃衬底和CdS薄膜上CdTe薄膜的结构特征.通过研究氧分压对CdTe薄膜择优取向的影响,证实了在恰当的近空间升华沉积过程中,两种衬底上的CdTe薄膜具有相同的结构.研究了玻璃衬底上CdTe薄膜的电学与光学性质,观察了后处理对上述薄膜性质的影响,并研制出了效率达1338%的小面积CdTe 薄膜太阳电池.

  • 溶胶-凝胶提拉法制备MgxNi1-xO薄膜与表征

    何作鹏, 季振国, 杜娟, 王玮, 范镓, 叶志镇

    Chin. J. Semicond.  2005, 26(4): 721

    Abstract PDF


  • GaN生长速率的研究

    金瑞琴, 赵德刚, 刘建平, 张纪才, 杨辉

    Chin. J. Semicond.  2005, 26(4): 726

    Abstract PDF


  • N-Al共掺ZnO薄膜的p型传导特性

    吕建国, 叶志镇, 诸葛飞, 曾昱嘉, 赵炳辉, 朱丽萍

    Chin. J. Semicond.  2005, 26(4): 730

    Abstract PDF


  • MOCVD生长GaN材料的模拟

    郭文平, 邵嘉平, 罗毅, 孙长征, 郝智彪, 韩彦军

    Chin. J. Semicond.  2005, 26(4): 735

    Abstract PDF


  • Al2O3陶瓷上金刚石膜生长工艺优化及α粒子响应

    楼燕燕, 王林军, 张明龙, 顾蓓蓓, 苏青峰, 夏义本燕, 夏义本

    Chin. J. Semicond.  2005, 26(4): 740

    Abstract PDF

    采用微波等离子体化学气相沉积(MPCVD)法在氧化铝陶瓷衬底上沉积金刚石膜,并制作梳状电极的α粒子探测器.通过优化薄膜生长条件,发现酒精浓度为0.8%、沉积温度为850℃时,金刚石薄膜的介电常数最接近单晶金刚石膜,X射线衍射、喇曼光谱及扫描电子显微镜测试表明金刚石膜的质量较好.探测器的I-V测试结果表明暗电流在1e-8~1e-7A之间,α粒子(241Am 5.5MeV)辐照下电流为1e-5~1e-4A.

  • (p)nc-Si∶H/(n)c-Si异质结变容二极管

    韦文生, 王天民, 张春熹, 李国华, 卢励吾

    Chin. J. Semicond.  2005, 26(4): 745

    Abstract PDF


  • 基于标准CMOS工艺的扇形磁敏晶体管及其模型

    姚韵若, 朱大中

    Chin. J. Semicond.  2005, 26(4): 751

    Abstract PDF

    提出一种基于0.6μm n阱标准CMOS工艺的扇形分裂漏磁敏晶体管,给出了器件相对灵敏度的数学模型.模型重点在于研究扇形分裂漏磁敏晶体管几何参数对相对灵敏度的影响.通过计算机数值积分计算和实验测试结果修正完善了器件的数学模型.测试结果表明:研制的器件最大相对灵敏度为3.77%/T,扇形结构有利于提高分裂漏磁敏晶体管的相对灵敏度.

  • 高温AlGaInP/GaAs双异质结双极晶体管

    刘文超, 夏冠群, 李冰寒, 黄文奎

    Chin. J. Semicond.  2005, 26(4): 756

    Abstract PDF

    利用Mo/W/Ti/Au难熔金属作为发射极欧姆接触设计并制作了一种用于功率放大器的新结构AlGaInP/GaAs双异质结双极晶体管(DHBT),分析了与传统AuGeNi作为接触电极的AlGaInP/GaAs DHBT的直流特性差异.研究结果表明,利用难熔金属作为欧姆接触电极的DHBT器件具有较好的高温特性,并进一步分析了其具有良好高温特性的机理.

  • 一种快速精确的GaAs MESFET寄生参数提取方法

    刘桂云, 张义门, 张玉明

    Chin. J. Semicond.  2005, 26(4): 760

    Abstract PDF

    提出了一种快速精确地提取GaAs MESFET寄生参数方法.这种方法以两组S参数为基础,应用解析表达式直接确定GaAs MESFET的九个寄生参数.该方法适用范围广.以一个0.3μm×280μm商用器件的一组寄生参数为基础,对该方法进行了验证.

  • SOI基双级RESURF二维解析模型

    郭宇锋, 方健, 张波, 李泽宏, 李肇基

    Chin. J. Semicond.  2005, 26(4): 764

    Abstract PDF

    提出了SOI基双级RESURF二维解析模型.基于二维Poisson方程,获得了表面电势和电场分布解析表达式,给出了SOI的双级和单级RESURF条件统一判据,得到RESURF浓度优化区(DOR,doping optimal region),研究表明该判据和DOR还可用于其他单层或双层漂移区结构.根据此模型,对双级RESURF结构的降场机理和击穿特性进行了研究,并利用二维器件仿真器MEDICI进行了数值仿真.以此为指导成功研制了耐压为560V和720V的双级RESURF高压SOI LDMOS.解析解、数值解和实验结果吻合得较好.

  • 基于PEEC方法的片内螺旋电感建模

    李富华, 赵吉祥, 李征帆

    Chin. J. Semicond.  2005, 26(4): 770

    Abstract PDF


  • 一种适用于射频电子标签的低电压低功耗振荡器

    韩益锋, 李强, 闵昊, 谢文录

    Chin. J. Semicond.  2005, 26(4): 775

    Abstract PDF

    提出了一种适合射频电子标签应用的振荡器设计方法.针对低电压低功耗的要求,选择了比较简单的振荡器结构,通过调节电流的方法来调节振荡器的输出频率.输出电流与电源无关的偏置电路设计保证了振荡器输出频率的稳定,低功耗的二进制权电流电路提供了很小的寄生参数、较高的电流精度和很小的芯片面积.芯片在Chartered 0.35μm CMOS工艺流片,电源电压为1.2~2V,环形振荡器消耗的平均电流约为6.5μA.

  • 数字射频存储器用DAC静态参数的表征与测试

    张有涛, 夏冠群, 李拂晓, 高建峰, 杨乃彬涛, 杨乃彬

    Chin. J. Semicond.  2005, 26(4): 781

    Abstract PDF

    分析并讨论了应用于相位体制数字射频存储器的DAC静态参数的表征方法.提出用时间非线性(TDNL和TINL)、幅度非线性(ADNL和AINL)以及相位非线性(PNL)来全面描述相位体制DAC的静态性能.仿真结果证明上述静态参数对DAC的频域性能有着显著影响,用它们表征相位体制DAC的静态性能是必要且可行的.采用上述方法对利用标准75mm GaAs MESFET全离子注入工艺流片得到的3bit相位体制DAC进行了低频静态测试,其静态参数优异,性能良好.

  • 高增益自偏S波段MMIC低噪声放大器

    王闯, 钱蓉, 孙晓玮, 顾建忠

    Chin. J. Semicond.  2005, 26(4): 786

    Abstract PDF

    报道了具有高增益自偏结构的低噪声S波段MMIC宽带低噪声高增益放大器.该放大器是采用国际先进的0.25μm PHEMT工艺技术加工而成.电路设计采用了两级级联负反馈结构,并采用电阻自偏压技术,单电源供电,使用方便,可靠性高,一致性好.MMIC芯片测试指标如下:在1.9~4.2GHz频率范围内,输入输出驻波小于2.0,线性功率增益达30dB,带内增益平坦度为±0.7dB,噪声系数小于2.7dB.芯片尺寸:1mm×2mm×0.1mm.这是国内报道的增益最高,芯片面积最小的S波段放大器.

  • 一种红外探测器专用77K工作CMOS前置放大器

    袁红辉, 袁剑辉, 王京辉

    Chin. J. Semicond.  2005, 26(4): 790

    Abstract PDF

    利用single-ended folded-cascode 结构和MOS管工作在线性区做反馈电阻,实现了一种在77K工作的高性能低功耗、低噪声前置放大器.分析了它的噪声特性,提出了减少噪声的措施.此前置放大器用1.2μm的标准CMOS工艺制造完成.经过测试,这种前置放大器在低温77K下能正常工作,反馈电阻大小为兆欧级,线性度达到了1%,等效输入噪声电流仅0.03pA/Hz,功耗小于1mW.

  • TiO2薄膜紫外探测器的光电特性

    甘勇, 刘彩霞, 张爽, 薛海林, 董玮, 张歆东, 邹博, 吴凤清, 徐宝琨, 陈维友

    Chin. J. Semicond.  2005, 26(4): 795

    Abstract PDF


  • MSM光探测器直流特性的二维分析

    于弋川, 何建军, 何赛灵, 邹勇卓

    Chin. J. Semicond.  2005, 26(4): 798

    Abstract PDF


  • 垂直腔面发射激光器的热学特性

    侯识华, 赵鼎, 孙永伟, 徐云, 谭满清, 陈良惠

    Chin. J. Semicond.  2005, 26(4): 805

    Abstract PDF


  • 基于SOA的交叉增益调制中探测光能量的数值分析

    刘超, 金潮渊, 黄永箴, 祝宁华

    Chin. J. Semicond.  2005, 26(4): 812

    Abstract PDF


  • 具有多运动自由度的新型多功能微镜

    余洪斌, 陈海清

    Chin. J. Semicond.  2005, 26(4): 816

    Abstract PDF


  • 旁栅效应对GaAs MESFET数字IC设计的影响

    张有涛, 夏冠群, 李拂晓, 高建峰, 杨乃彬

    Chin. J. Semicond.  2005, 26(4): 821

    Abstract PDF

    研究了不同旁栅电极结构、不同旁栅电极取向对旁栅阈值特性的影响,并研究了旁栅阈值的光敏特性.结果表明:半绝缘衬底中的电子和空穴陷阱是旁栅效应及其光敏特性的主要原因,Ti/Au/Ti布线金属做旁栅电极具有最好的旁栅阈值特性,Au/Ge/Ni/Au欧姆接触和Ti/Pt/Au/Ti栅金属的旁栅阈值特性相似,三者都有明显的光敏特性.上述结果为GaAs MESFET数字集成电路版图设计规则的制定提供了可靠依据.

  • 1V电源的CMOS能隙电压基准源

    盛敬刚, 陈志良, 石秉学

    Chin. J. Semicond.  2005, 26(4): 826

    Abstract PDF

    采用SMIC 0.35μm CMOS工艺实现了一种可以工作在1V电源电压下的CMOS能隙基准源.测试表明,该电路可以工作在1~2.5V电源电压下,输出的基准电压可以稳定在约0.446V.在从室温到100℃的范围内,温度系数不超过3.6e-5/K.

  • 晶片表面几何特性对键合的影响

    陈斌, 黄永清, 任晓敏

    Chin. J. Semicond.  2005, 26(4): 830

    Abstract PDF


  • 注氮工艺对SIMOX器件电特性的影响

    张国强, 刘忠立, 李宁, 范楷, 郑中山, 张恩霞, 易万兵, 陈猛, 王曦

    Chin. J. Semicond.  2005, 26(4): 835

    Abstract PDF

    研究了氮离子注入对SIMOX器件电特性的影响. 氮注入SIMOX的埋氧层并退火后,将减小前栅MOSFET/SIMOX的阈电压,提高其漏源击穿电压但对栅击穿电压影响较小.氮注入方式对SIMOX器件的I-V特性有重要影响.

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