Issue Browser

Volume 27, Issue 1, Jan 2006


  • Low-Microwave Loss Coplanar Waveguides Fabricated on High-Resistivity Silicon Substrate

    Yang Hua, Zhu Hongliang, Xie Hongyun, Zhao Lingjuan, Zhou Fan, Wang Wei

    Chin. J. Semicond.  2006, 27(1): 1

    Abstract PDF

    Three kinds of coplanar waveguides (CPWs) are designed and fabricated on different silicon substrates--common low-resistivity silicon substrate (LRS),LRS with a 3μm-thick silicon oxide interlayer, and high-resistivity silicon (HRS) substrate.The results show that the microwave loss of a CPW on LRS is too high to be used, but it can be greatly reduced by adding a thick interlayer of silicon oxide between the CPW transmission lines and the LRS.A CPW directly on HRS shows a loss lower than 2dB/cm in the range of 0~26GHz and the process is simple,so HRS is a more suitable CPW substrate.

  • Study and Fabrication of a Au/n-ZnO/p-Si Structure UV-Enhanced Phototransistor

    Guo Junfu, Xie Jiachun, Duan Li, He Guanghong, Lin Bixia, Fu Zhuxi

    Chin. J. Semicond.  2006, 27(1): 5

    Abstract PDF

    The fabrication and characterization of a Schottky-emitter heterojunction-collector UV-enhanced bipolar phototransistor (SHBT) are presented.The luminescence peak of the ZnO film is observed at 371nm in the PL spectrum.The sensitivity of the ultraviolet response from 200 to 400nm is enhanced noticeably, and the spectrum response at wavelengths longer than 400nm is also retained.The experiments show that the Au/n-ZnO/p-Si SHBT UV enhanced phototransistor enhances the sensitivity of the ultraviolet response noticeably.The UV response sensitivity at 370nm of the phototransistor is 5~10 times that of a ZnO/Si heterojunction UV enhanced photodiode.

  • Design and Fabrication of Power Si1-xGex/Si Heterojunction Bipolar Transistor for Wireless Power Amplifier Applications

    Xue Chunlai, Cheng Buwen, Yao Fei, Wang Qiming

    Chin. J. Semicond.  2006, 27(1): 9

    Abstract PDF

    A multi-finger structure power SiGe HBT device (with an emitter area of about 166μm2) is fabricated with very simple 2μm double-mesa technology.The DC current gain β is 14425.The B-C junction breakdown voltage reaches 9V with a collector doping concentration of 1×1017cm-3 and a collector thickness of 400nm.Though our data are influenced by large additional RF probe pads,the device exhibits a maximum oscillation frequency fmax of 101GHz and a cut-off frequency fT of 18GHz at a DC bias point of IC=10mA and VCE=25V.

  • An Ultra Wideband VHF CMOS LC VCO

    Ning Yanqing, Wang Zhihua, Chen Hongyi

    Chin. J. Semicond.  2006, 27(1): 14

    Abstract PDF

    This paper presents a VHF CMOS VCO.The most significant improvement on the VCO is that the cross-coupled MOSFET pairs are divided into several switchable parts so the characteristics can compensate the state change that results from the frequency tuning of the oscillator.This VCO is implemented in 0.18μm CMOS with a core area of about 550μm×700μm.The test results show that the tuning range covers 31~111MHz with a power consumption between 0.3~6.9mW and a phase noise at a 100kHz offset of about -110dBc/Hz

  • 12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer

    Ding Jingfeng, Wang Zhigong, Zhu En, Zhang Li, Wang Gui

    Chin. J. Semicond.  2006, 27(1): 19

    Abstract PDF

    A low power 12Gb/s single-stage 1∶4 demultiplexer (DEMUX) applied in SONET OC-192 is realized in TSMC’s mix-signal 0.25μm CMOS.All of the circuits are in source coupled FET logic (SCFL) to achieve as high a speed as possible and suppress common mode distortions.This DEMUX is featured for achieving single-stage demultiplexing by using a quarter-rate IQ clock.This method not only reduces the components of the DEMUX but also lowers its power dissipation.The fabricated DEMUX operates error free at 12Gb/s by 231-1 pseudorandom bit sequences in on-wafer testing.The chip size is 0.9mm×0.9mm and the power dissipation is only 210mW with a single 2.5V supply.

  • A Novel Algorithm to Extract Weighted Critical Area

    Wang Junping, Hao Yue, Zhang Huining, Zhang Xiaoju, Ren Chunli

    Chin. J. Semicond.  2006, 27(1): 24

    Abstract PDF

    Inductive fault analysis is a technique for enumerating likely bridges that is limited by the weighted critical area computation.Based on the rectangle model of a real defect and mathematical morphology,an efficient algorithm is presented to compute the weighted critical area of a layout.The algorithm avoids the need to determine which rectangles belong to a net and the merging of the critical area corresponding to a net pair.Experimental results showing the algorithm’s performance are presented.

  • Electron Injection Enhancement by Diamond-Like Carbon Film in Polymer Electroluminescence Devices

    Li Hongjian, Yan Lingling, Huang Baiyun, Yi Danqing, Hu Jin, He Yingxuan, Peng Jingcui

    Chin. J. Semicond.  2006, 27(1): 30

    Abstract PDF

    A diamond-like carbon (DLC) film is deposited as an electron injection layer between the polymer light-emitting layer(MEH-PPV) and aluminum (Al) cathode electrode in polymer electroluminescence devices (PLEDs) using a radio frequency plasma deposition system.The source material of the DLC is n-butylamine.The devices consist of indium tin oxide (ITO)/MEH-PPV/DLC/Al.Electron injection properties are investigated through I-V characteristics,and the mechanism of electron injection enhancement due to a thin DLC layer has been studied.It is found that:(1) a DLC layer thinner than 1.0nm leads to a higher turn-on voltage and decreased electroluminescent (EL) efficiency;(2) a 5.0nm DLC layer significantly enhances the electron injection and results in the lowest turn-on voltage and the highest EL efficiency;(3) DLC layer that exceeds 5.0nm results in poor device performance;and(4) EL emission can hardly be detected when the layer exceeds 10.0nm.The properties of ITO/MEH-PPV/DLC/Al and ITO/MEH-PPV/LiF/Al are investigated comparatively.

  • Simulation of a Double-Gate Dynamic Threshold Voltage Fully Depleted Silicon-on-Insulator nMOSFET

    Bi Jinshun, Wu Junfeng, Hai Chaohe

    Chin. J. Semicond.  2006, 27(1): 35

    Abstract PDF

    A novel planar DGDT FDSOI nMOSFET is presented,and the operation mechanism is discussed.The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici.The back-gate n-well is formed by implantation of phosphorus at a dosage of 3×1013cm-2 and an energy of 250keV and connected directly to a front-gate n+ polysilicon.This method is completely compatible with the conventional bulk silicon process.Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted (PD) SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.

  • Analysis and Design of a ΔΣ Modulator for Fractional-N Frequency Synthesis

    Zhang Weichao, Xu Jun, Zheng Zengyu, Ren Junyan

    Chin. J. Semicond.  2006, 27(1): 41

    Abstract PDF

    This paper presents the design considerations and implementation of a novel topology digital multi-stage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis.In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure.The circuit has been verified through Matlab simulation,ASIC implementation,and FPGA experiment,which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.

  • A 12-Channel,30Gb/s,0.18μm CMOS Front-End Amplifier for Parallel Optic-Fiber Receivers

    Li Zhiqun, Xue Zhaofeng, Wang Zhigong, Feng Jun

    Chin. J. Semicond.  2006, 27(1): 47

    Abstract PDF

    This paper presents a 12-channel,30Gb/s front-end amplifier realized in standard 0.18μm CMOS technology for parallel optic-fiber receivers.In order to overcome the problem of inadequate bandwidth caused by the large parasitical capacitor of CMOS photo-detectors,a regulated-cascode structure and noise optimization are used in the design of the transimpedance amplifier.The experimental results indicate that,with a parasitical capacitance of 2pF,a single channel is able to work at bite rates of up to 2.5Gb/s,and a clear eye diagram is obtained with a 0.8mVpp input.Furthermore,an isolation structure combined with a p+ guard-ring (PGR),an n+ guard-ring (NGR),and a deep-n-well (DNW) for parallel amplifier is also presented.Taking this combined structure,the crosstalk and the substrate noise coupling have been effectively reduced.Compared with the isolation of PGR or PGR+NGR,the measured results show that the isolation degree of this structure is improved by 29.2 and 8.1dB at 1GHz,and by 8.1 and 2.5dB at 2GHz,respectively.With a 1.8V supply,each channel of the front-end amplifier consumes a DC power of 85mW,and the total power consumption of 12 channels is about 1W

  • Elmore Delay Estimation of Two Adjacent Coupling Interconnects

    Dong Gang, Yang Yintang, Li Yuejin

    Chin. J. Semicond.  2006, 27(1): 54

    Abstract PDF

    An approach for analyzing coupling RC interconnect delay based on "effective capacitance" is presented.We compare this new method to the traditional method,which uses Miller capacitance.The results show that the new method not only improves the accuracy but also reflects the delay dependence on rise time.The method has the same complexity as the Elmore delay model and can be used in performance-driven routing optimization


  • Calculation of Microband Breadth of GaAs/AlGaAs Superlattice

    He Lijun, Cheng Xingkui, Li Hua, Zhang Jian, Zhou Junming, Huang Qi

    Chin. J. Semicond.  2006, 27(1): 59

    Abstract PDF

    GaAs/AlGaAs superlattices are grown by molecular beam epitaxy(MBE), and their photocurrent are measured at low temperature (T=77K) .From the view of electron wave mechanics,taking into account the electron wave reflections at the interface between the well and the potential barrier layer, we discuss the electronic states above the barriers in a GaAs/AlGaAs superlattice.This paper presents a new method on calculating the breadth of the microband,and the calculated microband breadth of GaAs/AlGaAs superlattice is in good agreement with the experimental results.

  • Screening Influence on Binding Energies of Donors in Quantum Wells with Finite Barriers Under Hydrostatic Pressure

    Wen Shumin, Ban Shiliang

    Chin. J. Semicond.  2006, 27(1): 63

    Abstract PDF

    The energy levels of donors in quantum wells with finite barriers are investigated using a variational method.We consider the variations of the electron effective mass,dielectric constant,and conduction band offset between the well and barriers with hydrostatic pressure,and we take into account the screening effect on the Coulombic potential of an impurity from the 2D electron gas.Numerical calculations are performed for the binding energies of impurity states in GaAs/AlxGa1-xAs quantum well systems.The relations between the binding energies of donors and Al concentration,well width,and hydrostatic pressure are given.The difference between the cases with and without screening is discussed.The results indicate that the screening increases with pressure,resulting in a decrease in the binding energies of the impurity states.

  • Effect of Rapid Thermal Annealing Ambient on Denuded Zone and Oxygen Precipitates in a 300mm Silicon Wafer

    Feng Quanlin, Shi Xunda, Liu Bin, Liu Zuoxing, Wang Jing, Zhou Qigang

    Chin. J. Semicond.  2006, 27(1): 68

    Abstract PDF

    In a 300mm silicon wafer,a suitable denuded zone depth and a high oxygen precipitate density are necessary to get a high gettering efficiency and to improve the gate oxide integrity (GOI).In this work,Ar and an N2/NH3 mixture gas are applied as rapid thermal annealing (RTA) ambients.It is demonstrated that a high density of oxygen precipitate and a thin denuded zone are obtained in the N2/NH3 mixture ambient,while a low density of oxygen precipitate and a thick denuded zone are observed in the wafer annealed in the Ar ambient.The effect of the RTA ambient and annealing time on the denuded zone and oxygen precipitates is discussed.

  • Effect of Pre-Rapid Thermal Annealing on FPDs and Denuded Zones in Large-Diameter CZ-Si

    Zhang Jianqiang, Liu Caichi, Zhou Qigang, Wang Jing, Hao Qiuyan, Sun Shilong, Zhao Liwei, Teng Xiaoyun

    Chin. J. Semicond.  2006, 27(1): 73

    Abstract PDF

    The relationship between flow pattern defects (FPDs) and the magic denuded zone (MDZ) in CZ silicon wafers is investigated after pre-RTA in different atmospheres.After pre-RTA at high temperature,the wafers are annealed at 800℃(4h)+1000℃(16h) to form an MDZ.After annealing in an Ar or N2/O2(9%) mixed atmosphere,the wafers exhibit low FPD density,high oxygen precipitation density,and a wide denuded zone.In the case of an N2/O2 mixed atmosphere,the FPD density and the oxygen precipitation density decrease with the increase of O2 content.Therefore the FPD density and oxygen precipitation density can be controlled by adjusting the N2/O2 ratio in the atmosphere

  • Effect of H2 on Low Temperature Selective Growth of Si1-xGex by UHV/CVD

    Zhao Xing, Ye Zhizhen, Wu Guibin, Liu Guojun, Zhao Binghui, Tang Jiuyao

    Chin. J. Semicond.  2006, 27(1): 78

    Abstract PDF

    The selective epitaxial growth (SEG) of Si1-xGex is successfully achieved at a very low temperature by UHV/CVD.The effect and associated mechanism of H2 on the SEG are also investigated.The selective epitaxial growth of Si1-xGex is performed on Si wafers with 6mm×6mm patterns using SiH4 and GeH4 as gas sources.First,Ge sources without H2(pure GeH4) and with H2 (90% H2 diluted GeH4) are used in the growth process.According to the SEM images of the SiO2 substrate under two different conditions,H2 is vital in SEG.Then,using 90% H2 diluted GeH4 as the Ge source with varying the flow ratio of SiH4 and GeH4 (90% H2) in order to control the H2 partial pressure,the optimal flow ratio is obtained.The morphology of the samples,which are epitaxially grown for 40min at different flow ratios,are investigated by SEM.Finally,the SEM images are compared to those of samples grown under different gas sources, and the mechanism responsible for the effect of H2 in the SEG of Si1-xGex is analyzed.

  • Influence of Annealing Temperature on Luminescence of β-FeSi2 Particles Embedded in Silicon

    Li Cheng, Lai Hongkai, Chen Songyan

    Chin. J. Semicond.  2006, 27(1): 82

    Abstract PDF

    The influence of annealing temperature on the luminescence and electrical properties of β-FeSi2 particles embedded in silicon is investigated.The experimental results indicate that annealing at 900℃ improves the particles’ crystal quality,but dislocations are introduced in the silicon due to the thermal and lattice mismatches,which broaden the photoluminescence spectrum and enlarge the leakage current.Stronger room temperature electroluminescence is obtained from the sample annealed at 800℃.

  • Influence of Oxidation on Residual Strain Relaxation of SiGe Film Grown on SOI Substrate

    Jin Bo, Wang Xi, Chen Jing, Zhang Feng, Cheng Xinli, Chen Zhijun

    Chin. J. Semicond.  2006, 27(1): 86

    Abstract PDF

    The influence of oxidation on the relaxation of residual strain in SiGe films epitaxially grown on SOI substrate are studied.These samples are oxidized with different technologies for the purpose of studying the influence of different oxidation processes on the relaxation of residual strain in SiGe films.Oxidation driven Ge atoms diffuse from the SiGe film to the top silicon layer.There is residual strain in SiGe film relaxation processes with the diffusion of Ge atoms.We contrast the dislocation distribution in the SiGe film and the top silicon layer:there is a strain transfer process between the SiGe film and the top silicon layer during oxidation.

  • Growth of Phosphorus-Doped p-Type ZnO Thin Films by MOCVD

    Zhou Xincui, Ye Zhizhen, Chen Fugang, Xu Weizhong, Miao Yan, Huang Jingyun, Lü Jianguo, Zhu Liping, Zhao Binghui

    Chin. J. Semicond.  2006, 27(1): 91

    Abstract PDF

    Phosphorus-doped p-type ZnO thin films are prepared on glass substrates by metalorganic chemical vapor deposition.DEZn,O2,and P2O5 powder are used as reactant and dopant sources.The p-type ZnO films are grown at a temperature between 400 and 450℃.The best p-type sample has a low resistivity of 4.64Ω·cm,a hole concentration of 1.61×1018cm-3,and a Hall mobility of 0.838cm2/(V·s) at room temperature.A strong emission peak at 3.354eV corresponding to neutral acceptor bound excitons is observed at 77K in the photoluminescence spectra,further verifying the p-type characteristics of the films

  • Photoresponse of ZnO Single Crystal Film

    Li Ying, Feng Shiwei, Yang Ji, Zhang Yuezong, Xie Xuesong, Lü Changzhi, Lu Yicheng

    Chin. J. Semicond.  2006, 27(1): 96

    Abstract PDF

    The Ohmic contact and photoresponse of a ZnO single crystal film produced by MOCVD are investigated.The electrical and photoresponsive changes in the ZnO film due to the RF sputter deposition of SiO2 (antireflective coating) are also discussed.A nonalloyed Al/Au metallization scheme forms a good Ohmic contact on the n-type ZnO.RF sputter deposition of SiO2 induces defects which behave as carrier traps and prolongs response time.The photoresponse of the ZnO epitaxial film deteriorates with time.

  • Ray Tracing Simulation of InGaN/GaN Light-Emitting Diodes with Parabolic Substrates

    Xia Changsheng, Li Zhifeng, Wang Chong, Chen Xiaoshuang, Lu Wei

    Chin. J. Semicond.  2006, 27(1): 100

    Abstract PDF

    A new kind of InGaN/GaN light-emitting diode with a parabolic substrate is proposed with special attention to the photon emitted into the substrate.Ray trace,the angular distribution of emitted power,and the external quantum efficiency for plane and parabolic InGaN/GaN light-emitting diodes are simulated and calculated preliminarily.The results show that the parabolic InGaN/GaN light-emitting diode can emit better quasi-parallel light than that with a plane substrate and can effectively utilize the photon emitted into the substrate,resulting in an increase in the emitted power in the forward direction by 12.6 times and an improvement in the external quantum efficiency by 1.22 times.

  • Accurate Measurement of Forward Electrical Characteristics in Laser Diodes

    Cong Hongxia, Feng Liefeng, Wang Jun, Zhu Chuanyun, Wang Cunda, Xie Xuesong, Lü Changzhi

    Chin. J. Semicond.  2006, 27(1): 105

    Abstract PDF

    The dependence of series resistance,ideality factor,junction voltage,and capacitance on the applied voltage or current of laser diodes (LDs) is determined by examining forward AC behavior together with I-V characteristics.The experimental results,for the first time, demonstrate that the junction voltage saturation occurs after the junction voltage, series resistance, ideality factor,and junction capacitance simultaneously show step offsets near the threshold.A negative capacitance effect in LDs is also observed under larger voltages or lower frequencies.

  • Effects of Bandgap Narrowing Induced by heavy Doping in Abrupt HBTs on Their Currents

    Zhou Shouli, Cui Hailin, Huang Yongqing, Ren Xiaomin

    Chin. J. Semicond.  2006, 27(1): 110

    Abstract PDF

    The bandgap narrowing is distributed between the conduction and valence bands,according to the Jain-Roulston model,and its effects on the currents of abrupt AlGaAs/GaAs HBTs including the self-heating effect,are analyzed.By comparison experimental results with the results of other distribution models of BGN commonly used in commercial software,it can be concluded that using an accurate dopant-dependent BGN distribution model between bands is very important.

  • A Novel SOI High Voltage Device Structure with a Partial Locating Charge Trench

    Luo Xiaorong, Zhang Bo, Li Zhaoji, Tang Xinwei

    Chin. J. Semicond.  2006, 27(1): 115

    Abstract PDF

    A novel high voltage device structure--partial locating charge trench SOI (PTSOI) is proposed.Interface charges changing with the drain voltage are introduced in the trench.The charges make the vertical electric field of the buried oxide increase from about 3ESi, C to the critical breakdown electric field of SiO2.In addition,the depletion layer spreads into the substrate through the silicon window.Hence the breakdown voltage is enhanced.The self-heating effect of SOI devices is alleviated as a result of the silicon window.The breakdown characteristics and thermal characteristics are researched by a 2D device simulator.A breakdown voltage greater than 700V can be obtained for the PTSOI device with a 2μm thick Si layer and 1μm buried oxide.The maximum temperature of the PTSOI device is 6K and 25K lower than that of TSOIs with 1μm and 3μm thick buried oxides,respectively

  • Total Dose Effect of Large-Scale Integrated Circuit Floating Gate ROM Devices

    He Baoping, Zhou Heqin, Guo Hongxia, Zhou Hui, Luo Yinhong, Yao Zhibin, Zhang Fengqi

    Chin. J. Semicond.  2006, 27(1): 121

    Abstract PDF

    A method for testing total dose effects is presented for VLSI.The consumption current of the device is measured.Meanwhile,the function parameters of the device and circuit are also measured. The relations between data errors,consumption current and total radiation dose are analyzed.Ionizing radiation experiments are performed on floating gate ROM devices by using 60Co γ-rays as prescribed by this test method.The experimental aim is to examine the radiation response at various dose rates.The parameters and function failure of the devices as function of dose rate are studied.By extrapolation,we predict the failure time of a floating gate ROM device in a space radiation environment

  • Design and Implementation of a Novel Chip for Full Digital Three-Phase SPWM Signal Generation

    Gao Yong, Yu Ningmei, Chen Lijie, Tang Shanqiang

    Chin. J. Semicond.  2006, 27(1): 126

    Abstract PDF

    A novel full digital three-phase sinusoidal pulse width modulation (SPWM) signal generation chip is presented for power electronics.A modified direct digital frequency synthesis(DDS),pipelined structure,and time-sharing ROM are adopted in the chip,for saving chip area and ensuring high performance and speed.The system clock is set at 24MHz,the output signals defined in 65536 equal steps cover a bandwidth from DC to 4kHz,and the multifunction is designed for control.The chip is fabricated by using charted 0.35μm COMS technology.The test results show that the chip achieves the design specification

  • A Novel Self-Bias High-Voltage Device Structure for Start-Up Circuit of Off-Line Switching Model Power Supply IC

    Liu Jizhi, Chen Xingbi, Li Ding

    Chin. J. Semicond.  2006, 27(1): 132

    Abstract PDF

    A novel self-bias high-voltage device structure for the start-up circuit of an off-line switching model power supply IC is described.The structure and properties of the device,made by RESURF technology,are analyzed and simulated.Using this novel start-up circuit structure for the off-line switching model power supply IC can save the cell area,reduce the power consumption of the circuit,and easily control and supply the larger output voltage.

  • A Low-Jitter and Low-Power Frequency Synthesizer Applied to 1000Base-T Ethernet

    Lu Ping, Wang Yan, Zheng Zengyu, Ren Junyan

    Chin. J. Semicond.  2006, 27(1): 137

    Abstract PDF

    This paper adopts a high-speed TSPC frequency and phase detector,a typical charge pump,and cross-coupled differential delay cells to realized a good frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Mbps modes.This frequency synthesizer can not only meet the requirements of the transmitter for very precise rising (falling) edge time control but also offer much finer time-interval clocks than VCO natural multi-phase outputs,thus greatly saving area and power.The data show that the σ of the voltage control oscillator jittercycle-cycle is only 11ps while that of the reference clock jittercycle-cycle is 16ps.This indicates that the frequency synthesizer works well for transmitters and receivers.The circuit is designed with SMIC 0.18μm standard CMOS technology,the power supply is 1.8V,and the power is lower than 4mW

  • A Teeterboard Pattern MEMS Permanent Magnet Bistable Structure Supported by Torsion and Cantilever Beam

    Jiang Zheng, Ding Guifu, Wang Yan, Zhang Dongmei, Wang Zhiming, Feng Jianzhi

    Chin. J. Semicond.  2006, 27(1): 143

    Abstract PDF

    After feasibility analysis and parameter optimization,a teeterboard pattern MEMS permanent magnet bistable structure supported by a torsion and cantilever beam is fabricated with sacrificial layer technology of non-silicon surface micro fabrication.The size of the bistable structure is 1.9mm×1.6mm×0.03mm.The stable states can be maintained without power consumption by a permanent magnet force,and the two states are switched by applying a perpendicular driving force on one side of the anchors to achieve a perpendicular displacement of 30μm.The driving moment can be adjusted by controlling the sizes of the permanent magnet,torsion,and the cantilever beam.With electromagnetic,electrothermal,and electrostatic micro actuators,this bistable structure can be applied to permanent magnet bistable MEMS relay.

  • A MEMS Based Focus Plane Array for Infrared Imaging

    Li Chaobo, Jiao Binbin, Shi Shali, Ye Tianchun, Chen Dapeng, Zhang Qingchuan, Guo Zheying, Dong Fengliang, Wu Xiaoping

    Chin. J. Semicond.  2006, 27(1): 150

    Abstract PDF

    Based on the opto-mechanical effect and MEMS technology,a novel substrate-free FPA with a thermally isolated structure for uncooled infrared imaging is developed.Alternately evaporating Au on a SiNx cantilever is used for thermal isolation.A human’s thermal image is obtained successfully using the infrared imaging system composed of the FPA and optical detection system.Experimental results show that the realization of thermal isolation in the substrate-free FPA increases the temperature of the deflecting leg effectively,while the NETD is about 200mK.

  • Effects of Die Bonding on MEMS Characteristics:Cell Library

    Song Jing, Huang Qing’an, Tang Jieying

    Chin. J. Semicond.  2006, 27(1): 156

    Abstract PDF

    Thermal mismatch induced by the die bonding structure greatly affects the reliability and performance of MEMS devices.A cell library method,as an alternative conventional FEM simulation,is introduced here to simplify the package-device co-design and the parametric study of MEMS components.Effects of the die bonding process on the pull-in voltage of a doubly supported micro-beam are predicted using this method, and the results are in good agreement with the FEM calculations.This method has the advantages of simplicity and accuracy and application to the co-design of the overall system of the packaged MEMS devices.

  • Effect of Load Stiffness on the Output of Thermal Microactuators

    Gao Jianzhong, Zhao Yulong, Jiang Zhuangde, Yang Jing

    Chin. J. Semicond.  2006, 27(1): 162

    Abstract PDF

    Due to the fact that micro-electromechanical systems (MEMS) based thermal microactuators and displacement amplification mechanisms are all compatible,the stiffness match between these two components is important to consider to achieve adequate output in the design phase.First,the effect of load stiffness on microactuators is theoretically analyzed.The finite element method (FEM) is then used to simulate the performance of both thermal actuators and compatible amplifiers.It is shown that the stiffness ratio between microactuators and compatible transmissions significantly influences the performance of the combined mechanism.Prototypes are fabricated on an SOI substrate with deep reaction ion etching (DRIE) technology and then are tested.Experimental results coincide well with the theoretical predictions.

  • Transmission Lines Embedded in Silicon Oxide Layers on Silicon Wafers

    Sun Longjie, Yang Bo, Guo Lihui

    Chin. J. Semicond.  2006, 27(1): 168

    Abstract PDF

    Transmission lines,microstrips and coplanar waveguides,are fabricated on lossy silicon substrates embedded in CMOS Cu/SiO2 interconnect layers.The impedance,loss,and slowing factor are studied in detail as they relate to the geometric size of the transmission lines.We show that microstrips and coplanar waveguides embedded in silicon oxide can be achieved with low loss on lossy silicon wafers,providing the essential passive components for designing microwave and millimetre-wave circuits on silicon wafers.

  • Direct Tunneling Effect in SiC Schottky Contacts

    Tang Xiaoyan, Zhang Yimen, Zhang Yuming, Guo Hui, Zhang Lin

    Chin. J. Semicond.  2006, 27(1): 174

    Abstract PDF

    The direct tunneling effect in SiC Schottky contacts is simulated based on electron tunneling probabilities through a triangular barrier,which are accurately solved using the one-dimensional time-independent Schrdinger equation.The simulation results show that the proposed method has the advantages of greater accuracy and adaptability to SiC Schottky contacts in high fields over the WKB approximation.It also can seamlessly treat thermionic emission and tunneling current

  • Investigation of ICP Etching Damage of InAsP/InP Strained Multiple Quantum Wells

    Cao Meng, Wu Huizhen, Lao Yanfeng, Huang Zhanchao, Liu Cheng, Zhang Jun, Jiang Shan

    Chin. J. Semicond.  2006, 27(1): 178

    Abstract PDF

    To investigate the ICP etching damage to InAsP/InP strained multiple quantum wells,specially designed InAsP/InP strained multiple quantum wells (SMQWs) are grown using gas source molecular beam epitaxy and etched by an inductively coupled plasma.The depth of damage in the SMQW structure is about 40nm after etching for 75nm.This is determined by measuring the photo-luminescence spectra of the sample before and after etching.This result is in good agreement with the theoretical damage depth of 43.5nm by M.Rahman’s model.It is found that the defects are mainly caused by ion channeling.

  • A Modified Model for Etching a Sacrificial Layer in Bubble Structures

    Wu Changju, Ma Huilian, Jin Zhonghe, Wang Yuelin

    Chin. J. Semicond.  2006, 27(1): 183

    Abstract PDF

    A previous sacrificial layer etching model treats the diffusion coefficient D as a constant through the etching process.This model fits the experimental data well during a short initial period of the etching time,but it deviates very seriously as the etching progresses.In order to explain this phenomenon and predict the etching process accurately,a modified model is proposed that treats the diffusion coefficient of HF as a function of the solution concentration.In the modified model,a decrease in the HF concentration will cause an increase of the HF diffusion coefficient,which will partly compensate for the decrease in concentration because of the long diffusion distance. In the modified model,the diffusion coefficient is also a function of temperature.In this way,the modified model matches the experimental data very well.These results provide new insight for understanding not only the mechanism of sacrificial layer etching,but also the solution diffusion in complex structures.The observed phenomenon should be applicable to other kinds of sacrificial layer etching if they are diffusion limited.


Advanced Search >>