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Volume 27, Issue 11, Nov 2006

    LETTERS

  • 实现64级灰度显示的无源OLED驱动芯片的设计

    刘铭, 秦波, Xiao Wenyu, Zhong Huiming, Chen Liang, Liu Lifang, Jia Chen, Chen Zhiliang

    Chin. J. Semicond.  2006, 27(11): 1889

    Abstract PDF

    A mixed-signal driver chip for a 132×64-pixel passive matrix OLED panel is presented.The chip has a 64-step gray scale control using the PWM method and two-step voltage pre-charge technology to pre-charge the OLED pixels.It consists of a digital controller,SRAM for display data memory,a DC-DC voltage converter,reference current generators,a pre-charge voltage generator,64 common drivers,and 132 segment drivers.The single chip is a typical current-drive circuit.It has been implemented in a Chartered 0.35μm 18V HV (DDD) CMOS process with a die area of 10mm×2mm.Test results show that the power consumption of the whole chip and all pixels with a constant driving current of 100μA while displaying the highest gray scale is 294mW with a 12V high voltage supply and a 3V low voltage supply.

  • An All-E-Beam Lithography Process for the Patterningof 2D Photonic Crystal Waveguide Devices

    Yu Hejun, Yu Jinzhong, Chen Shaowu

    Chin. J. Semicond.  2006, 27(11): 1894

    Abstract PDF

    We present an all-e-beam lithography (EBL) process for the patterning of photonic crystal waveguides.The whole device structures are exposed in two steps.Holes constituting the photonic crystal lattice and defects are first exposed with a small exposure step size (less than 10nm).With the introduction of the additional proximity effect to compensate the original proximity effect,the shape,size,and position of the holes can be well controlled.The second step is the exposure of the access waveguides at a larger step size (about 30nm) to improve the scan speed of the EBL.The influence of write-field stitching error can be alleviated by replacing the original waveguides with tapered waveguides at the joint of adjacent write-fields.It is found experimentally that a higher exposure efficiency is achieved with a larger step size;however,a larger step size requires a higher dose.

  • PAPERS

  • Investigations of Key Technologies for 100V HVCMOS Process

    Song Limei, Li Hua, Du Huan, Xia Yang, Han Zhengsheng, Hai Chaohe

    Chin. J. Semicond.  2006, 27(11): 1900

    Abstract PDF

    A novel dual gate oxide (DGO) process is proposed to improve the performance of high voltage CMOS (HVCMOS) devices and the compatibility between thick gate oxide devices and thin gate oxide devices.An extra sidewall is added in this DGO process to round off the step formed after etching the thick gate oxide and poly-silicon.The breakdown voltages of high voltage nMOS (HVnMOS) and high voltage pMOS (HVpMOS) are 168 and -158V,respectively.Excellent performances are realized for both HVnMOS and HVpMOS devices.Experimental results demonstrate that the HVCMOS devices work safely at an operation voltage of 100V.

  • Analysis of Si/GaAs Bonding Stresses with the FiniteElement Method

    He Guorong, Yang Guohua, Zheng Wanhua, Wu Xuming, Wang Xiaodong, Cao Yulian, Wang Qing, Chen Lianghui

    Chin. J. Semicond.  2006, 27(11): 1906

    Abstract PDF

    In conjunction with ANSYS,we use the finite element method to analyze the bonding stresses of Si/GaAs.We also apply a numerical model to investigate a contour map and the distribution of normal stress,shearing stress,and peeling stress,taking into full consideration the thermal expansion coefficient as a function of temperature.Novel bonding structures are proposed for reducing the effect of thermal stress as compared with conventional structures.Calculations show the validity of this new structure.

  • Digital Coarse Tuning Loop for Wide-Band Fast-Settling Dual-Loop Frequency Synthesizers

    Liu Junhua, Liao Huailin, Yin Jun, Huang Ru, Zhang Xing

    Chin. J. Semicond.  2006, 27(11): 1911

    Abstract PDF

    A new coarse tuning loop for a wide-band dual-loop frequency synthesizer is presented.The coarse tuning structure is composed of two digital modules, including a successive approximation register and a frequency comparator with a novel structure.The frequency comparator counts the prescaler cycles within a certain reference time and compares the number with preset data to estimate the VCO frequency.The frequency comparison error is analyzed in detail.Within a given coarse tuning time,our proposed structure shows a comparison error 20 times smaller than that of other reported structures.This structure also reuses the programmable divider as a part of the coarse tuning loop so that the circuit is greatly simplified.

  • Improved Statistical Interconnect Timing Analysis Considering Scattering Effect

    Lin Saihua, Yang Huazhong, Luo Rong, Wang Hui

    Chin. J. Semicond.  2006, 27(11): 1918

    Abstract PDF

    We propose an improved statistical approach for modeling interconnect slew that takes into account the scattering effect of a nanoscale wire.We first propose a simple,closed-form scattering effect resistivity model,considering the effects of both width and thickness.Then we use this model to derive statistical expressions of the slew metrics using the SS2M model.We find that the delay and slew can be greatly increased when considering the scattering effect.The proposed statistical SS2M model has an average error of 4.16% with respect to SPICE Monte Carlo simulations,with an average error of standard deviation of only 3.06%.

  • Properties of Strong Coupling Bound Magnetopolarons in QuantumDots with Unsymmetrical Parabolic Confinement Potential

    Chen Shihua, Xiao Jinglin

    Chin. J. Semicond.  2006, 27(11): 1923

    Abstract PDF

    The properties of a bound magnetopolaron with electron-LO-phonon strong-coupling in quantum dots with an unsymmetrical parabolic confinement potential are investigated using the Pekar type variational method.The ground state binding energy and the average number of virtual phonons around the electron of the bound magnetopolaron are derived.Numerical calculations indicate that both the ground state binding energy and the average number of virtual phonons around the electron increase with increasing lateral confinement strength,longitudinal confinement strength, and cyclotron frequency.Numerical calculations also indicate that the ground state binding energy increases with increasing coulomb potential.

  • Band Structures of Si Nanowires with Different Surface Terminations

    You Siyu, Wang Yan

    Chin. J. Semicond.  2006, 27(11): 1927

    Abstract PDF

    (100) silicon nanowires (SiNW) with different sizes and different surface terminations are studied with first-principles calculation.The results show that the one dimensional band structures of (100) SiNW with H and F terminations are both direct bandgap semiconductors,but SiNWs with an F termination have a smaller band gap and valence effective mass than SiNWs with an H termination.This can be interpreted via the σ-n mixing effect,i.e., the non-bonding 2P electrons (n) of F atoms produce an important orbital mixing with the σ valence electrons.We also predict from the calculations that the extreme of (100) SiNW-a 2×2 helical Si atom chain- is an indirect bandgap semiconductor.This prediction is explained at the end of this paper.

  • Activation of Fe Doping and Electrical Compensation in Semi-Insulating InP

    Miao Shanshan, Zhao Youwen, Dong Zhiyuan, Deng Aihong, Yang Jun, Wang Bo

    Chin. J. Semicond.  2006, 27(11): 1934

    Abstract PDF

    The impurity distribution,doping activation mechanism,and interaction between Fe atoms and point defects in Fe-doped and annealed undoped semi-insulating(SI) InP materials are compared.The substitution and activation of Fe occur mostly via an interstitial hopping mechanism in as-grown Fe-doped SI InP.However,Fe atoms aggregate around dislocations and form complex defects with vacancies.The concentration of Fe atoms at interstitial positions is very high,resulting in a low activation efficiency.The activation mechanism of Fe is a kick-out substitution process in SI material obtained by annealing undoped InP in an iron phosphide ambient.Fe atoms nearly completely occupy the indium lattice sites due to the indium vacancy in the material before annealing.The formation of deep level defects is suppressed in the annealing process.This results in high Fe activation efficiency and good electrical properties of the SI-InP material.

  • Influence of Reconstruction Defects on Dislocation Motion in Si

    Yang Lijun, Meng Qingyuan, Li Chengxiang, Zhong Kangyou, Guo Licheng

    Chin. J. Semicond.  2006, 27(11): 1940

    Abstract PDF

    We investigate the characteristics of dislocation motion as influenced by defects in a low temperature buffer during the growth of lattice-mismatched heterostructures (SiGe/Si).To do this, we introduce a pair of 30. partial dislocation dipoles into a fully periodic Si crystal.Kinks and their combination with reconstruction defects (kink-RD), which trigger the dislocation motion, are produced in the dislocation line.We employ the Parrinello-Rahman method in a molecular dynamics (MD) simulation and find that shear stress is exerted on the model to evoke the 30°partial dislocation move.Eight stable configurations of left and right kink-RDs in one migration period are derived from the MD simulation, and the energy profile of the kinks and kink-RDs during the migration process are calculated by means of the nudged elastic band method with the Si tight binding potential.We find that the kink-RDs have a lower migration barrier than the kinks.Finally, we conclude that in the low temperature Si buffer technique, the low temperature hampers the motion of reconstruction defects and reduces their annihilation probability.Therefore, more kinks can combine with reconstruction defects to form kink-RD structures to promote the motion of 30°partial dislocation, thereby lowering the dislocation density needed for stress release in the heterostructures.

  • Ground-State Transition Energy in GaInNAs/GaAs Quantum Well Structures

    Yang Jinghai, Yang Lili, Zhang Yongjun, Liu Wenyan, Wang Dandan, Lang Jihui, Zhao Qingxiang

    Chin. J. Semicond.  2006, 27(11): 1945

    Abstract PDF

    The optical transition energy in GaInNAs/GaAs QW structures is investigated from theoretical and experimental aspects.The discrete-level energy and the band-gap energy are calculated using the effective-mass approximation and two-level repulsion model,respectively.The changes in the band-gap energy due to strains are also discussed.The theoretical and experimental transition energies of GaInNAs/GaAs quantum well structures are compared,and they agree well.The effect of N on the transition energies of GaInNAs/GaAs quantum well structures is analyzed simply

  • Microstructure of an InGaN/GaN Multiple Quantum Well LED on Si (111) Substrate

    Li Cuiyun, Zhu Hua, Mo Chunlan, Jiang Fengyi

    Chin. J. Semicond.  2006, 27(11): 1950

    Abstract PDF

    The microstructure of an InGaN/GaN multiple quantum well (MQW) LED on Si (111) substrate is characterized using transmission electron microscopy (TEM) and double crystal X-ray diffraction (DCXRD).High-resolution TEM shows that there is no amorphous layer at the AlN/Si interface.However,stacking faults in the GaN film appear close to the GaN/AlN interface.A very sharp interface between the InGaN and GaN layers reveals the good quality of the MQW material.In addition,TEM and XRD indicate that the dislocation density in the n-GaN layer near the MQW is on the order of 1E8cm-2,and the major dislocation is pure edge dislocation (b=1/3〈11-20〉).

  • Effect of Substrate Structure on the Performance of a Silicon On-Chip Spiral Inductor

    Xue Chunlai, Yao Fei, Cheng Buwen, Wang Qiming

    Chin. J. Semicond.  2006, 27(11): 1955

    Abstract PDF

    The effect of substrate structure on the performance of a spiral inductor is investigated with the 3D electromagnetic simulator HFSS.With variations in the substrate structure including substrate conductivity,permittivity,and thickness of the dielectric layer, the performance of the inductors is analyzed in detail.The simulation results indicate that the performance of the spiral inductor can be improved by lowering the conductivity of the substrate,increasing the thickness of the dielectric layer,and using a low k dielectric layer.In the mean time,some "design rules" are summarized form the results of this study.

  • Measurement of Thermal Conductivity of Ultra-Thin Single Crystal Silicon Film Using Symmetric Structure

    Zhang Hao, Lü Zhichao, Tian Lilin, , Tan Zhimin, Liu Litian

    Chin. J. Semicond.  2006, 27(11): 1961

    Abstract PDF

    The traditional steady-state joule heating method is improved by inducing a symmetric structure,and a thermal isolation trench is added in suspended Si membrane.The novel measurement structure is optimized using ANSYS tools.A large reduction in thermal conductivity resulting from phonon boundary scattering is observed.The lateral thermal conductivity of the 50nm and 80nm Si films at a temperature of 293K are measured to 32 and 38W/(m·K),respectively,which,compared to the bulk value of 148W/(m·K),agree well with the prediction of the BTE equation.

  • Electrochemical Capacitance-Voltage Characterizationof Plasma-Doped Ultra-Shallow Junctions

    Wu Huizhen, Ru Guoping, Zhang Yonggang, Jin C G, Mizuno B, Jiang Yulong, Qu Xinping, Li Bingzong

    Chin. J. Semicond.  2006, 27(11): 1966

    Abstract PDF

    Ultra-shallow Si p+n junctions formed by plasma doping are characterized by electrochemical capacitance-voltage(ECV).By comparing ECV results with secondary ion mass spectroscopy(SIMS) results,it is found that the dopant concentration profiles in the heavily-doped p+ layer as well as junction depths measured by ECV are in good agreement with those measured by SIMS.But the ECV measurement of the dopant concentration in the lightly doped n-type substrate underneath is significantly influenced by the upper heavily-doped layer.The ECV technique is also easy to control and reproduce.The ECV results of ultra-shallow junctions (USJ) formed by plasma doping followed by different annealing processes show that ECV is capable of reliably characterizing a Si USJ with a junction depth as low as 10nm,and dopant concentration up to 1E21cm-3.Its depth resolution can reach as low as 1nm.Therefore it shows great potential in applications for characterizing USJ in sub-65nm technology node CMOS devices.

  • Ohmic Contact for InP-Based HEMTs

    Liu Liang, Yin Junjian, Li Xiao, Zhang Haiying, Li Haiou, He Zhijing, Liu Xunchun

    Chin. J. Semicond.  2006, 27(11): 1970

    Abstract PDF

    An ohmic contact experiment is conducted for InP-based high electron mobility transistors (HEMTs) with two different metal structures of Ni/Ge/Au and Ni/Ge/Au/Ge/Ni/Au.Comparison is made between rapid thermal annealing (10~40s) and alloying over a long time(10min).Optimized alloying conditions for the InP-based HEMT are obtained.Using the Ni/Ge/Au/Ge/Ni/Au structure,a typical contact resistance of 0.068Ω·mm is achieved by alloying at 270℃ for 10min.

  • Design and Fabrication of Gate-Type Resonant Tunneling Transistors

    Guo Weilian, Liang Huilai, Song Ruiliang, Zhang Shilin, Mao Luhong, Hu Liuchang, Li Jianheng, Qi Haitao, Feng Zhen, Tian Guoping, Shang Yuehui, Liu Yongqiang, Li Yali, Yuan Mingwen, Li Xiaobai

    Chin. J. Semicond.  2006, 27(11): 1974

    Abstract PDF

    A GaAs-based resonant tunneling transistor with a gate structure (GRTT) has been designed and fabricated successfully for the first time in mainland China.The design of the material structure,device structure,and photolithography mask;the fabrication of the device;and the parameter measurement and analysis are described systematically.The fabricated GRTT has a maximum PVCR of 46 and maximum transconductance of 8mS.This work establishes a foundation for further improvement of the performance and parameters of RTTs.

  • Fabrication of a High-Performance 1mm AlGaN/GaN HEMT on SiC Substrate

    Luo Weijun, Chen Xiaojuan, Li Chengzhan, Liu Xinyu, He Zhijing, Wei Ke, Liang Xiaoxin, Wang Xiaoliang

    Chin. J. Semicond.  2006, 27(11): 1981

    Abstract PDF

    This paper reports a high-performance AlGaN/GaN HEMT with 1 mm gate width on 6H-SiC substrate.The epitaxial materials of the device are grown with metal organic chemical vapor deposition.Test results indicate that the gate length of the device is 0.8μm,the output current density is 1.16A/mm,the transconductance is 241mS/mm,the breakdown voltage is greater than 80V,the current gain cutoff frequency reaches 20GHz,and the power gain cutoff frequency is 28GHz.The power gain of a continuous wave at 5.4GHz is 14.2dB,with an output power of 4.1W,while the corresponding results of pulsed power test are 14.4dB and 5.2W.Two ports impedance characteristics demonstrate good potential in microwave applications.

  • A New AlGaN/GaN HEMT Semiempirical DC Model

    Liu Dan, Chen Xiaojuan, Liu Guoguo, He Zhijing, Liu Xinyu, Wu Dexin

    Chin. J. Semicond.  2006, 27(11): 1984

    Abstract PDF

    A new AlGaN/GaN HEMT semiempirical DC model is given.This is the first model that takes into account the effect of the gate source voltages Vgs on the knee voltage.Functions describing the DC characteristic of the AlGaN/GaN HEMT are obtained.The model can be used to model the DC characteristic of AlGaN/GaN HEMTs based on sapphire as well as SiC.The error between results simulated by the model and the measured results is less than 3%.

  • Transient Thermal Effects of LDMOS in Switching Operation

    Li Meizhi, Guo Chao, Chen Xingbi

    Chin. J. Semicond.  2006, 27(11): 1989

    Abstract PDF

    The phenomenon of slow thermal runaway is studied and verified with thermal circuits to describe the rise and fall characteristics of lattice temperature during continuous pulses of applied electric power which produces thermal effects.Our results show that a high-frequency switch can operate in the thermally safe operation area if the delay time of the applied pulses is longer than the thermal delay time during the fall process of lattice temperature.We show that LDMOS will switch in the thermally safe operation area with its thermal resistance of 3.5K/W and thermal capacitance of 5μs·W/K if the frequency of the applied pulses is less than 7.14kHz with a duty cycle of 0.5,or if the duty cycle of the applied pulses is less than 0.3 with a frequency of 10kHz.A criterion is given for power devices in the thermally safe operation area.

  • Characteristics of Groove-Gate MOSFETs

    Cao Yanrong, Ma Xiaohua, Hao Yue, Yu Lei

    Chin. J. Semicond.  2006, 27(11): 1994

    Abstract PDF

    The groove- and planar-gate MOSFETs are compared and analyzed through simulation with the software SIVALCO,and the results show that the groove-gate MOSFETs can suppress short channel and hot carries effects.From the analysis of the field,we find that due to the corner effect,the performance of groove-gate MOSFETs is better than that of the planar.The groove-gate MOSFETs with 140nm channel length fabricated with a self-aligned process are tested,and the results effectively show the superiority of the groove-gate MOSFETs over the planar.

  • A Low-Field Hole Mobility Model of Strained Si1-xGex pMOSFET

    Zhang Xuefeng, Xu Jingping, Zou Xiao, Zhang Lanjun

    Chin. J. Semicond.  2006, 27(11): 2000

    Abstract PDF

    A semi-experienced low-field hole mobility model of a strained Si1-xGex/Si pMOSFET is proposed by considering the effect of the strain on the energy-band structure of SiGe alloy.This model includes the variation of mobility with strain (Ge content) and the coulomb-scattering mechanism of interface-trapped charges on inversion carriers.Using the model,the change of the hole mobility with strain (Ge content) is simulated at room temperature,and the influence of some factors on mobility is discussed.

  • Analytical Model for the Electric Field Distribution of an SOI High Voltage Device with a Compound Dielectric Layer

    Luo Xiaorong, Li Zhaoji, Zhang Bo

    Chin. J. Semicond.  2006, 27(11): 2005

    Abstract PDF

    A novel SOI high voltage device with a compound dielectric buried layer is proposed,and an analytical model for its electric field and potential is established.A unified criterion of RESURF condition for CDL SOI and a uniform dielectric buried layer SOI device is given.The vertical electric field of the buried layer is enhanced due to the low k (permittivity) of the dielectric buried layer at the drain side,the electric field in the drift region is modulated by the compound dielectric layer with different k values,and both increase the breakdown voltage of the device.Based on the analytical model and the 2D device simulation,the electric field distribution and potential distribution are analyzed.The simulation results are in good agreement with the analytical results.It shows that the electric field of the buried layer and breakdown voltage of the CDL SOI when the low k value is 2 are enhanced by 82% and 58% compared to conventional SOI,respectively.

  • Numerical Analysis of the Effect of a DBR with Graded Interfaces on the Resonant Cavity of a VCSEL

    Wang Xiaodong, Wu Xuming, , Wang Qing, Cao Yulian, He Guorong

    Chin. J. Semicond.  2006, 27(11): 2011

    Abstract PDF

    The optical characteristics and the effect on a VCSEL resonant cavity of an Al0.9Ga0.1As/AlyGa1-yAs/GaAs/AlxGa1-xAs DBR with linearly graded interfaces are analyzed numerically.The relations are established between the refractive index and the thickness of the graded interfaces.The reflectance spectrum and the reflective phase shift are calculated for an abrupt GaAs/Al0.9Ga0.1As DBR and a graded interface DBR using the characteristic matrix method.The influence of the graded layer on the reflectivity and reflective phase shift of the DBR is analyzed.The result shows that an extra graded layer as a phase matching layer must be added in front of the graded interface DBR near the VCSEL resonant cavity to obtain the condition of phase matching at the central wavelength.The accurate thickness of the phase matching layer and homogeneous layer are obtained by numerical analysis on the condition of phase matching.

  • Small Signal Equivalent Circuit Model of BuriedTunnel Junction VCSEL Chips

    Xu Guizhi, Hofmann W, Huang Hengpei, Zhang Tao, Xie Liang, Zhu Ninghua, Amann M C

    Chin. J. Semicond.  2006, 27(11): 2015

    Abstract PDF

    An equivalent circuit model for a 1.55μm buried tunnel junction VCSEL chip is proposed.The model is based on the semiconductor laser rate equations and the structure of the VCSEL chip,and every element in the circuit is represented.Values of the elements of the circuit are established using the reflection coefficient and transmission frequency response data.The simulation results agree well with experimental data at different bias currents,verifying the validity of the equivalent circuit model.

  • Study of Uni-Traveling-Carrier Photodetectors

    Zhu Haobo, Mao Luhong, , Yang Zhan, Guo Weilian

    Chin. J. Semicond.  2006, 27(11): 2019

    Abstract PDF

    A new type of photodetector,called a UTC-PD (uni-traveling-carrier photodetector) ,is simulated with Atlas simulator.The basic principle of the device is studied.In particular,the relationship between structure and performance is discussed.The obtained UTC-PD can achieve high responsivity (≥0.18A/W) and wide 3dB band-width (≥100GHz) simultaneously.Compared to conventional pin photodetectors,the UTC-PD has a simpler front-end circuit,lighter noise,and lower cost.

  • A Rail-to-Rail Input/Output Amplifier Using Common-GateFrequency Compensation

    Wang Weizhi, Jin Dongming

    Chin. J. Semicond.  2006, 27(11): 2025

    Abstract PDF

    A rail-to-rail input/output CMOS amplifier using common-gate compensation is proposed.The amplifier achieves a unity gain frequency of 25MHz while employing only one compensation capacitor.The power dissipation of the circuit is 1.34mW with a supply voltage of 5V and a biasing current of 20μA.Using the proposed circuit,a unity gain buffer is also implemented with a supply voltage of 3V and driving a capacitive load of 150pF.A THD of -51.6dB is obtained for a 2.66VPP 10kHz input sine signal.Simulated results reveal a high slew-rate and large driving capability.This amplifier is fabricated in CSMC 0.6μm CMOS mixed-signal technology.The test results are also provided.

  • A Wide-Band CMOS Low-Noise Amplifier for TV Tuner Applications

    Liao Youchun, , Tang Zhangwen

    Chin. J. Semicond.  2006, 27(11): 2029

    Abstract PDF

    A wide-band CMOS low-noise amplifier (LNA) is presented,in which the input MOSFET thermal noise is canceled by exploiting a noise-canceling technique.The chip was implemented in a TSMC 0.25μm 1P5M RF CMOS process.Test results show that in the range of 50~860MHz,the voltage gain is about 13.4dB,and the noise figure (NF) is below 3.5dB with a minimum NF value of 2.4dB at 350MHz.The input-referred 1dB compression point is -6.7dBm,and the IIP3 is 3.3dBm.The chip consumes 30mW with a 2.5V power supply.

  • A 1V MNC Bandgap Reference with High Temperature Stability

    Qin Bo, Jia Chen, Chen Zhiliang, Chen Hongyi

    Chin. J. Semicond.  2006, 27(11): 2035

    Abstract PDF

    A 1V matched nonlinear correction (MNC) CMOS bandgap reference with high temperature stability is presented.A 1V operational amplifier (OPA) with rail-to-rail input signal swing is also applied in the reference circuit.According to the experimental results,the output voltage is 3519mV at room temperature.It varies by only 0.5mV from the range of 15~100℃,and the temperature coefficient is 16.7ppm/℃.The power dissipation of the circuit is 0.16mW,and the area is 0.18mm2.

  • HVIC with Coupled Level Shift Structure

    Qiao Ming, Fang Jian, Li Zhaoji, Zhang Bo

    Chin. J. Semicond.  2006, 27(11): 2040

    Abstract PDF

    A coupled level shift structure is designed and implemented.Compared with conventional S level shift structures,the two high electric fields of an LDMOS and a high voltage junction termination (HVJT) introduced by a high voltage interconnection (HVI) are avoided. The HV level shift and isolation of the high side and low side are directly coupled,so the chip size is reduced.The isolated resistor in the C level shift structure can be increased by a JFET consisting of a Pwell,Nepi,and P-sub,and the short of a poly field plate (PFP) in the LDMOS and HVJT is avoided by use of a metal field plate (MFP).Using HV single poly single metal (SPSM) CMOS DMOS (CD) technology developed by us,we experiment on a 1000V 3-phase power MOS gate driver circuit with C level shift structure successfully.The experimental results show that the maximal breakdown voltage of the C level shift structure is 1040V,which is 62.5% higher than that of a conventional S structure.The 1000V HVIC can be used for the HV application of AC220V and AC380V.

  • An ASK-Based IF Receiver for Wireless Endoscopy Capsule Systems

    Yao Jinke, Chi Baoyong, Wang Zhihua

    Chin. J. Semicond.  2006, 27(11): 2046

    Abstract PDF

    This paper presents a low power ASK IF receiver for wireless endoscopy capsule systems.The receiver includes an AGC loop that compensates the channel attenuation,an ASK demodulator,and a band-gap based bias circuit.The IF-circuit was implemented in a 0.25μm CMOS process.Tests show that the IF receiver can correctly detect digital base-band signals from -30~10dBm IF signals with an IF operating frequency of 20MHz.The receiver draws about 2.1mA of current from a 2.5V power supply.

  • Impurity Distribution of Silicon Direct Bonding

    Chen Xin'an, Huang Qing'an

    Chin. J. Semicond.  2006, 27(11): 2051

    Abstract PDF

    There is a thin layer of native oxide between two directly bonded silicon wafers.The silicon extracts impurity from the oxide,thus drastically decreasing the impurity concentration at the interface of SiO2-Si.Based on the modified model of silicon direct bonding,an expression of impurity distribution is derived and verified by theory and experiment.Finally,it is found that the total impurity in silicon with oxide is much less than that without oxide,which decreases the junction depth of p-n+ junction.

  • Nonlinear Dynamical Behaviors in Flip-Chip Thermosonic Bonding

    Han Lei, Zhong Jue

    Chin. J. Semicond.  2006, 27(11): 2056

    Abstract PDF

    Dynamical characteristics of transducer systems are the key to the basic understanding of metal interconnection and reliable fine pitch flip-chip bonding.Systematic experimental analysis clearly shows that rich phenomena and effects such as a Duffing resonator,dynamical coupling between the transducer and bonding tool,and strange phase portraits of die movement may be explained by the nonlinear features of a real world transducer system.It is possible to explore their mechanisms and effects on bonding quality by identifying and decoding them from experimental data

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