Silicon-on-insulator (SOI)-based high-speed electro-optic modulators are the key component in optical communication and computing systems.It is necessary to scale down the size of optical waveguides to increase integrity and modulation speed.However,many difficulties will be faced,such as changes in the single-mode conditions,increased transmission loss and coupling loss,and polarization dependence.In this paper,the single-mode conditions of SOI waveguides with different section areas are introduced,and various techniques for dealing with these difficulties are described.Then,a high-speed silicon modulator with a metal-oxide-semiconductor capacitor and a compact silicon modulator with a ring resonator are introduced and analyzed, whose modulation frequencies are as high as 10 and 1.5GHz,respectively.
The linear-polarization optical property of CdSe quantum rods is studied in the framework of effective-mass envelope function theory.The effects of shape and magnetic field on the linear polarization factors are investigated.It is found that CdSe quantum spheres have negative polarization factors (xy-polarized emission)and quantum long rods with small radius have positive linear polarization factors (z-polarized emission).The z-direction is the direction of the c axis.Quantum long rods with large radius have negative linear polarization factors,due to the hexagonal crystal symmetry and the crystal field splitting energy.The linear polarization factors decrease and may change from a positive value to a negative value;i.e.,the z-polarized emissions decrease relative to xy-polarized emissions as the magnetic field applied along the z direction increases.
A low-voltage,low-power,and high-gain rail-to-rail operational amplifier(OpAmp)is presented.The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier,which does not degrade the output swing and is very suitable for low-voltage applications.In a 0.18μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed.For a load capacitance of 5pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65.9dB,gain bandwidth of 70.28 MHz,and phase margin of 50℃ with a quiescent power dissipation of 156.7μW.
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying(GMSK)modulation is presented.A pre-compensation fractional-N phase-locked loop(PLL)is adopted in the modulator.The transfer function of the type-II third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out.Methods to calibrate the important loop parameters are introduced.A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design.The designed circuits are simulated in a 0.18μm 1P6M CMOS process.The power consumption of the PLL is only about 11mW with the low power consideration in building blocks design,and the data rate of the modulator can reach 2Mb/s
The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented.Based on the principle of voltage-controlled oscillators’ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC.A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC.It is fabricated with a Chartered 0.35μm CMOS process,and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively.The maximum gain error measured in ten sample chips is ±3.85%.With sampling rate of 500kHz and when the voltage regulator module (VRM) works in steady state,the ring-ADC’s average power consumption is 2.56mW.The ring-ADC is verified to meet the requirements for digital VRM controller application.
The influence of a magnetic field and Coulomb field on the properties of a strong-coupling polaron in a semiconductor quantum dot is studied using the linear combination operator and unitary transformation method.The relations between the vibration frequency and the ground state energy of a strong-coupling bound magnetopolaron in a semiconductor quantum dot with the confinement length of the quantum dot,the Coulomb bound potential,cyclotron resonance frequency of magnetic field,and electron-phonon coupling strength are derived.Numerical calculation results show that the vibration frequency and the ground state energy of the strong-coupling bound magnetopolaron increase strongly with the decreasing confinement length of quantum dot while increase with the increasing cyclotron resonance frequency of magnetic field.The ground state energy of the strong-coupling bound magnetopolaron decreases with the increasing electron-phonon coupling strength and Coulomb bound potential.
The temperature dependences on the properties of strong-coupling bound magnetopolarn in a quantum dot are studied using the linear combination operator and the unitary transformation methods.The relations of the vibrational frequency,the ground state energy,and the mean number of phonons of the strong-coupling bound magnetopolaron in a quantum dot with the temperature are derived.Numerical calculations,for the RbCl crystal as an example,are performed,and the results indicate that the vibrational frequency,the ground state energy and the mean number of phonons of the strong-coupling bound magnetopolaron in a quantum dot increase with the increase of the temperature.The ground state energy increases with the increase of the confinement strength of the quantum dot
Defects and their influence on InP single crystal substrate arc investigated.Results on cluster dislocation and its deterioration on lattice perfection,pit-like micro-defects,residual damage, and impurities and their removal by cleaning are presented.Formation mechanisms of the defects and approaches to suppressing them are discussed.Finally,epi-ready InP polished single crystal wafer with high lattice perfection,free of surface damage,is obtained.
A tin dioxide nanotube is fabricated on titanium by anodization and electroplating.First,a nickel film is deposited on 3mm-thick titanium.Then a 1μm-thick tin layer is deposited thereon by electroplating.The wafer is anodized for 5min in 0.5mol/L oxalic acid solution,at constant DC 5V at room temperature.After the anodization,to enlarge the pore size and remove the barrier layer,the anodized specimens are immersed in a 1.0mol/L oxalic acid solution for 15min at 80℃.The obtained samples are examined by scanning electron microscopy,EDS,and X-ray diffraction.The results indicate that a layer of nano-pore arrays of tin oxidation,whose thickness is about 1μm,formed on the titanium.The pore diameter is 70nm.The distance between two adjacent pores is 80nm.The sample is heated to 500℃ for 2h to fabricate SnO2 compound and is used for the fabrication of composite coating on titanium also.
The principle of the enhancement of nc-Ge/Si islands by a photonic crystal single-defect cavity is explained.For a photonic crystal slab with a thickness of 300nm,the resonant wavelength of a photonic crystal single-defect cavity based on Ge/Si islands as a function of a and r／a is calculated with the 3D FDTD method and is analyzed theoretically.For fixed r／a and h,the wavelength increases sub-linearly with the increase of lattice constant.For fixed a and h,the wavelength decreases linearly with the increase of r/a.
Hole mobility in strained silicon pMOS inversion layers is investigated theoretically.Using a six-band stress-dependent k·p model,the subband structures of 2DHG in inversion layers are computed from a self-consistent solution to the one-dimensional Schrdinger and Poisson equations.The hole mobility dependence on the transverse electric field for both uniaxial compression and biaxial tension is studied with the Monte Carlo method and compared with the case of unstrained silicon.The simulation results show that both uniaxial compression and biaxial tension can enhance the hole mobility.Uniaxial compression along the [110] direction enhances the hole mobility much more than in any other crystalline orientation.
We propose a center-tapped equivalent model for center-tapped differential inductors.The single-ended and differential impedances in differential applications are derived.A 2-port S-parameter measurement with the center-tap grounded is used to extract the equivalent resistance,inductance,and Q-factor (RLQ).A multi-layer center-tapped differential inductor is implemented in a 0.35μm 1P4M RF CMOS process.The proposed model agrees well with the experimental results below the self-resonance frequency.
The geometrical correction factor of a sector Hall plate is obtained by the method of conformal mapping, according to which we derived the analytical expression of the relative sensitivity of a sector split-drain magnetic field-effect transistor.The mathematical model of relative sensitivity is improved,as verified by simulation and experiment.Compared with a rectangular MAGFET,a sector MAGFET has the advantage of high relative sensitivity.The maximum relative sensitivity obtained in experiment is 3.77%T-1,and our model predicts a maximum relative sensitivity of 3.81%T-1.
A 32GHz 0.5W PHEMT MMIC power amplifier,which has three stages,is designed,fabricated,and measured.It operates under a 6V power supply and 600mA DC bias.A 17.4dB maximum small signal gain and 0.5W saturated output power are achieved at the operation frequency.
A millimeter-wave band GaAs pin diode SPST switch MMIC is presented.It is ideal for low loss,high isolation,and high power applications.In the 15～20GHz frequency range,its insertion loss is less than 0.6dB,its VSWR is better than 1.5,and its isolation is better than 40dB.In the 20～40GHz frequency range,its insertion loss is less than 1.1dB,its VSWR is better than 1.35,and its isolation is better than 35dB.The output power of the pin SPST MMIC at 1dB compression is 2W.These results are obtained using a vertical GaAs pin diode process on MOCVD material.
A novel device structure for planar resonant tunneling diode (PRTD) is proposed.Semi-insulated (SI) GaAs is replaced with n＋ GaAs as substrate,and amorphous GaAs obtained by Boron ion implantation is employed as the electrical insulator in the devices.The PRTD and Monostable-Bistable transition logic element (MOBILE) formed by the PRTD are designed and fabricated successfully.This device structure can be widely used in all circuits whose common terminals are made by output terminals.
An optimized 808nm InGaAsP/InGaP/AlGaAs laser diode structure with a large optical cavity is analyzed.To achieve single-transverse mode lasing,the thickness of the cladding layers and cap layers are optimized to improve the modal discrimination.The optimal thicknesses are 0.8,0.6,and 0.11μm for the upper cladding layer,lower cladding layer,and cap layers,respectively.An ohmic contact layer with a high refractive index surrounded by the metal layer and cladding layer acts as a secondary waveguide.A leaky wave forms a parasitical mode in the secondary waveguide.The modal loss dependence on the cap thickness is periodic.The first resonance occurs when the cap thickness is λ1/4,and the interval between resonances is λ1/2,where λ1 is the perpendicular projected wavelength of the leaky wave for some mode.
The design of a 40GHz broadband light source is presented.Key technologies of the light source are developed,including techniques for stabilizing the devices and compensating the frequency response distortion.A 40GHz broadband light source based on a LiNbO3 optical modulator has been successfully manufactured.Experiments and tests show that the light source can be used not only for small signal frequency response measurement systems,but also for large signal SDH/SONET transmission test systems.
By mathematical proof,we identify a modified feedback emitter-coupled logic (MFECL) gate with an ECL memory-gate or D latch, because the MFECL gate is able to keep steady either of two states.Then we present a D master-slave flip-flop that consists of two ECL memory-gates.On the basis of the above theory,a five-carry shifting counter is designed using such D master-slave flip-flops.The above theory and circuits are verified through computer simulation.
A low-power phase-locked loop (PLL) is designed and fabricated in TSMC’s standard 0.25μm CMOS process.A behavioral simulation method for the PLL’s phase noise is presented.The power consumption of the PLL core is about 12mW.The rms jitter is 6.1ps,and the SSB phase noise is -106dBc/Hz at a 10kHz offset.
We first analyze the source of reference spurs.Then we present some design techniques to restrain them.These techniques include improving the matching between the up current and down current in the charge pump,alleviating the charge injection and clock feed-through of the charge pump’s switch,matching the up/down branch of the PFD,and enhancing the isolation of the PLL both in IC and PCB.Two PLLs designed for PCI-express transceivers are fabricated in a TSMC 0.13μm CMOS process. Measurement results show that these methods are effective
A novel design method for low power switched-capacitor (SC) circuits is presented. The new SC circuits make the best of the characteristics of switched-capacitor circuits and can be directly powered by alternative-current (AC) power supply; the power consuming OTA is powered OFF during sampling phase. Compared with the traditional direct-current-powered SC (DCPSC) circuits, AC-powered SC (ACPSC) circuits achieve a power saving ratio up to 40% without obvious damage to the settling behavior, which is simulated with CSMC 5-V 0.6-μm technology. Also, the functionality of ACPSC circuits is proven by fabricated chips.
A bandgap voltage reference based on the conventional architecture is optimized.The effects of the MOS device mismatch and the channel-length modulation are decreased by optimizing the design of the current mirror and controllingUDS.Better precision and a lower temperature coefficient are obtained.The average value of the output voltage is 1.23±0.02V,with a standard deviation (σ) of only 0.007V,for 200 chips that were measured.The average measured temperature coefficient is 16ppm/℃ in the range of -40 to 85℃,and the average power supply current is 100μA.The designed and measured values are well matched in this optimized architecture.
Based on the detailed analysis of the loading properties of a medium or small size TFT-LCD driver IC,a novel output buffer circuit of driving voltages is proposed.By using negative voltage feedback,the operating states of the output stage in the output buffer circuit can be controlled dynamically,which can provide source current and sink current alternately,so that the output voltage fluctuations can be rejected effectively.Compared with a conventional push-pull output buffer circuit,it has such advantages as lower static power consumption,smaller chip area,and better stability.Two output buffer circuits driving different voltages are designed and implemented using a 0.25μm CMOS process.HSPICE simulation results show that the static current is 3μA and the offset voltage is less than ±2mV.Furthermore,when the driving voltage for the TFT-LCD panel is switched between -8 and 16V,the fluctuations and the recovering times of the output voltages are less than ±0.4V and 7μs,respectively.By measuring the TFT-LCD driver IC’s engineering samples,it is shown that the proposed output buffer circuits can completely satisfy the demands of a medium or small size TFT-LCD driver IC.
An InGaP/GaAs HBT microwave power transistor with on-chip parallel RC stabilization network is developed with a standard GaAs MMIC process.From the stability factor K,the device shows unconditional stability in a wide frequency range due to the RC network.The power characteristics of the device as measured by a load-pull system show that the large-signal performance of the power transistor is affected slightly by the RC network.Psat is 30dBm at 5.4GHz,and P1dB is larger than 21.6dBm at 11GHz.The stability of the device due to RC network is proved by a power combination circuit.This makes the power transistor very suitable for applications in microwave high power HBT amplifiers.
A two-stage monolithic low noise amplifier is developed for satellite communication applications,using a 0.5μm enhancement PHEMT technology.The on-chip matched amplifier employs lumped elements to reduce the circuit size,and shows a 50Ω noise figure less than 0.9dB,gain greater than 26dB,and return loss less than -10dB in the S-C band range of 3.5 to 4.3GHz.The noise figure obtained here is the best result ever reported to date of an MMIC LNA with a gain of more than 20dB for the S-C band frequency range.It is attributed to the low noise performance of the enhancement PHEMT transistor and minimized parasitic resistance of the input match network by a common series source inductor and a unique divided resistance at the drain.
Based on the equivalent circuit model of a two-port optical receiver front-end,the relationship between the equivalent input noise current spectral density and the noise figure is analyzed.The derived relationship has universal validity for determining the equivalent input noise current spectral density for optical receiver designs,as verified by measuring a 155Mb/s high-impedance optical receiver front-end.Good agreement between calculated and simulated results has been achieved.
We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor (MOS) capacitor configuration integrated into silicon-on-insulator (SOI).Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure,which boosts the modulation efficiency compared with a single MOS capacitor.The simulation results demonstrate that the VπLπ product is 2.4V·cm.The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve,respectively,indicating a bandwidth of 8GHz.The phase shift efficiency and bandwidth can be enhanced by rib width scaling.
