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Volume 27, Issue 5, May 2006


  • Alloy Temperature Dependence of Offset Voltage and Ohmic Contact Resistance in Thin Base InGaP/GaAs HBTs

    Yang Wei, Liu Xunchun, Zhu Min, Wang Runmei, Shen Huajun

    Chin. J. Semicond.  2006, 27(5): 765

    Abstract PDF

    The alloy temperature dependence of Voffset and Rcontact is studied,and an optimal alloy temperature range for the best trade-off between Voffset and Rcontact is given for thin base HBTs.In addition,the reason for the high Voffset at high alloy temperature is interpreted using Schottky clamped theory.The lower Voffset of our U-shaped emitter HBT than that of traditional strip emitter HBTs is explained.

  • Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

    Xue Chunlai, Yao Fei, Cheng Buwen, Wang Qiming

    Chin. J. Semicond.  2006, 27(5): 769

    Abstract PDF

    The effects of key geometrical parameters on the performance of integrated spiral inductors are investigated with the 3D electromagnetic simulator HFSS.While varying geometrical parameters such as the number of turns (N),the width of the metal traces (W),the spacing between the traces (S),and the inner diameter (ID),changes in the performance of the inductors are analyzed in detail.The reasons for these changes in performance are presented.Simulation results indicate that the performance of an integrated spiral inductor can be improved by optimizing its layout.Some design rules are summarized.

  • Sub-1V CMOS Voltage Reference Based on Weighted Vgs

    Zhang Xun, Wang Peng, Jin Dongming

    Chin. J. Semicond.  2006, 27(5): 774

    Abstract PDF

    We propose a voltage reference based on the weighted difference between the gate-source voltages of an nMOS and a pMOS operating in their saturation regions.No diodes or parasitic bipolar transistors are used.The circuit is simulated and fabricated with SMIC 0.18μm mixed-signal technology,and our measurements demonstrate that its temperature coefficient is 44ppm/℃ and its PSRR is -46dB.It works well when Vdd is above 650mV.The active area of the circuit is about 0.05mm2

  • A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers

    Han Shuguang, Chi Baoyong, Wang Zhihua

    Chin. J. Semicond.  2006, 27(5): 778

    Abstract PDF

    Based on a physical understanding of nonlinearity and mismatch,a novel offset-cancellation technique for low voltage CMOS differential amplifiers is proposed.The technique transfers the offset voltage from the output to other parts of the differential amplifier and can greatly reduce the input-referred offset voltage without extra power consumption.A 1.8V CMOS differential amplifier is implemented in 0.18μm CMOS process using the proposed technique.The simulation results show that the technique could reduce the input-referred offset voltage of the amplifier by 40% with a 20% load transistor mismatch and a 10% input differential transistor mismatch.Moreover,the proposed technique consumes the least power and achieves the highest integration among various offset-cancellation techniques.

  • Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits

    Mao Xiaojian, Yang Huazhong, Wang Hui

    Chin. J. Semicond.  2006, 27(5): 783

    Abstract PDF

    A simple and successful method for the stability enhancement of integrated circuits is presented.When the process parameters,temperature,and supply voltage are changed,according to the simulation results,this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case.This method can be used in CMOS LC oscillator design.


  • Bound Polaron in a Quantum Well Under an Electric Field

    Chen Weili, Xiao Jinglin

    Chin. J. Semicond.  2006, 27(5): 787

    Abstract PDF

    We conduct a theoretical study on the properties of a bound polaron in a quantum well under an electric field using linear combination operator and unitary transformation methods,which are valid in the whole range of electron-LO phonon coupling.The changing relations between the ground-state energy of the bound polaron in the quantum well and the Coulomb bound potential,the electric field strength,and the well width are derived.The numerical results show that the ground-state energy increases with the increase of the electric field strength and the Coulomb bound potential and decreases as the well width increases.

  • Performance of an InP DHBT Grown by MBE

    Su Shubing, Liu Xinyu, Xu Anhuai, Yu Jinyong, Qi Ming, Liu Xunchun, Wang Runmei

    Chin. J. Semicond.  2006, 27(5): 792

    Abstract PDF

    We report the performance of the first self-aligned InP/InGaAs double heterojunction bipolar transistor (DHBT) produced in China.The device has a 2μm×12μm U-shaped emitter area and demonstrates a peak common-emitter DC current gain of over 300,an offset voltage of 0.16V,a knee voltage of 0.6V,and an open-base breakdown voltage of about 6V.The HBT exhibits good microwave performance with a current gain cutoff frequency of 80GHz and a maximum oscillation frequency of 40GHz.These results indicate that this InP/InGaAs DHBT is suitable for low-voltage,low-power,and high-frequency applications.

  • SOI MOSFET Model Parameter Extraction via a Compound Genetic Algorithm

    Li Ruizhen, Li Duoli, Du Huan, Hai Chaohe, Han Zhengsheng

    Chin. J. Semicond.  2006, 27(5): 796

    Abstract PDF

    We improve the genetic algorithm by combining it with a simulated annealing algorithm.The improved algorithm is used to extract model parameters of SOI MOSFETs,which are fabricated with standard 1.2μm CMOS/SOI technology developed by the Institute of Microelectronics of the Chinese Academy of Sciences.The simulation results using this model are in excellent agreement with experimental results.The precision is improved noticeably compared to commercial software.This method requires neither a deeper understanding of SOI MOSFETs model nor more complex computations than conventional algorithms used by commercial software.Comprehensive verification shows that this model is applicable to a very large range of device sizes.

  • Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies

    Guo Baozeng, Gong Na, Wang Jinhui

    Chin. J. Semicond.  2006, 27(5): 804

    Abstract PDF

    Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed.Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE.The simulation results show that the proposed circuits effectively lower the active power,reduce the total leakage current,and enhance speed under similar noise immunity conditions.The active power of the two proposed circuits can be reduced by up to 8.8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage.At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4%,respectively.Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.

  • Large Scale VLSI Module Placement Using LFF Heuristics by Stages

    Wei Shaojun, Dong Sheqin, Hong Xianlong, Wu Youliang

    Chin. J. Semicond.  2006, 27(5): 812

    Abstract PDF

    We present a deterministic algorithm for large-scale VLSI module placement.Following the less flexibility first (LFF) principle,we simulate a manual packing process in which the concept of placement by stages is introduced to reduce the overall evaluation complexity.The complexity of the proposed algorithm is (N1+N2)×O(n2)+N3×O(n4lgn),where N1,N2,and N3 denote the number of modules in each stage,N1+N2+N3=n,and N3<

  • Method of Verification for Manufacturing in Sub-Wavelength Design

    Wang Guoxiong, Yan Xiaolang

    Chin. J. Semicond.  2006, 27(5): 819

    Abstract PDF

    We describe a post resolution-enhancement-technique verification method for use in manufacturing data flow.The goal of the method is to verify whether designs function as intended,or more precisely,whether the printed images are consistent with the design intent.The process modeling is described for the model-based verification method.The performance of the method is demonstrated by experiment

  • Properties of Quasi-Two-Dimensional Strong-CouplingMagnetopolarons in Magnetic Fields

    Eerdunchaolu, Wuyunqimuge, Xu Qiu, Bai Xufang

    Chin. J. Semicond.  2006, 27(5): 824

    Abstract PDF

    The ground state of a magnetopolaron that is weakly coupled with bulk longitudinal optical phonons and strongly coupled with interface optical phonons,in an infinite quantum well within magnetic fields is studied using the linear-combination operator and a modified LLP variational method.Rules for how the vibration frequency and self-trapping energy of the magnetopolaron change with the width of the quantum well and the magnetic fields are obtained.Our numerical results for a CdF2/AgCl QW show that the vibration frequency and the self-trapping energy of the magnetopolaron decrease with increasing well width and increase with increasing magnetic fields strength,but the contribution of interaction between the different branches of phonons and the electron and the magnetic fields to the vibration frequency and the self-trapping energy of the magnetopolaron are greatly different.The above-mentioned phenomena are also analyzed.

  • Quantum Well Under an External Electric Field

    Zhao Fengqi, Sarula

    Chin. J. Semicond.  2006, 27(5): 830

    Abstract PDF

    The ground state and binding energy of a hydrogenic impurity as functions of the electric field and well width in a GaAs/AlxGa1-xAs PQW are investigated with the variational method.The effects of spatial dependent effective mass and spatial dependent dielectric constant are considered in the calculation.The results indicate that the effects of the external electric field on the ground state and binding energy of the hydrogenic impurity are noticeable,and they increase with increasing well width.The effects of the spatial dependent effective mass and spatial dependent dielectric constant make the ground state energy decrease and the binding energy increase.These effects decrease with increasing well width.

  • Average-Bond-Energy and Fermi Level on Metal-Semiconductor Contacts

    Li Shuping, Wang Renzhi

    Chin. J. Semicond.  2006, 27(5): 834

    Abstract PDF

    To further understand the average-bond-energy Em,which can be taken as the reference energy level in the calculation of metal-semiconductor contacts,the Em of the semiconductor and the Fermi level EF(M) of the metal on both sides of the metal-semiconductor interface in (Ge2)4(2Al)6(001),(Ge2)4(2Au)6(001),(Ge2)4(2Ag)6(001),(GaAs)4(2Al)6(001),(GaAs)4(2Au)6(001),and GaAs)4(2Ag)6(001) superlattices are investigated by the calculation of the LMTO-ASA energy band structure with the frozen-potential method.The results show that Em of the semiconductor and EF(M) of the metal are almost on the same horizontal energy level,i.e.Em≈EF(M) .In other words,Em and EF(M) on both sides of the metal-semiconductor interface are mutually aligned.This indicates that reliable calculation results can be obtained by taking Em as the reference energy level in the calculation of the barrier height of ideal metal-semiconductor contacts.

  • Energy Band Structure and Conducting Characteristics of ITO Films

    Zhang Zhiguo

    Chin. J. Semicond.  2006, 27(5): 840

    Abstract PDF

    Using scanning electron micrographs and XRD analysis of ITO films,the energy band structures of equilibrium and non-equilibrium of ITO films are constructed.A model of the band-tail state distribution is built using the Kronig-Penney model.A never-before-reported hysteresis loop in the I-V curve is obtained in the measurement.The experimental results agree well with the theoretical data.By analyzing the mechanism behind the I-V characteristic,the model of the energy band structure is proved reasonable.The temperature characteristics of the ITO film measured show that the slope of the conductivity-temperature curve varies from a positive value to a negative one.

  • Isochronal and Isothermal Annealing Effects on Si1-xGexThin Film by Ion Beam Sputtering

    Wang Guangwei, Ru Guoping, Zhang Jianmin, Cao Jihua, Li Bingzong

    Chin. J. Semicond.  2006, 27(5): 846

    Abstract PDF

    Polycrystalline Si1-xGex thin film is deposited on n-Si(100) and SiO2 substrates respectively by ion beam sputtering.The Ge fraction in the Si1-xGexlayer is determined to be 0.15~0.16 by Auger electron spectroscopy.The samples are annealed in a conventional furnace at different temperatures for different durations to investigate temperature and time effects on crystallinity.Phase identification is performed by X-ray diffractometry.It is found that the Si1-xGexfilm has a higher crystallinity on n-Si than on SiO2 under identical annealing conditions.The dependences of the average grain size on annealing temperature and time are exponential and parabolic functions, respectively,as determined by curve fitting.Thus the crystallization process of ion beam sputtered Si1-xGex film may be controlled by grain growth.

  • Extraction of Equivalent Oxide Thickness for HfO2 High k Gate Dielectrics

    Chen Yong, Zhao Jianming, Han Dedong, Kang Jinfeng, Han Ruqi

    Chin. J. Semicond.  2006, 27(5): 852

    Abstract PDF

    The equivalent oxide thickness (EOT) of an HfO2 high kdielectric is extracted in two steps.First,a dual-frequency technique is employed for the C-V curve to overcome the effects of leakage current and substrate resistance.Second,an approach using flat-band capacitance is demonstrated for extracting the EOT of a high kdielectric,without the effects of inversion or accumulation capacitance.The relative error between the EOT extracted by this two-step approach and by the quantum corrected Poisson equation is less than 5%,thus validating the approach.

  • A Static-State Model of NPT-IGBTs with Localized Lifetime Control

    Fang Jian, Jiang Huaping, Qiao Ming, Zhang Bo, Li Zhaoji

    Chin. J. Semicond.  2006, 27(5): 857

    Abstract PDF

    A static-state model of NPT-IGBTs with localized lifetime control is proposed,the results of which fit 2D simulation.With this model,the forward characteristics of localized lifetime control NPT-IGBT influenced by the parameters of localized low-lifetime region are discussed in detail.We also systematically explain why the optimized locations of low-lifetime region are different by different localized lifetime control methods in previous reports.

  • Temperature Characteristics of AlGaN/GaN HEMTs Using C-Vand TLM for Evaluating Temperatures

    Wang Chong, Zhang Jinfeng, , Yang Yan, Hao Yue, Feng Qian

    Chin. J. Semicond.  2006, 27(5): 864

    Abstract PDF

    The DC characteristics of AlGaN/GaN HEMTs are measured in a temperature range from 25 to 200℃. On the same wafer, Schottky C-V and transmission line model measurements are carried out at different temperatures.The temperature dependence of the distribution of the two-dimensional electron gas,the sheet resistance,the ohmic specific contact resistance,and the buffer leakage current are analyzed.We conclude that the reduced saturation current is mainly due to the degradation of the electron transport property.The channel leakage current arises from the gate leakage current,and the leakage of the GaN buffer layer plays a secondary role.

  • Numerical Simulation of Si/Si1-xGex Resonant Tunneling Diode at Room Temperature

    Li Tao, Yu Zhiping, Wang Yan, Huang Lei,

    Chin. J. Semicond.  2006, 27(5): 869

    Abstract PDF

    I-V curves of a 35nm p-type Si/Si1-xGex resonant tunneling diode (RTD) are simulated with the quantum hydrodynamic (QHD) model.An integrated difference scheme including the Schafetter-Gummel method,second upwind method,and second-order central difference method is used to discretize the QHD equations,maintaining both accuracy and stability.Investigations of some structural modifications are also carried out.The analytical results indicate that both quantum barrier thickness and hole effective mass affect the NDR characteristics of Si/Si1-xGex RTDs.The simulated peak-to-valley current ratio of 1.14 at 293K agrees with the experimental result when x=0.23.

  • Parameter Extraction of a III-V Compound HBT Model

    Liu Jun, Sun Lingling

    Chin. J. Semicond.  2006, 27(5): 874

    Abstract PDF

    Novel equations in terms of the current of the intrinsic collector and emitter are implemented to improve the fitting ability of a III-V compound HBT model.An equivalent circuit for the HBT under zero- and cold-bias conditions is proposed for the extraction of access resistances and parasitic inductances.In order to determine the intrinsic and extrinsic parts of the base-emitter,base-collector junction capacitances accurately,a novel direct parameter-extraction method based on "cold-bias" S-measurements is developed.After directly extracting the intrinsic collector resistance Rci,this method describes how to extract the intrinsic and extrinsic capacitances from different "cold bias" points.Experimental validation on a GaAs HBT device with a 180μm2 emitter is carried out,and excellent results are obtained up to 40GHz.

  • Breakdown Characteristics of SOI LDMOS High VoltageDevices with Variable Low k Dielectric Layer

    Luo Xiaorong, , Li Zhaoji

    Chin. J. Semicond.  2006, 27(5): 881

    Abstract PDF

    A novel SOI high voltage device structure with a variable low k dielectric layer (VLkD) is proposed.The buried layer is made up of dielectrics with variable k.The vertical electric field of the buried layer and the vertical breakdown voltage are enhanced due to the low dielectric constant.An enhanced dielectric electric field principle is then proposed.The modulation effect of the buried dielectric layer with different k on the surface electric field increases the lateral breakdown voltage.The RESURF criterion for VLkD SOI is developed.The dependence of breakdown characteristics on the structure parameters of VLkD is researched by 2D device simulator.It is shown that an electric field of the buried layer of 248V/μm and breakdown voltage of 295V can be obtained for a VLkD structure with a 2μm thick Si layer and 1μm composite buried layer with kIL=2 and kIH=3.9.The electric field of the buried layer and breakdown voltage are enhanced by 93% and 64%,respectively, compared to conventional SOI with a 1μm buried oxide layer.

  • Breakdown Voltage Analysis for a Double Step Buried Oxide SOI Structure

    Duan Baoxing, Zhang Bo, Li Zhaoji

    Chin. J. Semicond.  2006, 27(5): 886

    Abstract PDF

    A novel structure with a double step buried oxide SOI (D-SBOSOI) is developed on the basis of single step buried oxide structure.The relation of three times the vertical electric field between the silicon and buried oxide in conventional structure has been broken due to charge accumulation on the step buried oxide in D-SBOSOI,resulting in an electric field of 200V/μm in the buried oxide.Furthermore,the surface electric field in this structure reaches nearly ideal uniform distribution due to the additive electric field modulation by double step buried oxide.The results show that the breakdown voltage is increased because the vertical and lateral fields are optimized in this structure by virtue of 2D MEDICI simulation.

  • Design of Silicon Spiral Inductors Used for 5~6GHz Wireless LAN

    Sun Longjie, Yang Bo, Guo Lihui

    Chin. J. Semicond.  2006, 27(5): 892

    Abstract PDF

    A method for designing and optimizing the construction of inductor layout is presented.A set of 5.7GHz inductors with low resistivity silicon substrate is designed with 0.18μm Cu/SiO2 interconnect process technology.The layout structures such as the inner core size,coil-width,and coil-space of the inductors (0.2~11nH) are optimized.Compared to general methods,this method improves the Q of the 5.7GHz inductors to 5~8.

  • Characteristics of a Front-Illuminated Visible-Blind UV PhotodetectorBased on GaN p-i-n Photodiodes with High Quantum Efficiency

    You Da, Tang Yingwen, Zhao Degang, Xu Jintong, Xu Yunhua, Gong Haimei

    Chin. J. Semicond.  2006, 27(5): 896

    Abstract PDF

    AlxGa1-xN/GaN hetero-epitaxial front-illuminated visible-blind UV photodetectors with very high external quantum efficiency are fabricated and characterized.Light between 340~365nm can be absorbed by i-layer by penetrating the p-AlGaN layer,so the quantum efficiency can be greatly enhanced.Then the effect of the p-AlGaN thickness on the characteristics of the detector is investigated,and two devices with different p-AlGaN thicknesses (0.1μm,0.15μm) are fabricated.The measurements show that the p-AlGaN thickness can only affect the responsivity of 200~340nm light,and the quality of the i-GaN layer can greatly affect the responsivity of 340~365nm light.The device with 015μm thick p-AlGaN has much higher quantum efficiency in the 340~365nm range, and the zero-bias peak responsivity is about 0.214A/W at 365nm,corresponding to an external quantum efficiency of 856%.Moreover,this device exhibits a low dark current density of 3.16nA/cm2 at zero-bias, which indicates that the device has a very high SNR

  • Voltage Controlled Oscillator

    Li Li, Zhao Zhengping, Zhang Zhiguo, Guo Wensheng, Lü Miao, Yang Ruixia

    Chin. J. Semicond.  2006, 27(5): 900

    Abstract PDF

    A 2GHz LC VCO is fabricated using a micromachined variable capacitor for frequency tuning.The MEMS variable capacitors,whose controlling plates and capacitor plates are separated,are fabricated in a surface micromachining process.These devices have a quality factor of 38.462 at 2GHz.The MEMS VCO operating at 2.007GHz achieves a single side band phase-noise of -107.5dBc/Hz at a 100kHz offset from the carrier and an output power of -13.67dBm.On the basis of analysis of VCO mechanical-thermal noise produced from the micromachined variable capacitor,a method for lowering the phase noise by reducing the squeeze damping is proposed and an optimized number of damping holes is obtained.

  • Recombination Width and External Quantum Efficiency in Organic Electro-Phosphorescent Devices

    Dai Guozhang, Li Hongjian, Dai Xiaoyu, Pan Yanzhi, Xie Qiang, Peng Jingcui

    Chin. J. Semicond.  2006, 27(5): 905

    Abstract PDF

    Based on the experience formula and the triplet (T) -triplet (T) annihilation processes,an analytical model to calculate the recombination width and the external quantum efficiency of doped organic electrophosphorescence (EPH) devices is presented.The influences of applied bias,current density, and device thickness on the width of the recombination zone and the external quantum efficiency are studied thoroughly.It is found that:(1) as the applied voltage increases,the recombination width of the device decreases and the external quantum efficiency increases;(2) with increasing the thickness of the device,the recombination width increases accordingly,and the external quantum efficiency behaves differently at different applied voltages;(3) the external quantum efficiency decreases significantly with increasing the recombination current density.

  • Bifurcation and Dynamic Stability of a Light-InjectionMQW Semiconductor Laser

    Yan Senlin

    Chin. J. Semicond.  2006, 27(5): 910

    Abstract PDF

    The bifurcation,dynamic stability,and other properties of a four-dimensional model of an external light injection multi-quantum-well (MQW) semiconductor laser are studied.Bifurcation is numerically simulated via varying the external injection light intensity,the frequency detuning,the linewidth enhancement parameter,and the drive current of the laser.The route to chaos from bifurcation,single-period,and multi-period is illustrated,and a chaotic spectrum is also shown.The maximum locking frequency domain formula is given.A perturbation equation for a four-dimensional model of an external light-injection MQW laser,and eigenvalue equation and its root are demonstrated.The Hopf bifurcation condition of the laser is theoretically given.The dynamic stability of the laser is theoretically and numerically analyzed.Laser oscillation frequencies in single-period,dual-period,and hexa-period states are obtained by simulation.

  • Energy Band Design for a Terahertz Si/SiGe Quantum Cascade Laser

    Lin Guijiang, Lai Hongkai, Li Cheng, Chen Songyan, Yu Jinzhong

    Chin. J. Semicond.  2006, 27(5): 916

    Abstract PDF

    The eigenenergies of confined states in Si/SiGe/Si quantum wells are calculated with nextnano3 software for the design of terahertz Si/SiGe QCLs.The results indicate that the structure of the Si/SiGe quantum cascade may be optimized by using a strain-symmetric heterostructure consisting of a Si1-xGex(0.27<x<0.3) well with a width of 3nm and a Si barrier with a width of 3nm.

  • Enhancement of Light Extraction of LED by Photonic Crystal Structures

    Du Wei, Xu Xingsheng, Sun Zenghui, Lu Lin, Gao Junhua, Zhao Zhimin, Wang Chunxia, Chen Hongda

    Chin. J. Semicond.  2006, 27(5): 921

    Abstract PDF

    The band structure of a 2D infinite photonic crystal is calculated using the FDTD method.Slab photonic crystals with InP are fabricated.Two fabrication methods--one using only PMMA as mask and one using PMMA and SiO2 as masks are used.The results show that the first method cannot yield an accurate pattern transfer,while the other method can.The extraction efficiency in an LED is enhanced successfully by use of the photonic crystal.The light extraction efficiency of the LED with the photonic crystal structure is twice as high as that of the unprocessed sample under the same testing conditions.Along with the increase of lattice constant,the extraction efficiency also increases.

  • Effect of Manufacturing Tolerances on Characteristics ofArrayed Waveguide Grating Multiplexers

    Qin Zhengkun, Ma Chunsheng, Li Delu, Zhang Haiming, Zhang Daming, Liu Shiyong

    Chin. J. Semicond.  2006, 27(5): 926

    Abstract PDF

    The effects of manufacturing tolerances on transmission characteristics are analyzed for a 3333 polymer arrayed waveguide grating (AWG) multiplexer via transmission theory. Simulated results show that manufacturing tolerances result in a shift of the transmission spectrum and in the increase of the crosstalk compared with theoretical device. The accumulation and compensation of manufacturing tolerances are investigated. In order to realize the normal demultiplexing for a fabricated AWG device, some allowed manufacturing tolerances are discussed.

  • Measurement of Luminous Flux of Blue LEDs Using Spectral-Correction-Integral-Photometry Method

    Pan Jiangen, Shen Haiping, Feng Huajun

    Chin. J. Semicond.  2006, 27(5): 932

    Abstract PDF

    A spectral-correction-integral-photometry method and its application in the measurement of the luminous flux of blue LEDs are introduced.The sources of uncertainty in the measurements are theoretically analyzed.Compared to the uncertainties of the spectrophotometry method and the integral method,the results show that this method can achieve high measurement accuracy.It is important to the assessment of the LEDs’ qualities.

  • Fabrication of Self-Testable Pressure Sensors Based on Phase Change

    Huo Mingxue, Tang Xiaochuan, Yin Liang, LiuXiaowei, Wang Xilian

    Chin. J. Semicond.  2006, 27(5): 937

    Abstract PDF

    A novel self-testable method, thermo-pneumatic actuation,which is based on phase change,is presented.It can be used in large-scale self-testable pressure sensors.The phase change material (PCM) fills the cavity of the sensor.Applying voltage to the heating resistor,the PCM will be brought to boil.The vapor inside the cavity of the pressure sensor produces a significant pressure on the diaphragm,so a self-test is implemented by means of a thermal actuator based on the phase change.By the magnitude of the PCM that fills the cavity and the power of the heating resistor,the self-testing of the pressure sensors with different measurement range can be achieved.Based on this principle,a novel large-scale self-testable pressure sensor is fabricated.The sensor is built in a silicon-glass-silicon sandwich structure by anodic bonding.The self-testing output of the sensor is 6.8% of the full-scale output,and the accuracy is 2.1‰.

  • A Transient Method for Testing Thermoelectric Coolers

    Gong Changmeng, Chen Zhen, Wu Zhou, Chang Guoqiang, Qian Ruiming, Chen Yunfei

    Chin. J. Semicond.  2006, 27(5): 944

    Abstract PDF

    The figure of merit ZT,maximum temperature difference,and response time are important parameters for thermoelectric coolers.A transient method for testing these parameters is introduced,and the effect of the heat sink is also discussed.The resistance and Seebeck voltages used to calculate the ZT and the maximum temperature difference are measured using a testing system composed of a DC pulse generator and a DAQ card.The transient method is simple and accurate,and can be used to test thin film thermoelectric coolers.In addition,this method spends very little time.Thus,it can shorten the reliability test period for thermoelectric coolers.A 4mm×4mm×2.4mm commercial thermoelectric cooler is tested using this method.A figure of merit ZT of 0.39,maximum temperature difference of 58.5K,and response time of 20s is measured.

  • Design of a Monolithic Hot Swap Controller IC with BCD Technology

    Wu Xiaobo, Zhang Yongliang, Zhang Danyan, Yan Xiaolang

    Chin. J. Semicond.  2006, 27(5): 948

    Abstract PDF

    To avoid the faults arising from hot board insertion,which may lead to the damage of the board and the backplane and even give rise to the collapse of the system in the worst-case scenario,a hot swap controller IC is developed to ensure the safe insertion and removal of a circuit board from a live backplane.To prevent over current/over voltage and surge current faults,multi protections for both the board and backplane,including a limit on the automatic starting current, a circuit breaker that triggers in the event of over current faults,and the driving of an SCR crowbar to protect the loads in the event of over input voltage faults,are proposed and realized.The under-voltage detecting and output voltage monitoring are also available for its use.After the optimization of the system,circuit,and layout design,the IC is realized in BCD (bipolar-CMOS-DMOS) technology,which is able to operate under a very high voltage and drive current.The chip area is about 2.5mm×2.0mm.It works normally under the range of 4.5 to 16.5V and consumes 18mW at 12.0V.The test results show that the expected functions are achieved and main features meet the requirements well.


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