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Volume 27, Issue 7, Jul 2006

    LETTERS

  • Refinement of an Analytical Approximation of the Surface Potential in MOSFETs

    Lu Jingxue, Huang Fengyi, Wang Zhigong, Wu Wengang

    Chin. J. Semicond.  2006, 27(7): 1155

    Abstract PDF

    A refinement of an analytical approximation of the surface potential in MOSFETs is proposed by introducing a high-order term.As compared to the conventional treatment with accuracy between 1nV and 0.03mV in the cases with an oxide thickness tox=1~10nm and substrate doping concentration Na=1E15~1E18cm-3,this method yields an accuracy within about 1pV in all cases.This is comparable to numerical simulations,but does not require trading off much computation efficiency.More importantly,the spikes in the error curve associated with the traditional treatment are eliminated.

  • A Wide-Band High-Linearity Down-Conversion Mixer for Cable Receptions

    Gu Ming, Shi Yin, Dai F F

    Chin. J. Semicond.  2006, 27(7): 1159

    Abstract PDF

    We analyze a wide-band,high-linearity down-conversion mixer for cable receptions that is implemented in 0.35μm SiGe BiCMOS technology.The bandwidth of the RF (radio frequency) input covers the range from 1 to 1.8GHz.The measured input power at the -1dB compression point of the mixer reaches +14.23dBm.The highest voltage conversion gain is 8.31dB,while the lowest noise figure is 19.4dB.The power consumed is 54mW with a 5V supply.The test result of the down-conversion mixer is outlined.

  • Design and Implementation of a Novel Area-Efficient Interpolator

    Peng Yunfeng, Kong Derui, Zhou Feng

    Chin. J. Semicond.  2006, 27(7): 1164

    Abstract PDF

    This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter.In an effort to reduce the area and design complexity,a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified.The proposed subfilter structure further minimizes the arithmetic number.Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability.The interpolation filter can be applied to a delta-sigma DAC and is fully functional.

  • PAPERS

  • Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

    Wang Wei, Sun Jianping, Gu Ning

    Chin. J. Semicond.  2006, 27(7): 1170

    Abstract PDF

    A quantum model based on solutions to the Schrdinger-Poisson equations is developed to investigate the device behavior related to gate tunneling current for nanoscale MOSFETs with high-k gate stacks.This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance.Comparisons are made for gate current behavior between nMOSFET and pMOSFET high-k gate stack structures.The results presented are consistent with experimental data,whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.

  • An Analytical Model for the Surface Electrical Field Distribution and Optimization of Bulk-Silicon Double RESURF Devices

    Li Qi, Li Zhaoji, Zhang Bo

    Chin. J. Semicond.  2006, 27(7): 1177

    Abstract PDF

    A new 2D analytical model for the surface electrical field distribution and optimization of bulk-silicon double RESURF devices is presented.Based on the solution to the 2D Poisson's equation,the model gives the influence on the surface electrical field of the drain bias and structure parameters such as the doping concentration,the depth and the position of the p-top region,the thickness and the doping concentration of the drift region,and the substrate doping concentration.The dependence of breakdown voltage on the length and doping concentration of the drift region is also calculated.Further more,an effective way to gain the optimum high-voltage is also proposed.All analytical results are verified by simulation results obtained by MEDICI and previous experimental data,showing the validity of the model presented here.

  • A 16 bit Stereo Audio ΣΔ A/D Converter

    Chen Lei, Zhao Yuanfu, Gao Deyuan, Wen Wu, Wang Zongmin, Zhu Xiaofei

    Chin. J. Semicond.  2006, 27(7): 1183

    Abstract PDF

    A 16 bit stereo audio novel stability fifth-order ΣΔ A/D converter that consists of switched capacitor ΣΔ modulators,a decimation filter,and a bandgap circuit is proposed.A method for the stabilization of a high order single stage ΣΔ modulator is also proposed.A new multistage comb filter is used for the front end decimation filter.The ΣΔ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB.The ADC was implemented in 0.5μm 5V CMOS technology.The chip die area occupies only 4.1mm×2.4mm and dissipates 90mW.

  • A 1.1GHz LC VCO with Automatic Amplitude Control for Tuner Applications

    Yan Jun, Mao Wei, Ma Desheng, Gu Ming, Xu Qiming, Hu Xueqing, Shi Yin, Dai F F

    Chin. J. Semicond.  2006, 27(7): 1189

    Abstract PDF

    This paper presents an LC VCO with auto-amplitude control (AAC),in which pMOS FETs are used,and the varactors are directly connected to ground to widen the linear range of Kvco.The AAC circuitry adds little noise to the VCO but provides it with robust performance over a wide temperature and carrier frequency range.The VCO is fabricated in a chartered 50GHz 0.35μm SiGe BiCMOS process.The measurements show that it has -127.27dBc/Hz phase noise at 1MHz offset and a linear gain of 32.4MHz/V between 990MHz and 1.14GHz.The whole circuit draws 6.6mA current from 5V supply.

  • Accurate Interconnection Length and Routing Channel Width Estimates for FPGAs

    Gao Haixia, Ma Xiaohua, Yang Yintang

    Chin. J. Semicond.  2006, 27(7): 1196

    Abstract PDF

    We study the problem of the prediction of interconnection dimensions for FPGAs,including estimating interconnection length and channel width.Experimental results show that our estimates are more accurate than those of existing methods.

  • Full-Chip Scalable Routing Framework Considering Congestion and Performance

    Yao Hailong, Cai Yici, Hong Xianlong, Zhou Qiang

    Chin. J. Semicond.  2006, 27(7): 1201

    Abstract PDF

    This paper presents a novel full-chip scalable routing framework that simultaneously considers the routing congestion and the circuit performance.In order to bridge the gap,the presented framework calls the detailed router immediately after a global route is extracted.With the interleaving mode of global routing immediately followed by detailed routing,accurate routing resource and congestion information can be obtained,which provides valuable guidance for the following global routing process.The framework features the fast pattern and framed shortest path global router,a maze-based congestion-driven detailed router,and better interaction between the two routers.In the framework,timing critical nets can be assigned higher priority for performance concern,and different net ordering techniques can be adopted for different routing objectives.The framework is tested on a set of commonly used benchmark circuits and compared with a previous multilevel routing framework.Experimental results show that the presented framework obtains significantly better routing solutions than the previous one considering circuit performance,routing completion rate,and runtime.

  • Infrared Spectrum of Nitrogen-Vacancy Complexes in Nitrogen-Implanted Silicon

    Chen Hailong, Wang Lei, Ma Xiangyang,

    Chin. J. Semicond.  2006, 27(7): 1209

    Abstract PDF

    Nitrogen ions are implanted into silicon wafer on both sides,followed by rapid thermal processing (RTP) at different temperatures.Fourier transform infrared spectroscopy (FTIR) is employed to characterize the nitrogen behavior in the as-nitrogen-implanted silicon and RTP-treated nitrogen-implanted silicon samples.It is found that four new IR absorption bands appear in the FTIR spectra of the nitrogen-implanted silicon subjected to RTP at 750~900℃,which are believed to be related to nitrogen-vacancy complexes.Theoretical calculation based on a specific atomic configuration model shows that among the newly observed four IR absorption bands there are two bands that are related to the N2V2 complex.

  • Synthesis and Spectral Properties of InP Colloidal Quantum Dots

    Zhang Daoli, Zhang Jianbing, Wu Qiming, Yuan Lin, Chen Sheng

    Chin. J. Semicond.  2006, 27(7): 1213

    Abstract PDF

    InP colloidal quantum dots(QDs) are prepared using the dehalosilylation reaction of InCl3·4H2O and P(Si(CH3)3)3 in trioctylphosphine oxide (TOPO).The TOPO is used as capping groups and colloidal stabilizer,and the dodecylamine added during the later period of the reaction period is used as surfactant.Particle size,crystallinity,lattice structure,morphology,and size distributions are measured using powder X-ray diffraction and transmission electron microscopy.The optical properties are characterized with photoluminescence and ultraviolet spectrometers.These results indicate that the average diameter of the QDs,which possess good crystallinity and size distribution,is 2.5nm,and hence they clearly exhibit quantum confinement effect.

  • Optical and Electrical Properties of ZnO/PS Heterostructure

    Zhao Bo, Li Qingshan, Zhang Ning, Chen Da, Zheng Xuegang

    Chin. J. Semicond.  2006, 27(7): 1217

    Abstract PDF

    The optical and electrical properties of ZnO/porous Si (PS) heterostructure are studied.The PS sample is formed by the anodization of a single-crystal Si wafer.ZnO films are then deposited on the PS substrate by pulsed laser deposition.White light formed by combining the red emission from the PS layers with the blue-green emission from the ZnO films is obtained.Due to the roughness of the PS surface,some cracks appear in the ZnO films,which can be seen from the SEM spectra.The I-V characteristics of the ZnO/PS heterostructure are different from those of the common diode,whose reverse current is not saturated.Based on the I-V characteristics,an energy band diagram is proposed.

  • Effect of Growth Temperature on Properties of ZnO Thin Films

    Su Hongbo, Dai Jiangnan, Pu Yong, Wang Li, Li Fan, Fang Wenqing, Jiang Fengyi

    Chin. J. Semicond.  2006, 27(7): 1221

    Abstract PDF

    High quality ZnO thin films are grown on Al2O3 (0001) substrates by atmospheric-pressure metal organic chemical vapor deposition (AP-MOCVD).Effects of growth temperature on the structure,optical characteristics of ZnO thin films are investigated by double crystal X-ray diffraction (ω and θ-2θ scans) and room temperature photoluminescence(PL) spectra.With the rise of the growth temperature,the c-axis lattice constant of the ZnO films increases while the bandgap becomes wider.

  • Fabrication of ZnO Nanowires by Vapor-Phase Deposition and Their Field Emission Properties

    Zhang Qifeng, Rong Yi, , Chen Xianxiang, Zhang Gengmin, Zhang Zhaoxiang, Xue Zengquan

    Chin. J. Semicond.  2006, 27(7): 1225

    Abstract PDF

    Unoriented ZnO nanowires are fabricated either on the surface of silicon wafer or at the tip of needle-like tungsten by vapor-phase deposition.Both the plane field emission and tip field emission of ZnO nanowires are studied using a field emission microscope.The results show that for unoriented ZnO nanowire thin films,the electric field intensities corresponding to the turn-on voltage and threshold voltage of field emission are 4.7 and 7.6V/μm,which are much lower than those of aligned nanowire arrays.The enhancement of the field emission ability is attributed to the fact that the field-induced screening effect can be effectively avoided due to the widely spaced intervals that exist between the unoriented nanowires.The field emission of the tungsten tip also can be effectively improved by assembling ZnO nanowires on the tip,which presents a potential application of ZnO nanowire on the probe of electron microscopes with ultrahigh resolution.

  • Influence of Doping Level on the Gauge Factor of Polysilicon Nano-Film

    Chuai Rongyan, Liu Xiaowei, Huo Mingxue, Song Minghao, Wang Xilian, Pan Huiyan

    Chin. J. Semicond.  2006, 27(7): 1230

    Abstract PDF

    For the purpose of aiding the development of effective MEMS strain sensors using polysilicon nano-film,we investigate the relationship between the B-doped concentration and the gauge factor of LPCVD-grown polysilicon nano-film and analyze the structure of the film via scanning electron photomicrographs and X-ray diffraction-spectra.Experiments show that under a heavy doping condition,the gauge factor of the nano-film is significantly larger than that of monocrystalline silicon with the same doping level,and when the doping concentration is around 2.5E20cm-3,the gauge factor of the film increases with the increase of the doping concentration.These results are explained by the tunneling effect.A modified model of piezoresistive properties for polysilicon is then presented constructively.

  • Structural and Optical Properties of CdTe Thin Films on Glass Grown by Hot Wall Vacuum Deposition

    Yao Zhaohui, Chen Tingjin, Xia Chaofeng, Yuan Hairong, Liu Zuming, Liao Hua, Wang Fan

    Chin. J. Semicond.  2006, 27(7): 1236

    Abstract PDF

    CdTe thin films with different thicknesses are prepared on well-cleaned glass by hot wall vacuum deposition,and their structural and optical properties are measured.XRD results show that the films are polycrystalline with a typical cubic phase structure and preferred orientation of (111).The lattice constant is 0.649nm for a 17.87μm film,which matches the standard value well.The transmittance spectra and the reflection spectra are measured with a Cary 5000 double beam spectrometer from 200 to 1200nm,and both the absorption coefficient and the extinction coefficient as well as the refractive index are discussed in the intrinsic absorption region.A plot of (hνα)2 versus hν is used to determine the optical energy gap of the CdTe thin films.It is found that the optical energy gap decreases with the increase of film thickness,possibly due to a larger grain size.These results confirm that CdTe is a direct gap material with a high absorption coefficient in the intrinsic absorption region.

  • Study of Sublimation Crystal Growth of Bulk AlN

    Zhao Youwen, Dong Zhiyuan, Wei Xuecheng, Duan Manlong, Li Jinmin

    Chin. J. Semicond.  2006, 27(7): 1241

    Abstract PDF

    Experimental results of bulk AlN crystal growth by physical vapor transport (PVT) and its characterization are presented.A growth temperature of 1900℃ is reached by RF coil heating of the AlN source material contained in a BN crucible.Thin needle crystals and dense polycrystals are obtained in this case.It is difficult to grow large AlN crystals using a BN crucible.A growth temperature of 2200℃ is reached by RF induction heating of the source material contained with a tungsten crucible.AlN crystals in a diameter of 22mm are grown on AlN ceramic plate and 6H-SiC wafer,respectively,of which the largest grain size is 10mm in length and 5mm in diameter.The structure and component of several AlN samples are analyzed using X-ray powder diffraction.The chemical thermodynamic process and growth phenomena related to the AlN PVT growth are discussed.

  • Study of Bottom-Gate μc-Si TFTs

    Li Juan, Zhang Xiaodan, Liu Jianping, Zhao Shuyun, Wu Chunya, Meng Zhiguo, Zhang Fang, Xiong Shaozhen

    Chin. J. Semicond.  2006, 27(7): 1246

    Abstract PDF

    The incubation layer is the key factor in the growth of microcrystalline silicon (μc-Si) film used as the active layer of μc-Si TFT,which is confirmed by experimental results in detail.We find that decreasing the silicon concentration (Sc) is one effective way to thin the incubation layer.We also find that SiNx,used as the gate-insulator-layer of the bottom gate TFT,can increase (by about 20%) the crystalline volume factor (Xc) of μc-Si thin film deposited thereon.Therefore,while depositing μc-Si on SiNx to fabricate the bottom gate TFT,this effect must be taken into account.As a result,to obtain excellent performance from a bottom-gate μc-Si TFT,the appropriate Sc for the active-layer must be no less than 3%.According to the relation between the Xc of μc-Si film and its deposition condition,it can be seen clearly that under the same deposition condition,the difference between the Xc value of μc-Si film deposited on glass and that on SiNx for the active layer in TFT is ~0%,which indicates the augmenting role of SiNx in the crystalline growth of μc-Si thin film.

  • High-Temperature Transport Properties of 2DEG in AlGaN/GaN Heterostructures

    Tao Chunmin, Tao Yaqi, Chen Cheng, Kong Yuechan, Chen Dunjun, Shen Bo, , Jiao Gang, Chen Tangsheng, Zhang Rong

    Chin. J. Semicond.  2006, 27(7): 1251

    Abstract PDF

    The transport properties of the two-dimensional electron gas (2DEG) in fully strained and a partially strain-relaxed Al0.22Ga0.78N/GaN heterostructures at temperatures ranging from 300 to 680K are investigated with Hall measurements.The results indicate that the 2DEG mobility is primarily limited by LO phonon scattering processes at high temperatures.The calculated results also show that the 2DEG distribution gradually expands to the inside of the AlGaN and GaN layers with increasing temperature due to the electron transfer to the higher order subbands. Hence, the effect of screening on LO phonon scattering is weakened and the alloy scattering of the AlGaN layer on the 2DEG becomes stronger.

  • Output Power of an AlGaN/GaN HFET on Sapphire Substrate

    Zhang Zhiguo, Yang Ruixia, Li Li, Feng Zhen, Wang Yong, Yang Kewu

    Chin. J. Semicond.  2006, 27(7): 1255

    Abstract PDF

    The low breakdown voltage of AlGaN/GaN HFETs,which is caused by the poor buffer layer of GaN epitaxial wafer,is improved through mesa isolation and implantation isolation.Annealing at 500℃ for 50s after the gate metal deposition yields the best performance for an Ni-AlGaN/GaN diode.In particular,the ideality factor and barrier height reach 1.5 and 0.87eV,respectively.Optimization is achieved by comparing the performance of the gate and output power of AlGaN/GaN HFETs fabricated under different conditions.The output power of a 1mm-gate-wide AlGaN/GaN HFET on sapphire substrate is 4.57W, with a power added efficiency of 55.1% at 8GHz.

  • C-V Characteristic Distortion in the Pinch-Off Mode of a Buried Channel MOS Structure in 4H-SiC

    Gao Jinxia, Zhang Yimen, Zhang Yuming

    Chin. J. Semicond.  2006, 27(7): 1259

    Abstract PDF

    The distortion of the C-V characteristics of a SiC buried-channel MOS structure is presented.It is difficult to characterize the gate capacitance because there is a pn junction in buried-channel MOSFETs.The surface depletion region and n-side space-charge region merge when the channel is punched through.In this case,the total surface capacitance is the sum of the surface depletion region capacitance and the pn junction capacitance,and the C-V characteristics are distorted.The analytic expression of gate capacitance in the pinch-off mode is obtained by solving Poisson’s equation.The C-V characteristics in the pinch-off mode are analyzed on a fundamental physical level.The gate capacitance calculated with the model agrees well with experimental results.

  • A New Direct Tunneling Gate Current Model for Short Channel MOSFETs with HALO Structure

    Zhao Yao, Xu Mingzhen, Tan Changhua

    Chin. J. Semicond.  2006, 27(7): 1264

    Abstract PDF

    The direct tunneling current of a short channel MOSFET with a HALO structure is investigated, and a new direct tunneling gate current model is obtained.It is found that the extension regions of the gate/source and gate/drain decrease the direct tunneling gate current density because the flat band voltage between the gate/source and gate/drain is higher than that of the substrate.The extension regions reduce direct tunneling current continuously as the channel length decreases.A new direct tunneling gate current model is obtained by comparing the simulation and experimental results.This model is applicable to the devices with an ultra thin gate oxide (2~4nm),a short channel (0.13~0.25μm),and a HALO structure.

  • Output Characteristics of a Buried n Layer RF Power PSOI LDMOS

    Wang Xiaosong, Li Zehong, Wang Yiming, Zhang Bo, Li Zhaoji

    Chin. J. Semicond.  2006, 27(7): 1269

    Abstract PDF

    A novel buried n layer partial SOI RF power LDMOS is proposed.The output characteristics of the RF power LDMOS are greatly affected by the parasitic capacitance.Because the depletion width under the buried oxide layer of the proposed structure increases,the output capacitance decreases.Its drain-substrate capacitance is 39.1% and 26.5% less than that of the normal LDMOS and the partial SOI LDMOS respectively.At the 1dB compression point,its output power and power gain are 62% and 11.6% higher than those of the partial SOI LDMOS respectively,and the power-added efficiency of the proposed structure increases from 34.1% to 37.3%.The breakdown voltage of the proposed structure is 14% higher than that of the bulk structure.

  • A Novel Structure with Multiple Equipotential Rings for Shielding the Influence of a High Voltage Interconnection

    Chen Wanjun, Zhang Bo, Li Zhaoji

    Chin. J. Semicond.  2006, 27(7): 1274

    Abstract PDF

    A novel structure with multiple equipotential rings(MER-LDMOS) for shielding the influence of a high voltage interconnection(HVI) is proposed,and its shielding model is explained and proved with 2D device simulation.The influences of various factors on the breakdown voltage of MER-LDMOS are discussed in detail,including the p-top dose,the length of equipotential ring,the distance between the equipotential rings,and the thickness of the SiO2.A significant increase in the breakdown voltage is realized using the MER-LDMOS structure,and its breakdown voltage increases by more than 100% compared with that of conventional LDMOS.Furthermore,the proposed structure has the advantages of simple fabrication,large process tolerance,and small leakage current.It is a new method for shielding the influence a high voltage interconnection in a high voltage integrated circuit.

  • Time Dependence of Radiation Damage in Bipolar Operational Amplifiers

    Gao Song, Lu Wu, Ren Diyuan, , Niu Zhenhong

    Chin. J. Semicond.  2006, 27(7): 1280

    Abstract PDF

    The time dependence of radiation damage in bipolar op-amps is studied through a series of radiation experiments.The results show that radiation damage in bipolar op-amps is closely related to time,and we can evaluate low-dose rate radiation damage in devices by adjusting radiating the dose rate,annealing temperature,and annealing time parameters to experiment on circulating radiation-anneal.From the interface states point of view,the possible mechanisms of radiation damage are also analyzed.

  • K-Band Monolithic Low Noise Amplifier with High Gain

    Wang Chuang, Qian Rong, Sun Xiaowei

    Chin. J. Semicond.  2006, 27(7): 1285

    Abstract PDF

    Two high gain K band MMIC LNAs (low noise amplifiers) on an advanced 0.25μm PHEMT process are reported.A structure with three cascaded circuits is used for increasing the gate width without limit.Source feed inductors appropriate for obtaining a good noise figure (NF) and high gain are adopted.A new resistor and capacitor network attached to the sources and drains is applied to suppress low frequency oscillations.For convenience, the same set of negative and positive voltage sources is provided through the resistance in the chip to the three-cascade circuit, which performs very well.The values of VSWin and VSWout of LNA2 are less than 2.The small signal gain from 24GHz to 26.5GHz reaches to 24dB and the noise figure (NF) is less than 3.5dB.Both LNAs have wide dynamic ranges and their chip areas are small,with dimensions of 1mm×2mm×0.1mm.The output power of the LNAs is greater than 15dBm at the 1dB compressed point.These LNAs can be employed in front of a 24GHz radar and a 26.5GHz local distribution system (LMDS) .

  • Data Retention in EEPROM Cells

    Cheng Wei, Hao Yue, Ma Xiaohua, Liu Hongxia

    Chin. J. Semicond.  2006, 27(7): 1290

    Abstract PDF

    We present a theoretical and experimental investigation of the date retention ability of EEPROM cells at a given voltage.An expression for EEPROM data retention is derived.The electrical characteristics are presented.The result shows that the data retention time varies linearly with the applied voltage in a log-log plot.Under the assumption that the charge loss mechanism is Fowler-Nordheim tunneling through the thin oxide,the data retention time of EEPROM cells is derived,and the experience formula is checked by experiment.

  • A Photovoltaic Si X-Ray Detector

    Zhang Zhiguo

    Chin. J. Semicond.  2006, 27(7): 1294

    Abstract PDF

    The structure of a vertical multijunction detector is presented.The workmanship conditions and results of thermomigration are presented.The insulation line method of disposing electrode wire is introduced,and the problem of photoetching an electrode after thermomigration is solved.Additionally,the effects of the workmanship conditions on device performance are analyzed.Through contrasting the sensitivity region and the inefficacy region,several current parameters of the vertical multijunction detector are calculated.In particular,the efficiency of collecting photoelectrons excited in the device for two X-ray marker spectra that come from two targets is calculated.The spectrum responsivity of the device is calculated and discussed,and the selection of window material of the device is discussed.Finally,through measuring the simulation defects in the metal mouldboard,the device is proved to have sufficient responsivity and distinguishability.

  • A New Design Method for the Gate-Cathode Layout of GCT

    Wang Cailin, Gao Yong

    Chin. J. Semicond.  2006, 27(7): 1300

    Abstract PDF

    The gate-cathode structures of gate commutated thyristor (GCT) and gate turn-off thyristors are analyzed.Based on the commutation mechanism of a GCT during turn-off,a new design method for the gate-cathode layout of GCT is presented.Compared with the existing method,the new method increases the effective cathode area of GCT,decrease the thermal resistance,and improve the current capability under the precondition of uniform current distribution during turn-off.

  • Theoretical Analysis of a Novel Resonant Cavity Enhanced Modulator with High Extinction Ratio and Low Insertion Loss

    Zhou Zhen, Yu Chongxiu, Ma Jianxin

    Chin. J. Semicond.  2006, 27(7): 1305

    Abstract PDF

    A novel type of resonant cavity enhanced (RCE) modulator,which is composed of a symmetric RCE modulator and an asymmetric F-P cavity,is proposed.The analysis shows that this RCE modulator combines the advantages of symmetric and asymmetric RCE modulators and thus can easily achieve a high extinction ratio and low insertion loss simultaneously.This modulator has a larger variable reflection region under a certain modulation voltage.

  • An Analytical Expression of Free Carrier Lifetime in an SOI Rib Waveguide Used for Raman Amplification

    Chen Mingyi, Mao Luhong, Hao Xianren, Zhang Shilin, Guo Weilian

    Chin. J. Semicond.  2006, 27(7): 1310

    Abstract PDF

    The lifetime of free carriers in a silicon-on-insulator(SOI) rib waveguide,which is used for Raman amplification,is studied in connection with the nonlinear optical loss.An analytical expression for the free carrier lifetime in an SOI rib waveguide with a pin under a reverse bias voltage of zero,which is in accord with others’s experimental results,is presented through theoretical deduction and two-dimensional numerical simulation.The results indicate a maximum reduction of to 80% of the free carrier lifetime inside the waveguide with a pin under a reverse bias voltage of zero compared to the one with no pin.The reason for the further reduction of the free carrier lifetime after reverse biasing the pin is also studied,and the theoretical limit of the free carrier lifetime is obtained through the view of velocity saturation under a strong field.Finally,the net Raman gain of the SOI rib waveguide versus the input pump optical intensity is simulated under different free carrier lifetimes,which directs the study of silicon-based Raman amplification.

  • A Design Technique of Neuron MOS Binary Circuits Based on Multiple-Valued Logic

    Hang Guoqiang

    Chin. J. Semicond.  2006, 27(7): 1316

    Abstract PDF

    A design method for binary neuron MOS circuits employing a summation signal with multiple values is presented.The logical relation of each neuron MOS transistor is formulated using the transmission operation in order to make effective and practical use of the circuits.Using the proposed method,some neuron MOS circuits realizing two-variable common functions and a full adder are designed,and the ratio of the coupling capacitance in each circuit can be calculated conveniently.All the proposed circuits have very simple configurations.Furthermore,the synthesis procedures can be simplified significantly since the voltage signals are added easily by means of floating gates in the neuron MOS transistors.The effectiveness of the proposed approach is validated by HSPICE simulation using TSMC 0.35μm double-polysilicon CMOS technology.

  • 2D Numerical Simulation of Sacrificial Layer Etching

    Li Yanhui, Li Weihua

    Chin. J. Semicond.  2006, 27(7): 1321

    Abstract PDF

    Since the etching mechanism of sacrificial layer is mainly restricted by diffusion,a 2D etching model based on the diffusion equation is constructed and the relative boundary conditions are given.Explicit and implicit numerical algorithms using the finite-difference method are presented to solve the 2D diffusion equation to get the value of the concentration at every site at different times.The topography model is then used to compute the etching state to determine the etch contour at the front.A simulation program that can simulate different complex sacrificial structures is implemented.The simulation is validated by experiments.

  • Three-Dimensional Fabrication by Electron Beam Lithography Using Overlapped Increment Scanning

    Hao Huijuan, Zhang Yulin, Lu Wenjuan, Wei Qiang

    Chin. J. Semicond.  2006, 27(7): 1326

    Abstract PDF

    Overlapped increment scanning in electron beam lithography and the calculation methods for the exposure doses and the etching depth and sensitivity are presented for the structural characteristics of three-dimensional patterns as well as the self-devised pattern generator of an e-beam lithography system.Based on the calculated dose relations according to the scanning mode,the exposure experiments are conducted in an SDS-3 e-beam lithography system.After the development,the distinct three-dimensional structures of the conic of trapezoid 1 and the conic are obtained.Overlapped increment scanning therefore can be used for three-dimensional fabrication,and the calculation of the relations between exposure doses and the etching depth and sensitivity can provide the practical parameters for it.

  • A Pre-Oxidation Cleaning Process to Decrease the Microroughess of Si Wafer Surfaces

    Ku Liming, Wang Jing, Zhou Qigang

    Chin. J. Semicond.  2006, 27(7): 1331

    Abstract PDF

    The microroughness of silicon surfaces after pre-oxidation cleaning is studied using atomic force microscopy,and the cleaning mechanism is analyzed by building surface reaction and oxide layer models.The experimental results show that the oxide layer on a wafer’s the surface can eliminate the anisotropic etching in the ammonia solution.The RMS roughness of the surface is less than that obtained using the traditional RCA process,and it decreases with the increase of ammonia concentration after forming an oxide layer prior to RCA cleaning.

  • Cl2-Based Dry Etching of GaN Using Inductively Coupled Plasma

    Liu Beiping, Li Xiaoliang, Zhu Haibo

    Chin. J. Semicond.  2006, 27(7): 1335

    Abstract PDF

    Inductively coupled plasma (ICP) etching of GaN is carried out with Cl2/He and Cl2/Ar.The effects of ICP power,DC bias,total flow rate,and Cl2∶He ratio on the etch rate and surface morphology are discussed when etching GaN using Cl2/He.Experimental results indicate that the etching rate is very high,and the maximum reaches 420nm/min.The etched surface is very smooth,with an RMS less than 1nm.An SEM photo shows a smooth etched surface and vertical sidewall.The difference between Cl2/He and Cl2/Ar etching under the same conditions,including etch rate,surface morphology,and the ρc of the n-type contact on the etched surface,is investigated

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