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Volume 27, Issue S1, Dec 2006

  • Match and Mixed Lithography Technology Between E-Beam Lithography System and Optical Lithography System

    Chen Baoqin, Liu Ming, Xu Qiuxia, Xue Lijun, Li Jinru, Tang Yueke, Zhao Min, Liu Zhuming, Wang Deqiang, Ren Liming, Hu Yong, Long Shibing, , Lu Jing, Yang Qinghua, Zhang Lihui

    Chin. J. Semicond.  2006, 27(S1): 1

    Abstract PDF

    This paper described the match & mixed lithography technology between E-beam lithography system and optical lithography system.The following contents are illustrated in detail:(1) Match & mixed lithography technology between E-beam and optical system; (2) Match & mixed lithography technology between stepper and JBX-5000 lithography system; (3) Match & mixed lithography technology between contact printers and JBX-5000LS; (4) Big/small electrical beam current or big/small aperture diaphragm mixed lithography technology; (5) Alignment mark making method in match & mixed lithography technology.The technologies mentioned above have extensively been applied in the fields of micro- and nano- manufacture.As the results,we realized the 20nm line,27nm gate CMOS transistor,50nm island SET,100nm gate HEMT and other nanometer level devices.

  • Nano Electrical Devices and Integration

    Liu Ming, Chen Baoqin, Xie Changqing, , Wang Congshun, Long Shibing, Xu Qiuxia, Li Zhigang, Yili Chengrong

    Chin. J. Semicond.  2006, 27(S1): 7

    Abstract PDF

    The progress and challenge on quantum mechanism nano-devices such as single-electron transistors (SET),resonant tuneling diodes(RTD), and molecular devices are investigated and discussed.The SET with CMOS compatible technology is successfully fabricated,and the Coulomb blockade effect is clearly observed.AlAs/GaAs/In0.1Ga0.9As/GaAs/AlAs double-barrier resonant tunneling diodes (DBRTDs) grown on semi-insulated GaAs substrate with molecular beam epitaxy are demonstrated.With ringed collector and thin barriers,the devices exhibit a maximum PVCR of 13.98 and a peak current density of 89kA/cm2 at room temperature.Finally,the progress of molecular memory with cross-bar structure is summarized.


  • Photoluminescence of Electron- and Neutron-Irradiated n-Type 6H-SiC

    Zhong Zhiqin, Gong Min, Wang Ou, Yu Zhou, Yang Zhimei, Xu Shijie, Chen Xudong, Ling Chichung, Fung Hanyuan, Beling C D

    Chin. J. Semicond.  2006, 27(S1): 11

    Abstract PDF

    n-type 6H-SiC materials irradiated with electrons having energies of Ee=1.7,0.5,and 0.4MeV and neutrons are studied via low temperature photoluminescence.For Ee≥0.5MeV electron-irradiated and neutron-irradiated samples,the LTPL emission lines S1/S2/S3 at 478.6/483.3/486.1nm are observed for the first time.Thermal annealing studies show that the defects S1/S2/S3 disappear at 500℃.However,the well-known D1-center is only detected for annealing temperatures over 700℃.By considering the threshold displacement energies of Emin(C) and Emin(Si) and thermal annealing behavior,it is found that the defects S1/S2/S3 are a set of silicon-related primary defects and the D1-center is a kind of secondary defect.

  • Room Temperature Resonant Tunneling and Negative DifferentialResistance Effects in a Self-Assembed Si Quantum Dot Array

    Yu Linwei, Chen Kunji, Song Jie, Wang Jiumin, Wang Xiang, Li Wei, Huang Xinfan

    Chin. J. Semicond.  2006, 27(S1): 15

    Abstract PDF

    We report the room temperature resonant tunneling and negative differential resistance (NDR) effects in a self-assembled Si quantum dot (Si-QDs) array.The double-layer structure of Al/SiO2/Si-QDs/SiO2/p-Si substrate is fabricated by layer-by-layer deposition and in situ plasma oxidation in a plasma-enhanced chemical vapor deposition (PECVD) system.Obvious NDR effects are directly observed in the current-voltage characteristics,and similar peak structures at the same voltage are also identified in the capacitance-voltage characteristics.Both of them are attributed to the resonant tunneling and charging dynamics in the Si-QD array.Moreover,the major features,such as the scan-rate and scan-direction dependences of the peak structure,are investigated,and the underlying mechanism is found to be quite different from that of a quantum well structure.Based on a master-equation numerical model,the resonant tunneling and charging dynamics together with the unique features can be satisfactorily explained and reproduced.

  • Strain Effect on Photoluminescence from InGaN/GaN and InGaN/AlGaN MQWs

    Yu Tongjun, Kang Xiangning, Qin Zhixin, Chen Zhizhong, Yang Zhijian, Hu Xiaodong, Zhang Guoyi

    Chin. J. Semicond.  2006, 27(S1): 20

    Abstract PDF

    Photoluminescence,HR-XRD,and Raman scattering spectra of InGaN/GaN MQWs and InGaN/AlGaN on sapphire and membranes with no substrate fabricated by laser lift-off are studied.In contrast to the emission peak from the membrane samples of InGaN/GaN MQWs,which blue-shifts after annealing at 700℃,a red-shift of the PL peak position in the InGaN/AlGaN MQW membrane sample is observed,showing different strain effects in these MQWs.In Raman scattering spectra,the InGaN/GaN MQW film without sapphire substrate has a lower E2 mode frequency (567.5cm-1) than that of the films with substrate (569.1cm-1),which indicates that the compressive stress in the films is released partially when the sapphire substrate is taken off.

  • Photoluminescence of nc-Si/SiN Superlattices Embeddedin Optical Microcavities

    Chen San, Qian Bo, Chen Kunji, Cen Zhanhong, Liu Yansong, Han Peigao, Ma Zhongyuan, Xu Jun, Li Wei, Huang Xinfan

    Chin. J. Semicond.  2006, 27(S1): 25

    Abstract PDF

    We fabricate a-Si/a-SiNz superlattices and a one-dimensional amorphous silicon nitride photonic crystal microcavity by plasma enhancement chemical vapor deposition (PECVD).To improve the light-emitting efficiency of the nc-Si/a-SiNz superlattices,which are made from a-Si/a-SiNz superlattices by laser annealing,an nc-Si quantum dot array is inserted into the photonic crystal microcavity.Raman spectroscopy and transmission electron microscopy analysis show that nc-Si with a size of 4nm,which is close to the designed thickness of the a-Si sublayers,is formed in the a-Si sublayers.Owing to microcavity effects,the PL peak of the nc-Si/a-SiNzsuperlattices embedded in the microcavity is strongly narrowed,and the intensity of the PL is enhanced by two orders of magnitude with respect to the emission of λ/2-thick nc-Si/a-SiNz superlattices.Light emission at a cavity-resonant frequency from the nc-Si/a-SiNz superlattices is enhanced while other frequencies are forbidden.This leads to the narrowing of the PL spectrum and enhancement of the intensity.

  • Design of a Low Noise,Low Power Audio Power Amplifierfor Driving Headphones

    Wei Benfu, Yuan Guoshun

    Chin. J. Semicond.  2006, 27(S1): 29

    Abstract PDF

    This paper describes the design and implementation of a low noise,low power,programmable-gain audio power amplifier used as a headphone driver.It obtains a 0.1% THD+N with a 5V power-supply,a 1kHz frequency audio signal,and a 120mW continuous average output power into a 16Ω load.In addition,the gain can be set from +12 to -34.5dB in 32 discrete steps of 1.5dB.The amplifier is used as the core of a programmable gain audio power amplifier for driving headphones.The audio power architecture,the main module circuits of the amplifier design,the test results,and the chip layout are included.Experimental results using a CSMC 0.6μm double poly double metal CMOS process show that the required performance can be obtained.

  • Comparison of Body-Contact and Patterned-SOI LDMOSFETs for RF Wireless Applications

    Li Wenjun, Cheng Xinhong, Song Zhaorui, Chen Zhanfei, Liu Jun, Sun Lingling

    Chin. J. Semicond.  2006, 27(S1): 32

    Abstract PDF

    A novel patterned-SOI LDMOSFET with a silicon window beneath the p-type channel is designed and fabricated for RF power amplifier applications.It has good DC and RF characteristics,with no kink effect on the output performance,an off-state breakdown of up to 13V,fT=8GHz at a DC bias of VG=4V and VD=3.6V.These characteristics are better than those of body-contact SOI LDMOSFETs on the same wafer with the same process conditions.

  • A Model of the Temperature Dependence of the Fall Time ofa TF SOI CMOS Inverter with EM NMOST and AMPMOST Assemblies at 27~300℃

    Zhang Haipeng, Wei Tongli, Feng Yaolan, Wang Qin, Zhang Zhengfan

    Chin. J. Semicond.  2006, 27(S1): 36

    Abstract PDF

    The temperature dependence of the fall time of an SOI CMOS inverter with EM NMOST and AM PMOST assemblies is modeled approximately in electronics in a high temperature range (27~300℃) in detail.In addition,experiments on the inverter are done at 27,100,150,200,250,and 300℃,respectively,and the measured results are illustrated and discussed simply.They indicate that the inverter is very suitable for high temperature applications up to 300℃ and that its fall time varies only slightly with temperature.If optimization is introduced during its design process,a more symmetrical rise/fall characteristic may be realized,and it could be used at higher frequencies.

  • Design Issues for Cross-Coupled LC Oscillators

    Man Jiahan, Zhao Kun, Ye Qing

    Chin. J. Semicond.  2006, 27(S1): 40

    Abstract PDF

    This paper introduces design issues for cross-coupled LC oscillators.From a physical standpoint,the VCO topology,the amplitude of the tank,the noise source,the phase noise,and the Q factor of the tank are studied.According to these analyses,the design issues and constraints are presented.Finally,the simulation results of a cross-coupled LC oscillator are reported.

  • Effect of Electron-Phonon Interaction on NonequilibriumTransport in Quantum Dot Systems

    Chen Zuozi, Lu Haizhou, Lü Rong,

    Chin. J. Semicond.  2006, 27(S1): 44

    Abstract PDF

    The electron-phonon interaction has important effects on the nonequilibrium transport through the semiconductor quantum dot (QD) or the single molecule transistor.Based on the improved electron-phonon disentangled scheme and the equation of motion approach of the nonequilibrium Green functions,it is found that at low temperature,the phonon sidebands in the spectral function are quite sensitive to the relative positions of the renormalized QD level and the Fermi levels in the leads,showing the broken particle-hole symmetry in the QD.The phonon satellites of the Kondo peak come from two types of spin exchange processes.In the presence of moderate Zeeman splitting,these two types of Kondo satellites can be recognized in the spin resolved spectral function.These features of the spectral functions will also manifest themselves in the nonlinear differential conductance.

  • Influence of Interaction Between Phonons and Magnetic Fieldon Properties of Bound Polaron in a Quantum Dot

    Yu Yifu, Yin Jiwen, Xiao Jinglin

    Chin. J. Semicond.  2006, 27(S1): 49

    Abstract PDF

    The influence of the interaction between phonons and the magnetic filed on the properties of the bound polaron in a semiconductor quantum dot is studied.The ground state energy of the bound magnetopolaron in a semiconductor quantum dot is derived using a linear combination operator and perturbation method.Considering the interaction between phonons of different wave vectors in the recoil process,the influences of the magnetic filed,the Coulomb bound potential,the electron-phonon coupling strength,the effective confinement length of a quantum dot and the interaction between phonons on the ground state energy of the bound magnetopolaron in a semiconductor quantum dot are discussed.Numerical calculation results show that when considering the interaction between phonons the ground state energy of the bound magnetopolaron in a semiconductor quantum dot will increase strongly with decreasing the effective confinement length of the quantum dot.When l0>0.7, the influence of the interaction between phonons on the ground state energy of the bound magnetopolaron in a semiconductor quantum dot can not be ignored in a quantum dot.

  • Temperature Dependences of Polaron in a Parabolic Quantum Wire

    Ding Zhaohua, Zhao Cuilan, Xiao Jinglin

    Chin. J. Semicond.  2006, 27(S1): 54

    Abstract PDF

    Taking into account the interaction of the electron with optical phonon modes,the temperature dependences of polaron in parabolic quantum wires in polar crystals,which are both weak-coupling and strong-coupling,were investigated respectively by using Tokuta’s improved linear combination operator and the variational methods.Numerical calculation for RbCl and CdTe crystals indicated that the effective mass m* of polaron will decrease with increasing of temperature T,the mean number N of optical phonon and vibration frequency λ of polaron will increase with increasing of temperature T.

  • XRD Reciprocal Space Mapping of InAsP/InGaAsP/InP Strain Epilayers

    Huang Zhanchao, Wu Huizhen, Lao Yanfeng, Liu Cheng, Cao Meng

    Chin. J. Semicond.  2006, 27(S1): 58

    Abstract PDF

    The strain state of compressed InAsP and tensile InGaAsP layers,which are grown on (100) InP substrate by molecular beam epitaxy,is investigated through X-ray triple-axis diffraction mapping.(004) and (224) plane diffraction mappings of two materials are tested.The results indicate that partly relaxed InGaAsP epilayer has different strains at different azimuth.Excluding the influence of tilt and strain of epilayer,we accurately calculate the bulk mismatch of InAsP and InGaAsP,which is 1.446% and -0.5849%, respectively.And high quality strain-compensated multiple quantum wells (8) is grown according to these precise parameters.

  • Calculation of Band Gap Structures of 2D Square Lattice Photonic Crystals Using Plan Wave Expansion Method

    Cun Huanyao, Tan Renbing, Wang Rongli, Bai Han, Zhang Xi, Hu Jiaguang, Zhang Jin

    Chin. J. Semicond.  2006, 27(S1): 64

    Abstract PDF

    The band gap structures of two-dimensional (2D) square lattice photonic crystals are calculated using the plan wave expansion method.It gives a detail deduction for the electromagnetic wave theory of 2D photonic crystals and Bloch wave solutions in stratified periodic dielectric.Both TE and TM modes are considered in photonic crystals with no defects consisted of dielectric air cylinders and dielectric columns in air background.We get different dispersion curves,and designed two kinds of 2D photonic crystal periodical structures with band gaps in low-frequency ranges.It is found that the periodic dielectric constructed from air cylinders in Si matrix can generate an absolute photonic band gap in the infrared range for both TE and TM modes.The dependences of air cylinders or silicon rods radius and filling factors in the two kinds of photonic crystals are also studied in TM mode.

  • Photoluminescence Study on Resonant Energy Transfer ProcessBetween Two Sizes of CdTe QDs Embedded in Gelatin Films

    Xu Ling, Ma Zhongyuan, Xu Jun, Huang Xinfan, Chen Kunji

    Chin. J. Semicond.  2006, 27(S1): 68

    Abstract PDF

    Thioglycolic-acid-stabilized CdTe nanocrystals (NCs) are synthesized with wet chemistry method.Energy transfer process between two sizes of CdTe nanoceystals embedded in gelatin films is investigated.Photoluminescence results for the mixed system show that long-range resonance energy transfer (LRRT) between QDs occurs when nanocrystals are in close proximity.From PL results,quenching efficiency-distance curve can be obtained.This critical distance R0=9.5nm from our mixed system agree well with other’s results obtained in solid films.

  • Tight Binding of Photoluminescence in the SiC/nc-Si Multi-Layer Film

    Liang Zhijun, Wang Zhibin, Wang Li, Zhao Fuli, Yang Shenghong, He Zhenhui, Chen Dihu

    Chin. J. Semicond.  2006, 27(S1): 72

    Abstract PDF

    Based on the sp3s tight-binding model proposed by Vogl,the relationship between the band structure and photoluminescence (PL) of the SiC/nc-Si multi-layer is studied.An optimal design of the structure of the SiC/nc-Si multi-layer is presented,theoretically indicating that the {Si}1{SiC}8 supper lattice possesses the highest efficiency of emitting blue light.Multiple SiCx/nc-Si films is fabricated by plasma enhanced chemical vapor deposition and high temperature thermal oxidation.And the structure characteristics of the multiple films is studied by TEM,revealing that the structure of the fabricated multiple films is {Si}1{SiC}5,which is slightly different from the ideal design.Finally,the experimental results of the PL spectrum are analyzed theoretically,and the mechanism of the each light emitting peak is discussed in detail.

  • Photoluminescence During the Crystallization of a-Si∶H/SiO2 Multilayers

    Ma Zhongyuan, Han Peigao, Li Wei, Chen San, Qian Bo, Xu Jun, Xu Ling, Huang Xinfan, Chen Kunji, Feng Duan

    Chin. J. Semicond.  2006, 27(S1): 76

    Abstract PDF

    a-Si∶H/SiO2 multilayers with different thickness of a-Si∶H were layer by layer deposited and in situ plasma oxidized by plasma enhanced chemical vapor deposition system.Size-controlled nc-Si/SiO2 multilayers were obtained through step-by-step thermal annealing of a-Si∶H/SiO2 multilayers including dehydrogenation,rapid thermal annealing,quasi-static annealing.The change of photoluminescence from a-Si∶H/SiO2 to nc-Si/SiO2 was traced through step-by-step post-treatment combined with Raman,FTIR and TEM.The origin of the change of photoluminescence at different stage of thermal annealing is investigated.The relation between the change of photoluminescence and microstructure of the samples is discussed in detail.

  • Formation Process of S-K Quantum Dots

    Yu Like, Xu Bo, Wang Zhanguo, Jin Peng, Zhao Chang, Lei Wen, Hu Liangjun, Liu Ning

    Chin. J. Semicond.  2006, 27(S1): 80

    Abstract PDF

    We grow a single highly inhomogeneous sample of InGaAs quantum dots (QD).The fact that the thickness of the InGaAs layer varies in sample’s different regions leads to an inhomogeneous distribution of QD’s size and density.Such a distribution is well in accordance with the different periods of QD’s formation,which gives us a best view of the whole process of QD’s evolution through a single sample.Atomic force microscopy and photoluminescence spectra show that the size (height and diameter) of the quantum dots becomes narrower and tends to be an equilibrium value when the amount of InGaAs increases.

  • Patterned Growth and Field Emission Properties of ZnO Nanorods

    Chang Zhongkun, Yu Ke, Zhang Yongsheng, Li Lijun, Ouyang Shixi, Zhang Qingjie, Wang Qingyan, Zhu Ziqiang

    Chin. J. Semicond.  2006, 27(S1): 84

    Abstract PDF

    Patterned ZnO nanorods have been first grown on patterned silicon nanocrystallite (SiNC) films that were fabricated on (100) orientation p-type boron-doped silicon wafer by hydrogen ion implantation technique and the anodic etching method,and their field emission properties were obtained.Field emission measurements demonstrated that the synthesized ZnO nanorods have excellent field emission properties,namely low turn-on field,low threshold field,and high emission spot density.The patterned ZnO nanorods have great potential in the application of flat panel displays.

  • Evolution of Micro-Structures on PbSe Buffer Layer and Self-Organization of PbTe QDs

    Xu Tianning, Wu Huizhen, Si Jianxiao, Cao Chunfang, Qiu Dongjiang, Dai Ning

    Chin. J. Semicond.  2006, 27(S1): 87

    Abstract PDF

    PbSe single crystal films are grown on cleaved (111) surface of BaF2 substrate by molecular beam epitaxy.The effects of different Se/PbSe flux ratio (Rf) on morphologies of PbSe films are studied.For PbSe film grown without Se vapor,the surface morphology is characterized by 3D islanding.This feature is changed into triangle holes when low Rf is used,and the dimension of triangle holes decreases as Rf increases.Spirals with monolayer (1ML=0.354nm) steps are observed at Rf=0.6.The diameters in plane of spirals range from 1 to 3μm,and the average step spacing within the spirals is 150nm.The reason for evolution of microstructures on PbSe surface is that the Se vapor has played an important role in the strain relaxation,which can change the growth mode of PbSe films.Finally,we demonstrate the self-organization of PbTe QDs on PbSe buffer layer with the spiral features.The PbTe QDs with two-height distribution are observed.The average heights of the two type PbTe QDs are 11 and 23nm,respectively.

  • Influence of Thermal Annealing on Properties of InGaN Films

    Wen Bo, Jiang Ruolian, Liu Chengxiang, Xie Zili, Zhou Jianjun, Han Ping, Zhang Rong, Zheng Youdou

    Chin. J. Semicond.  2006, 27(S1): 92

    Abstract PDF

    InGaN films with an indium composition of 0.14 grown by metal organic chemical vapor deposition were thermally annealed at different temperature.The evolutions of crystalline property,surface morphology,optical characteristic and electric characteristic of In0.14Ga0.86N films with the annealing temperature were studied by X-ray diffraction,atomic force microscope,photoluminescence,and variable temperature Hall measurements.By comparison,an optimum annealing temperature of 500℃ for improving the properties of In0.14Ga0.86N film was obtained.The multiple scattering mechanisms in the film and their variations after thermal annealing were also analyzed by fitting the experimental data of variable temperature Hall measurements.

  • Investigation of Indium Surface Segregation in InxGa1-xN Films

    Liu Chengxiang, Xie Zili, Han Ping, Liu Bin, Li Liang, Fu Kai, Zhou Jianjun, Ye Jiandong, Wen Bo, Wang Ronghua, Zhang Yu, Chen Dunjun, Jiang Ruolian, Gu Shulin, Shi Yi, Zhang Rong, Zheng Youdou

    Chin. J. Semicond.  2006, 27(S1): 97

    Abstract PDF

    InxGa1-xN alloy film has been epitaxially grown on sapphire (0001) substrate by MOCVD.The measurement results show that the indium content of InxGa1-xN film decreases from 0.72 to 0.27 as the substrate temperature increases from 620℃ to 740℃.This indicates that an increase in the growth temperature results in a lower indium incorporation efficiency in the InxGa1-xN film.According to the results of X-ray diffraction and X-ray photoelectron spectroscopy,the phenomenon of In surface segregation occurs during growing InxGa1-xN film at 620℃ and 690℃.This phenomenon,however,is controlled when the substrate temperature increases to be as high as 740℃.The indium aggregation in the InxGa1-xN film can be avoided since the higher growth temperature results in the increment of the desorption rate for the excess In and the enhancement of the surface mobility for the In atom.As the V/III ratios increasing from 14000 to 38000 at the same temperature of 690℃,the phenomenon of In surface segregation is reduced due to the more activated N supplied by the higher V/III ratio which is prone to forming In-N bonds.

  • Influence of GaN Buffer Layer for InN Growth

    Liu Bin, Zhang Rong, Xie Zili, Xiu Xiangqian, Li Liang, Liu Chengxiang, Han Ping, Zheng Youdou

    Chin. J. Semicond.  2006, 27(S1): 101

    Abstract PDF

    The growth of hexagonal InN film on sapphire (0001) by metal organic chemical vapor deposition was investigated.The high quality InN film was obtained by using LT GaN buffer layer.The photoluminescence (PL) from InN film demonstrated that the optical band gap of InN is 0.7eV.By comparatively studying the influence of different GaN buffer layer:no GaN buffer layer (directly grown),low-temperature (LT) and high-temperature (HT) GaN buffer layers,LT GaN and annealing at high temperatures,the better crystalline quality and the smoother surface of InN film grown by using LT GaN buffer layer were found,which could be explained by the different growth mode of InN.The electrical properties of InN film also characterized by Hall effect measurements.The highest mobility of 567cm2/ (V·s) was obtained.

  • Properties of Zn-Diffused InP Surfaces with Sealed Tube Method

    Lü Yanqiu, Zhuang Chunquan, Huang Yangcheng, Li Ping, Gong Haimei

    Chin. J. Semicond.  2006, 27(S1): 105

    Abstract PDF

    Zn3P2 used as source,(100) oriented and unintended doped InP wafers are diffused with the sealed tube method at different diffusion temperatures and diffusion times.Hole and Zn depth profiles are measured by electrical chemical capacitance-voltage (ECV) and secondary ion mass spectroscopy (SIMS).The results show that the concentrations of hole and Zn in InP layers after diffusion decrease sharply at the diffused/virgin interface.The hole concentration at InP surfaces primary depends on diffusion temperature.The thickness of the diffused layer increases with diffusion time.The Zn concentration is higher one magnitude of order than the hole concentration at InP surfaces.Furthermore,photoluminescence measurement shows that the properties of InP surfaces change little by properly decreasing diffusion temperature and increasing diffusion time if the carrier concentration is enough.

  • Optical Properties of a-GaN Deposited by Sputtering

    Jia Lu, Xie Erqing, Pan Xiaojun, Zhang Zhenxing

    Chin. J. Semicond.  2006, 27(S1): 109

    Abstract PDF

    GaN films are deposited by direct current reactive sputtering.X-ray diffraction (XRD),Fourier infrared absorption spectrum (FTIR),and UV-VIS spectrum are carried out.The XRD patterns indicate that the GaN films deposited at room temperature have amorphous structures.The UV-VIS spectrum indicates that the sample is thicker with increasing substrate temperature,but the optical bandgap is narrower.Ar pressure has a big influence on the bandgap and the roughness of the films.

  • Space-Charge-Limited Current Properties of Amorphous GaN Thin Films

    Zhang Zhenxing, Xie Erqing, Pan Xiaojun, Jia Lu, Han Weihua

    Chin. J. Semicond.  2006, 27(S1): 113

    Abstract PDF

    Amorphous GaN thin films are deposited on silicon substrates by magnetron sputtering.The current-voltage characteristics of the GaN Schottky diodes cannot be understood in terms of thermionic emission simply by including the effects of a series resistance and recombination current,which suggests that other current transport mechanism (space charge limited current,SCLC) is dominant.Analysis of the data indicates an equilibrium electron concentration of 1.1E4cm-3 and a trap located 0.363eV below the conduction band edge.SCLC measurements may be used to probe the properties of deep levels in the wide bandgap amorphous GaN.

  • Optical Properties of Ultralong Hexagonal Polytype Nano-Silicon Carbide Rod

    Zhang Hongtao, Chen Kun, Lemmer U, Bastian G

    Chin. J. Semicond.  2006, 27(S1): 117

    Abstract PDF

    Ultralong nanosilicon carbide rods were prepared by modified PECVD (plasma enhanced chemical vapor deposition) technique,which is four hexagonal multi-type structure.Their diameters range from 18 to 50nm with high resolution TEM,and their lengths range from 0.3μm to 6mm. Raman spectra show that it is 4 hexagonal poly-type nano-silicon carbide rod,and the exciton of ultraviolet emerges strongly in deep region,meanwhile two wide emitting bands emerge at 550~620nm and 700~750nm,respectively.The computing illustrates that the SiC bandwidth is 3.98eV,and this phenomena is not fitted into the computing results according to quantum mechanism.

  • Characteristics of Vanadium Ion-Implanted Layer of 4H-SiC

    Wang Chao, Zhang Yuming, Zhang Yimen

    Chin. J. Semicond.  2006, 27(S1): 120

    Abstract PDF

    Semi-insulating layers could be successfully formed by vanadium ion (V+) implantation in 4H-SiC.The fabrication processes and characteristics of the implanted layer are developed in details.The profile of implantation depth is simulated using the Monte Carlo simulator TRIM.Resistivity measurements are performed for the semi-insulating 4H-SiC samples.The resistivity of V+-implanted layer is strongly dependent on the conduction type of initial 4H-SiC sample.The resistivity at room temperature is about 1.2E9~1.6E10Ω·cm and 2.0E6~7.6E6Ω·cm for p- and n-type samples,respectively.

  • Deposition of SiCN Nano-Films by Sputtering Method on Quartz Substrate

    Lin Hongfeng, Xie Erqing, Zhang Jun, Yan Xiaoqin,

    Chin. J. Semicond.  2006, 27(S1): 124

    Abstract PDF

    Nano-structure silicon carbon nitride (SiCN) films were deposited by radio-frequency (RF) sputtering method.Nano-grains with ~50nm diameter were formed and distributed tightly leading to a compact surface of SiCN films.Conductivity of the nano-SiCN films were in agreement with exponential law of typical semiconductors.Optical band gap (Eopt) of the SiCN films can be adjusted through altering the N2 flux during deposition.The alterable Eopt of the SiCN films would make them to be a potential photoelectric material in the future.

  • Deposition and Ion Implantation of Boron Nitride Film

    Deng Jinxiang, Chen Hao, Liu Junkai, Tian Ling, Zhang Yan, Zhou Tao, He Bin, Chen Guanghua, Wang Bo, Yan Hui

    Chin. J. Semicond.  2006, 27(S1): 127

    Abstract PDF

    The sulfur doping of boron nitride films usually adopts an in-situ doping control technique during their deposition processes.In this paper the sulfur doping of boron nitride films is realized through ion implantation.Experiment results show that the boron nitride films of sulfur ion implantation are n-type.The resistivity of the boron nitride films decrease with increasing sulfur ion implantation dose.Annealing of the implanted boron nitride films results in increasing their doping effect.The resistivity of the film implanted at the dose of 1E16cm-2 and annealed at 600℃ for 60min is 2.20E5Ω·cm,which is 6 orders lower than that of the un-implanted film.

  • Growth of Nickel Silicide Thin Films by Solid Phase Reactionand Ion Beam Synthesis

    Zhang Xingwang

    Chin. J. Semicond.  2006, 27(S1): 131

    Abstract PDF

    Nickel silicide thin films were prepared by solid phase reaction (SPR) and ion beam synthesis (IBS).The samples were characterized by using Rutherford backscattering spectrometry (RBS),X-ray diffraction (XRD),micro-Raman spectroscopy,electrical resistivity and Hall effect measurements.The structures of nickel silicide films prepared by solid phase reaction depended on the post-annealing conditions,and the nickel disilicide (NiSi2) phase was formed after a two-step annealing at 1123K,while the NiSi2 layers were obtained directly by ion beam synthesis at low temperature (523K).The temperature dependence of the sheet resistivity and the Hall mobility from 30 to 400K showed typical metallic behavior for nickel silicides prepared by SPR and peculiar peak and valley features for the NiSi2 layers synthesized by IBS.

  • Rapid Thermal Annealing Characteristics of the Ge/Si(001)Nano-Island Multilayer

    Shi Wenhua, Luo Liping, Zhao Lei, Zuo Yuhua, Wang Qiming

    Chin. J. Semicond.  2006, 27(S1): 136

    Abstract PDF

    The rapid thermal annealing characteristics of the Ge/Si(001) multilayer nano-islands material are investigated by X-ray diffraction and photoluminescence measurements.It is found that the thermal activated Ge/Si atom interdiffusion in nano-island region is much stronger than that in wetting layer.And the interdiffusion becomes stronger;the crystal quality begins deteriorating when the annealing time is larger.If the material is annealed at 800℃ for about 10s,Ge/Si atom interdiffusion is relatively small and the crystal quality keeps good.Meanwhile,it can activate over 50% of the impurities which are implanted by ion beams

  • Thin Highly-Relaxed SiGe Induced by Ion Implantion intothe Epitaxial Substrates

    Xu Xiangdong, Guo Fulong, Zhou Wei, Liu Zhihong, Zhang Zhaojian, Li Xiyou, Zhang Wei, Qian Peixin

    Chin. J. Semicond.  2006, 27(S1): 140

    Abstract PDF

    We propose an approach for preparation of thin highly-relaxed SiGe by combining ion implantation and UHV/CVD techniques.The as-yielded materials are analyzed by micro-Raman spectroscopy and atomic force microscope.The results reveal that large area,thin (100nm) SiGe layer with high relaxation (94%) is thus successfully prepared.Selective chemical etching of SiGe,with the etching rate of 254nm/min,is also performed to study the mechanism.It is found that a strained-Si layer exists at the interface between the epi-SiGe and Si substrate,which is believed to be resulted from both ion implantation and formation of a relaxed-SiGe layer.

  • Effect of Si Intermediate Layer on High Relaxed SiGe Layer Grown Using Low Temperature Si Buffer

    Yang Hongbin, Fan Yongliang

    Chin. J. Semicond.  2006, 27(S1): 144

    Abstract PDF

    High relaxed SiGe layer is grown using low temperature Si buffer technology which combined with a Si intermediate layer,the effect of the Si intermediate layer on relaxed SiGe layer is investigated.This work researches the misfit dislocation etching pattern in different thickness of the SiGe epilayer using the preferential chemical etching and the optical microscopy.Furthermore the influence of intermediate Si layer on dislocation generation,propagation and strain relaxation in epitaxial SiGe layer is investigated.The results show that the intermediate Si layer remarkably changed the dislocation generation and propagation in SiGe layer,consequently the surface morphology also appeared obviously difference

  • Growth and Shape Preservation of Self-Assembled SiGe Quantum Rings

    Li Fanghua, Jiang Zuimin

    Chin. J. Semicond.  2006, 27(S1): 148

    Abstract PDF

    The shape transformation from quantum dots (QDs) to quantum rings (QRs) at Si capping temperature of 640℃ is investigated.A mechanism based on strain energy relief is suggested to explain the QD to QR shape transformation.Successful shape preservation of SiGe QRs is obtained by capping QRs at temperatures below 350℃.A kinetic mechanism is suggested to explain the shape preservation of SiGe QRs at low temperature capping.

  • Chemical Vapor Deposition of Ge Films on Si1-xGex∶C Buffers

    Wang Ronghua, Han Ping, Xia Dongmei, Li Zhibing, Han Tiantian, Liu Chengxiang, Fu Kai, Xie Zili, Xiu Xiangqian, Zhu Shunming, Gu Shulin, Shi Yi, Zhang Rong, Zheng Youdou

    Chin. J. Semicond.  2006, 27(S1): 151

    Abstract PDF

    Ge films have been deposited on Si (100) substrates with Si1-xGex∶C buffers by chemical vapor deposition method.Based on the results of Auger electron spectroscopy,Si1-xGex∶C buffers are thought to be consisted of two layers.One is the Si1-xGex∶C epitaxial layer due to the reaction of GeH4,C2H4 and Si atoms diffusing from the substrate to the surface,and the other is the Si1-xGex layer due to Ge atoms diffusing from the Si1-xGex∶C epitaxial layer to the substrate.Ge films grown on Si1-xGex∶C buffers have a good crystal orientation,with the thickness of the films exceeding the critical thickness of the Ge film deposited on Si directly.The electron mobility of the films equals with bulk Ge materials with the same doping concentration of 1.0E19cm-3.

  • Influence of Deposition Parameters on Electrical Propertiesof Ge2Sb2Te5 Thin Films

    Xia Jilin, Liu Bo, Song Zhitang, Feng Songlin

    Chin. J. Semicond.  2006, 27(S1): 155

    Abstract PDF

    The influence of deposition parameters such as sputtering power and pressure during sputtering on the electrical properties of Ge2Sb2Te5 is investigated.Through measuring the square resistances changing with different annealing temperatures,the deposition mechanism is researched.The results indicate that the sputtering power does not influence the square resistance distinctly,but with the sputtering pressure increasing,the resistance decreases with annealing temperature much more quickly,which means that the crystallization temperature for phase-change from face-centered-cubic to hexagonal structure decreases with the increasing of sputtering pressure.

  • Effect of Si-Implantation on the Structure and Resistance of Ge2Sb2Te5

    Liu Bo, Song Zhitang, Feng Songlin, Chen Bomy

    Chin. J. Semicond.  2006, 27(S1): 158

    Abstract PDF

    Ge2Sb2Te5 films are deposited by RF magnetron sputtering on Si(100)/SiO2 substrates.Si ions are implanted into Ge2Sb2Te5 films.The effect of silicon implantation on the structure and sheet resistance of Ge2Sb2Te5 film is studied in detail using X-ray diffraction and four-point probe methods.It is indicated that the structure of crystalline Ge2Sb2Te5-Si is identified as a multi-phase structure,including of face-centered-cubic low temperature phase,hexagonal high temperature phase and crystalline Sb2Te3 phase with a rhombohedral structure.Silicon implantation has great effect on the resistance-annealing behaviour of Ge2Sb2Te5 film.The sheet resistance of crystalline Ge2Sb2Te5-Si film is higher than that of Ge2Sb2Te5 film when annealing temperature is higher than 400℃,which can reduce the operation current for the phase transition from crystalline to amorphous phase.The improvement of resistance-temperature reliability is beneficial for enlarging the operation current range.

  • CMP and Electrochemical Characterization of Ge2Sb2Te5 Filmin Polishing Slurry

    Liu Qibin, Zhang Kailiang, Wang Liangyong, Song Zhitang, Feng Songlin

    Chin. J. Semicond.  2006, 27(S1): 161

    Abstract PDF

    Electrochemical behavior of Ge2Sb2Te5 films has been investigated in CMP slurry at different pH value and H2O2 concentration.Electrochemical measurements were performed with Solartron SI1287,including open circuit potential(OCP),potentiodynamic polarization sweep.OCP results indicate that Ge2Sb2Te5 alloy films show a passive behavior when pH value is 10,present a passive-active transition when pH value is 11,and present a active behavior when pH value is 12.For potentiodynamic polarization sweep measurements,the shape of the curves changes little with different pH value and H2O2 concentration,suggesting that the reactions at the alloy-slurry interface are the same.CMP of Ge2Sb2Te5 films was investigated using self-made slurry,and polished surface of wafer with GST film is analyzed by SEM and EDS.Results show that the fill structure of GST for phase change memory is formed by CMP process.

  • Effect of Rapid Thermal Process on Oxygen Precipitatesin Heavily As-Doped Wafer

    Sun Shilong, , Liu Caichi, Hao Qiuyan, Teng Xiaoyun, Zhao Liwei, Zhao Yanqiao, Wang Lijian

    Chin. J. Semicond.  2006, 27(S1): 165

    Abstract PDF

    Rapid thermal process (RTP) is performed to heavily-As doped silicon wafer.It is found that the density of oxygen precipitates increases slowly with the increase of the RTP temperature,the cooling rate, and the RTP time.

  • Photoluminescence Characterization of HfON∶Tb Films with Sputtering

    Jiang Ran, Xie Erqing, Jia Changwen, Lin Hongfeng, Pan Xiaojun, Li Hui

    Chin. J. Semicond.  2006, 27(S1): 169

    Abstract PDF

    The HfON∶Tb films are deposited on p-Si by DC sputtering.The samples prepared are annealed at different temperatures.Fluorescence photospectrometer is employed to characterize the photoluminescence.We observe several strong photoluminescence spectra at room temperature in visible region.Different peaks show the different change and there is a slight blue shift with the change of the annealing temperature.The luminescence mechanism of the samples is discussed.We propose an energy transfer mechanism from HfON host to Tb3+ ions.Photoluminescence intensity is found to have well matching relation with the doping concentration of Tb3+ ions and will vanish with the certain concentration of Tb3+ ions.

  • Electrical Properties of HfOxNy Gate Dielectrics

    Jiang Ran, Xie Erqing

    Chin. J. Semicond.  2006, 27(S1): 172

    Abstract PDF

    The electrical properties and the conductive mechanism of HfOxNy gate dielectric films deposited by dc sputtering were studied.The results indicate that higher temperature annealing in nitride ambient is helpful to improve the electrical properties of HfOxNy gate dielectric films.And at the low electric field the I-V characteristics obeys the Ohm’s law,while at the moderate field,the conductive mechanism is according to the space charge limited current(SCLC) theory.The leakage current density is not high that indicate that HfOxNy is a promising material instead of SiO2.

  • High Resolution X-Ray Diffraction and Reciprocal LatticeMapping of Strained-Si/SiGe on SOI

    Ma Tongda, Tu Hailing, Shao Beiling, Liu Ansheng, Hu Guangyong

    Chin. J. Semicond.  2006, 27(S1): 175

    Abstract PDF

    High resolution X-ray double-crystal diffraction (DCD),triple-axis diffraction (TAD),and TAD reciprocal lattice mapping (RLM) are employed to characterize Si/SiGe/Si heterostructures on SOI.The crystallographic misalignment within the layers,and Ge concentration and relaxation percentage of the SiGe layer are measured using TAD combined with DCD (TAD-DCD).TAD RLM can present necessary structural parameters of Si/SiGe/Si heterostructures on SOI.The strain in the thin Si capping layer is determined by high resolution TAD RLM.

  • Fabrication of Strained Silicon Using Reduced Pressure Chemical Vapor Deposition Process

    Wang Jing, Liang Renrong, Xu Yang, Liu Zhihong, Xu Jun, Qian Peixin

    Chin. J. Semicond.  2006, 27(S1): 179

    Abstract PDF

    Strained Si/uniform relaxed Si0.9Ge0.1/graded relaxed SiGe/Si substrate is fabricated using reduced pressure chemical vapor deposition process.The surface roughness and dislocation density are effectively decreased by optimizing the Ge grading rate in the graded SiGe buffer layer and the SiGe epitaxial process.Compared with samples without graded SiGe buffer,the surface roughness (root mean square) of strained Si with the graded SiGe buffer is improved form 3.07 to 0.75nm.The dislocation density is about 5E4cm-2,and the strain in the strained Si cap layer is about 0.45%.

  • High Resistivity and Thick Epitaxial Layer of n-Type on Low Resistivity p-Type Substrates

    Tan Weidong, Tang Youqing, Ma Lixing, Luo Hong, Zhang Wenqing, Gao Tao

    Chin. J. Semicond.  2006, 27(S1): 183

    Abstract PDF

    A epitaxial technique of high resistivity and thick epitaxial layer is presented in this paper.The thick n-type epitaxial films with high resistivity are fabricated by an especial control method on p-type silicon substrates which resistivity is less than 0.02Ω·cm on PE-2061S.The epitaxial resistivity is more than 40Ω·cm and the epitaxial thickness is more than 100μm.It is demonstrated that the epitaxial wafers can meet the requirements for the IGBT applications.

  • Fabrication of Surface Nanostructures Using Scanning Electron Microscope

    Zhu Nianlin, Zhang Jin, Chen Ergang, Bai Han, Zhang Xi, Wang Guangcan, Guo Junmei, Dou Juying

    Chin. J. Semicond.  2006, 27(S1): 186

    Abstract PDF

    We present a new method to fabricate PMMA 1D and 2D periodic nanostructures at the tens-to-hundreds of nanometers scale using the calibrating sign of a digital scanning electron microscope (SEM).In our work,a controllable negative bias voltage generator is cascaded into the cathode self-bias-voltage circuits of SEM,and its internal resistance is far smaller than the self-bias-voltage resistance.The SEM works normally when the generator do not produce negative bias voltage.Once the negative bias voltage is generated,it will restrain electrons emitted from the cathode not passed the grid.The resulting patterning of PMMA-1D and 2D periodic nanostructures are formed by electron beam scanning in the modified SEM.

  • Fabrication of SOI Material Using Low Temperature Bonding Technology

    Zhan Da, Ma Xiaobo, Liu Weili, Song Zhitang, Feng Songlin

    Chin. J. Semicond.  2006, 27(S1): 189

    Abstract PDF

    Nitrogen plasma activation is used before the bonding of the silicon and silicon oxide wafers,and the relationship between the bonding strength and annealing temperature is investigated.The results show that the bonding strength increases dramatically with the increase of annealing temperature when the temperature is below 300℃;above 300℃,the increase tendency becomes unconspicuous.SOI materials are obtained by Smart-Cut technology with nitrogen plasma activation.The characterization results show that the defect density in SOI top layer is low enough after being annealed at 500℃

  • Saturation Behavior of Ultrathin Gate Oxides After Soft Breakdown

    Xu Mingzhen, Tan Changhua, Duan Xiaorong

    Chin. J. Semicond.  2006, 27(S1): 193

    Abstract PDF

    The physical origin of post soft breakdown (SBD) current saturation behavior of ultrathin gate oxides is discussed on the basis of electron velocity saturation concept.The post soft breakdown current-voltage (I-V) characteristic is studied with the proportional difference operator (PDO) method.It is shown that the proportional difference of the soft breakdown I-V curve is a peak function.Its peak position and height are related to the saturation velocity of electron in SBD path and the saturation current density through the SBD path,respectively.In addition a simple and useful method of defining and characterizing the SBD path cross-section in SiO2 based on the defect scattering mechanism is also presented.

  • Ultra-Thin Ru/TaN Bi-Layer as Diffusion Barrier to Seedless Copper Interconnect

    Tan Jingjing, Zhou Mi, Chen Tao, Xie Qi, Ru Guoping, Qu Xinping

    Chin. J. Semicond.  2006, 27(S1): 197

    Abstract PDF

    The property of Ru/TaN bi-layer as diffusion barrier to copper interconnect is investigated.Ru/TaN and Cu/Ru/TaN films are prepared by ion beam sputtering system without breaking the vacuum.Rapid thermal annealing is carried out in high purity N2 atmosphere.Sheet resistance measurement and X-ray diffraction show good thermal stability of the Ru/TaN bi-layer structure.Bias leakage current versus time measurement,which is very sensitive to mobile ions in the oxide,is also used to investigate the copper MOS structure.The direct copper electroplating on the Ru/TaN/Si structure is also carried out.The results show that the Ru/TaN bi-layer with good thermal stability and diffusion barrier property can be widely used in seedless copper interconnects.

  • Field Emission from Rare-Earth Silicides

    Duan Huigao, Xie Erqing, Ye Fan, Wang Xiaoming

    Chin. J. Semicond.  2006, 27(S1): 202

    Abstract PDF

    Several kinds of rare-earth silicides are prepared by implanting rare-earth ions into silicon using a metal vapor vacuum arc (MEVVA) ion source.They show excellent electron field emission characteristics with turn-on fields between 15 and 20V/μm at a current density of 1μA/cm2.After annealed by electron beam,the turn-on field can be lower than 10V/μm and the field emission current density increases as much as an order of magnitude.Their excellent field emission characteristics are attributed to the good thermal stability and the lower work function of the rare-earth silicides.The field emission mechanism is analysed using Fowler-Nordheim theory.Their FN plots can be divided into two segments obviously,and this perhaps is due to the thermal effect in the process of field emission.

  • Development of a Stripe Gate Power MOSFET

    Wang Lixin, Liao Taiyi, Lu Jiang

    Chin. J. Semicond.  2006, 27(S1): 205

    Abstract PDF

    A new planar stripe gate power MOSFET is developed.It has a lower RDS(ON),a higher switch speed and better operation stability compared to traditional cell design.Its manufacture flow is also presented,which is simple and practicable.

  • Field Emission from Hafnium Oxynitride

    Duan Huigao, Xie Erqing, Ye Fan, Jiang Ran, Wang Xiaoming

    Chin. J. Semicond.  2006, 27(S1): 208

    Abstract PDF

    HfOxNy films are prepared by direct current sputtering and subsequently are annealed at high temperature.Their field emission characteristics are investigated.Low turn-on field,high field emission current density,and very good field emission stability are showed.High voltage activation plays a critical role in improving the field emission of HfOxNy,which is thought that the chemical structure and the surface character of the samples are changed at high voltage.The field emission mechanism for HfOxNy is in agreement very well with the classical Fowler-Nordheim tunneling theory.

  • Field Emission from Reaction Sputtering CN Films

    Lin Hongfeng, , Xie Erqing, Zhang Jun, Yan Xiaoqin

    Chin. J. Semicond.  2006, 27(S1): 211

    Abstract PDF

    Carbon nitride (CN) films are deposited with reaction sputtering method.Nano-cone arrays are formed and distributed large areas on the surface of CN films with this method.CN films show excellent field emission behavior with a current density ~10mA/cm2 at 15.5V/μm due to their unique geometrical configurations.The field emission properties of the CN films can also be meliorated through circular survey experiments,which may lead to CN films be a great potential cold cathode materials for future field emission display.

  • Electric Characteristics of Pentacene Field Effect Transistor

    Deng Jinxiang, Chen Guanghua, Beton P H

    Chin. J. Semicond.  2006, 27(S1): 214

    Abstract PDF

    Organic thin film field effect transistor of pentacene is fabricated through evaporating heated pentacene powder in high vacuum.Being a semiconductor layer,pentacene thin film is deposited on p-type silicon (100) that has a silicon dioxide layer.The thickness of pentacene thin film is 70nm.The thickness of Au electrodes including source,drain and gate is 50nm.As an insulating layer,the silicon dioxide is 300nm thick.The channel in the pentacene film field effect transistor is 15μm long,and 190μm wide.AFM is used to characterize the surface morphology of the pentacene thin film.The influence of deposition rate of the pentacene film on the electric characteristics of pentacene field effect transistor is studied.At a deposition rate of 0.24 and 1.36nm/min,the mobility of the field effect transistor is 2.7E-4 and 2.2E-6cm2/(V·s) respectively.

  • Electrical Properties of Wide Bandgap ZnMgO and Fabricationof Transparent Thin Film Transistors

    Wu Huizhen, Liang Jun, Lao Yanfeng, Yu Ping, Xu Tianning, Qiu Dongjiang

    Chin. J. Semicond.  2006, 27(S1): 218

    Abstract PDF

    We propose to use Hexagonal phase Zn1-xMgxO as active channel layer and cubic phase Zn1-xMgxO as gate dielectric of transparent thin film transistors(TFTs).The consistent Zn1-xMgxO thin films are sequentially deposited on ITO substrates and monolithigraph and electrical contact are made.The TFTs have demonstrated an on/off ratio of 1E4 and a channel mobility on the order of 0.6cm2/(V·s).Leakage current is as low as 4.0E-8A at 2.5MV/cm electrical field.

  • High Linearity Float-Zone Silicon Phototransistors with High Sensitivity and Stability

    Han Dejun, Sun Caiming, Sheng Liyan, Zhang Xiurong, Zhang Haijun, Yan Fengzhang, Yang Ru, Zhang Lu, Ning Baojun

    Chin. J. Semicond.  2006, 27(S1): 223

    Abstract PDF

    A float zone silicon phototransistor is fabricated with sensitivity of 38A/W for light of wavelength 0.83μm and optical power of 0.15nW.This demonstrates that the linearity reaches the highest when the base of the phototransistor is completely depleted,and the fitting goodness of output is 0.9954 over a 40dB range from 0.15 to 1500nW.The stability of 1% in the sensitivity for the punch through phototransistor with an internal current conversion gain of 130 can be obtained if the bias voltage and operating temperature can be stable to about 2.5%(1V in 40V) and the temperature to ±2℃.The stability is better than that of reported APD which had a similar gain.

  • A Research on Current Collapse of GaN HEMTs Under DC High Voltage

    Long Fei, Du Jiangfeng, Luo Qian, Zhou Wei, Xia Jianxin, Yang Mohua

    Chin. J. Semicond.  2006, 27(S1): 227

    Abstract PDF

    Based on GaN HEMTs’ device physics and experiment testing results,a new physical model of current collapse is presented.Research results show that under high drain voltage the channel electrons easily eject into GaN buffer layer and are trapped,depleting 2DEG and inducing current collapse.This model describes relationship between current collapse and traps in buffer layer,obtaining product 0.95×θ|VGS| of electron mobility and 2DEG density before and after current collapse.This conclusion can be assisted in AlGaN/GaN HEMT devices’ further theory research and investigation.

  • Temperature Characteristics of Microwave Power SiGe HBTs

    Yang Jingwei, Zhang Wanrong, Jin Dongyue, Qiu Jianjun, Gao Pan

    Chin. J. Semicond.  2006, 27(S1): 231

    Abstract PDF

    Temperature characteristics of SiGe HBT are studied.Experiment data show that the variation of VBE with temperature of SiGe HBT is smaller than that of homo-junction silicon BJT.The needed emitter ballast resistance in SiGe HBT is thus smaller than that in Si BJT when thermal stability of transistors is improved.At the same time,the negative differential resistance characteristics of SiGe HBT is also observed at a high collector-emitter voltage and high current,which can prevent the thermal instability of power transistors effectively,and this is not the case with Si devices.Therefore,SiGe HBT is proved to be more suitable for microwave power devices.

  • A Novel Strained Si Channel Heterojunction pMOSFET

    Zhang Jing, Xu Wanjing, Tan Kaizhou, Li Rongqiang, Li Kaicheng, Liu Daoguang, Liu Luncai

    Chin. J. Semicond.  2006, 27(S1): 235

    Abstract PDF

    A novel MBE-grown method using low-temperature (LT) Si technology is introduced into the fabrication of strained Si channel heterojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and SiGe layer,the strain relaxation degree of the SiGe layer is increased.At the same time,the threading dislocations (TDs) are hold back from propagating to the surface and result a TD density less than 1E6cm-2.The LT-Si technology also reduces thickness of relaxed Si1-xGex epitaxy layer from several μm using UHVCVD to less than 400nm (x=0.2),which will improve the heat dissipation of devices.AFM tests of strained Si surface show RMS is less than 1.02nm.The I-V measurements indicate that hole mobility has an enhancement of 25% compared to similarly processed bulk Si pMOSFET.

  • Microwave Power-Tested Technology of SiC MESFET

    Wang Tongxiang, Pan Hongshu, Li Liang

    Chin. J. Semicond.  2006, 27(S1): 239

    Abstract PDF

    The microwave testing system of SiC MESFET is analyzed.For the device based on the third era semiconductor,the microwave testing system of SiC MESFET is established associating to the testing technology of Si and GaAs MESFET.The test of watt level power output is accomplished under the working frequency of 2GHz.The result is that the power gain is greater than 6dB,the fT is 6.7GHz,and fmax achieves 25GHz.

  • A Carrier-Based Analytic Model for the Undoped Symmetric Double-Gate MOSFETs

    He Jin, Tao Yadong, Bian Wei, Liu Feng, Niu Xudong, Song Yan

    Chin. J. Semicond.  2006, 27(S1): 242

    Abstract PDF

    A carrier-based analytic model for undoped symmetric double-gate MOSFETs is presented.It is based on an exact solution of the Poisson equation coupled to the Pao-Sah current formulation in terms of the carrier concentration.From this model,the different dependences of the surface potential,centric potential,inversion charge and the current on the silicon body thickness and the gate oxide are elucidated analytically,and then the predicted I-V characteristics are compared with the 2D numerical simulations.The analytical results of the model presented show in a good agreement with the 2D simulation,demonstrating the model is valid for all operation regions and traces the transition between them without any auxiliary variable and function.

  • Device Simulation of Nano-Scale MOSFETs Based on Bandstructure Calculation

    Yu Zhiping, Tian Lilin

    Chin. J. Semicond.  2006, 27(S1): 248

    Abstract PDF

    As the device channel length keeps shrunk from several tens nanometers to a few nanometers,it has been commonly agreed upon that the multi-gate structure (including FinFET) is an effective means for improving the device Ion/Ioff ratio.For many years,the effects of quantum mechanics (QM) on the carrier distribution and transport in MOSFETs have been recognized and studied.When the cross-section of a channel is confined to an order of a few nanometers,a more fundamental issue in solid-state physics arises.That is,the dependence of bandstructure or electronic structure on the geometry of the material can no longer be ignored and has non-negligible effects on device characteristics.In this paper,the efficient calculation of bandstructure in the channel region using the first principles is discussed.The electrical characteristics of devices are obtained through the solution of Schrdinger equation with open boundary conditions,based on the carrier transport parameters (such as effective mass and mobility) from bandstructure calculation.The relationship between carrier mobilities and the crystal orientation is also studied,taking into consideration the stress effects on the bandstructure and scattering mechanisms.

  • Mechanism in SiGe-on-Insulator Fabricated by Modified Ge-Condensation Technique

    Zhang Miao, Di Zengfeng, Liu Weili, Luo Suhua, Song Zhitang, Chu Paul K, Lin Chenglu

    Chin. J. Semicond.  2006, 27(S1): 252

    Abstract PDF

    An improved technique is demonstrated to fabricate silicon-germanium on insulator (SGOI) starting with a sandwiched structure of Si/SiGe/Si. After oxidation and successive annealing of the sandwiched structure,a relaxed SGOI structure with 18% Ge fraction is produced.The results indicate that the added Si cap layer is advantageous in suppressing Ge loss at the initial stage of SiGe oxidation and the subsequent annealing process homogenizes the Ge fraction.Raman measurements reveal that the strain in the SiGe layer is fully relaxed at high oxidation temperature (~1150℃) without generating any threading dislocations and crosshatch patterns,which generally exist in the relaxed SiGe layer on bulk Si substrate.

  • Reliability Model of Thin Oxide CMOS

    Liao Jingning, Guo Chunsheng, Liu Pengfei, Wu Yuehua, Li Zhiguo

    Chin. J. Semicond.  2006, 27(S1): 257

    Abstract PDF

    This paper describes two models that are related to the defect of gate oxide and one thermal resistance model of semiconductor devices to evaluate chip life.With CMOS IC technology scaling,the conventional TDDB model cannot provide the necessary accuracy for calculation and prediction.And the reliability of thin gate oxides is also one of the most important problems in CMOS integrated circuits.Thus the development of CMOS TDDB model is very important.

  • Development of High Performance AlGaN/GaN HEMTswith Low Ohmic Contact

    Liu Jian, Li Chenzhan, Wei Ke, He Zhijing, Liu Guoguo, Zheng Yingkui, Liu Xinyu, Wu Dexin

    Chin. J. Semicond.  2006, 27(S1): 262

    Abstract PDF

    The process of Ti/Al/Ti/Au ohmic contact of AlGaN/GaN HEMTs were studied systematically.After the study of annealing process,we got the ohmic contact ratio of 1E-7Ω·cm2.We also analyzed the mechanism of ohmic contact of AlGaN/GaN HEMTs.Based on the optimization of device fabrication,we developed high performance AlGaN/GaN HEMTs.The device with 40μm gate width has reached a maximum extrinsic transconductance of 250mS/mm,and the current density of the device with 0.8mm gate width is 1.07A/mm(Vg=0.5V) at Vds=30V.The output power of 0.8mm gate width device is 32.5dBm(1.6W) at 8GHz,the output power density is 2.14W/mm and power gain 12.7dB.

  • Research of the Critical Parameters of Power RF LDMOS

    Huang Xiaolan, Wu Dexin, Zhang Yaohui, Li Ke, Wang Lixin

    Chin. J. Semicond.  2006, 27(S1): 266

    Abstract PDF

    Breakdown voltage,cutoff frequency fT and Ron are key parameters of power RF LDMOS devices.The measures of enhancing these characteristics are usually conflicting and restricting each other.The relations of these parameters are studied and the optimizing schemes are discussed.The progress and achievement in the field are also presented.

  • Study of High-Speed Digital-to-Analog ConverterBased on BiCMOS Technology

    Liu Daoguang, Li Rongqiang, Shi Jiangang, He Kaiquan, Liu Yukui, Tan Kaizhou, Zhang Jing, Yang Qiudong, Zhong Yi, Shu Man, Xu Wanjing, Xu Shiliu

    Chin. J. Semicond.  2006, 27(S1): 271

    Abstract PDF

    Investigation on high-speed digital-to-analog converter based on BiCMOS technology is described.Through the 16-bit D/A converter with parallel input and current-mode,the circuit design,process and test are carried out.At the operational voltage of ±5.0V,the measured results are as follows:the conversion rate is greater than or equal to 30MSPS,the setup time is 50ns,the gain error is ±8% FSR,the integral nonlinear error is 1/2 LSB,and the power consumption is 500mW.

  • Development of High Voltage pMOS Devices

    Song Limei, Li Hua, Du Huan, Xia Yang, Han Zhengsheng

    Chin. J. Semicond.  2006, 27(S1): 275

    Abstract PDF

    A high voltage pMOSFET (HVpMOS) applied for 100V high voltage integrated circuit is designed and successfully fabricated based on the standard 0.8μm CMOS technology developed by the Institute of Microelectronics,Chinese Academy of Sciences.The breakdown voltage of the HVpMOS is -158V,and the output current reaches about 17mA for the device with W/L=100μm/2μm when gate bias is -100V.Experiment results demonstrate that the HVpMOS devices can work safely at an operation voltage of 100V.

  • Device Structure and Fabricating Method for SOI LIGBT/LDMOSIntegrated with Anti-ESD Diode

    Zhang Haipeng, Wang Qin, Sun Lingling, Gao Mingyu, Li Wenjun, Lü Youhua, Liu Guohua, Wang Jie

    Chin. J. Semicond.  2006, 27(S1): 279

    Abstract PDF

    To explore the way to realize SOI LIGBT/LDMOS devices and PIC with VLSI technology,the structure and fabricating method for the devices integrated with anti-ESD diode are presented,according to which the equivalent circuits at resistive load are given.Then the process flowchart is designed.The main factors which impact the design of parameters related to anti-ESD diode are discussed in details.At last,the requirements for process control are introduced simply.

  • High Performance Gate Length 22nm CMOS Device withStrained Channel and EOT 1.2nm

    Xu Qiuxia, Qian He, Duan Xiaofeng, Liu Haihua, Wang Dahai, Han Zhengsheng, Liu Ming, Chen Baoqin, Li Haiou

    Chin. J. Semicond.  2006, 27(S1): 283

    Abstract PDF

    As scaling CMOS device towards sub-30nm gate length,device physics and semiconductor technology will encounter a series of barriers.This paper deeply investigates sub-30nm CMOS key process technologies,especially offers a new low-cost technique for enhancement of hole mobility using strained channel by Ge pre-amorphization implantation (PAI) for S/D extension to overcome the serious short channel effect (SCE) and to improve drive current/off state leakage ratio,which makes 32% hole effective mobility improvement at 0.6MV/cm vertical field for 90nm gate length pMOS.And the hole mobility enhancement strengthens with the scaling down of feature size of the device.The analysis using zero order Laue Zone diffraction on large angle convergent beam electron diffraction (LACBED) in TEM reveal very large compressive strain of -3.6% (gate length 75nm) in the channel region induced by Ge PAI for S/D extension.Based on the optimum of integration technology,high performance gate length 22nm CMOS devices and gate length 27nm CMOS 32 frequency dividers embedded with 57 stage/201 stage CMOS ring oscillator with strained channel are fabricated successfully with EOT 1.2nm and Ni-SALICIDE.

  • SOI Device Design for SEU Hardening

    He Wei, Zhang Zhengxuan

    Chin. J. Semicond.  2006, 27(S1): 291

    Abstract PDF

    A CMOS device design technique based on SOI process,using actively biased isolated wells for single event upset hardening,has been described.Medici and Hspice simulations were performed to simulate inverter constructed by actively biased isolated wells.This paper also discusses the application of this technique.

  • Failure Analysis of Electronic Devices

    Wang Kaijian, Li Guoliang, Zhang Jun, Wang Jing

    Chin. J. Semicond.  2006, 27(S1): 295

    Abstract PDF

    In order to study the relation of crystal structure of material to performance of device and to improve performance of device,we analyze failure phenomena of the pin of electronic devices with poor weld ability by microscope and electronic probe.

  • Leakage Current Analysis of High Power AlGaInP Lasers

    Xu Yun, Li Yuzhang, Song Guofeng, Gan Qiaoqiang, Yang Guohua, Cao Yulian, Cao Qing, Guo Liang, Chen Lianghui

    Chin. J. Semicond.  2006, 27(S1): 299

    Abstract PDF

    In AlGaInP/GaInP multi-quantum well(MQW) lasers,the injected electrons will surmount the potential barrier between the active layer’s quasi-Fermi level and the conduction band of the p-cladding layer in the high injection or high temperature condition,resulting in the leakage current,which seriously deteriorate the output parameters of laser diodes.In this letter,the effective electron potential was estimated by testing the change of threshold current and differential quantum efficiency with temperature,and was compared with theoretical simulation results.Consequently,the influence of the p-cladding layer’s concentration on the effective potential height was discussed.

  • Optical Properties of Direct Wafer Bonded Micro-Cavity Structures

    Lao Yanfeng, Wu Huizhen, Huang Zhanchao, Liu Cheng, Cao Meng

    Chin. J. Semicond.  2006, 27(S1): 304

    Abstract PDF

    Fabry-Perot micro-cavity resonator structures are directly wafer bonded.Their optical properties of reflectivity are measured using Fourier-transform infrared spectroscopy and simulated theoretically using transfer matrix method.An exponential variation of optical thickness for multi-layers at the both sides of the bonding interface is constructed to analyze the effects of wafer-bonding on the micro-cavity structures.Results show that lower-temperature bonding is advantageous for the fabrication of high-optical quality structures.But a defect-blocking layer should be involved into the wafer-boned structures for the improvement of bonding quality when a higher annealing temperature is used.

  • Application of Buried Tunnel Junction in Long-Wavelength VCSEL Structure

    Liu Cheng, Wu Huizhen, Lao Yanfeng, Huang Zhanchao, Cao Meng

    Chin. J. Semicond.  2006, 27(S1): 309

    Abstract PDF

    δ-doped p+-AlInAs-n+-InP and p+-InP-n+-InP tunnel junction structures are grown by gas-source molecular-beam epitaxy (GSMBE) on InP (100) substrates.Distribution of carriers and electrical properties are characterized by electrochemical C-V method and current-voltage characteristics.It is found that p+-AlInAs-n+-InP tunnel junction is superior to p+-InP-n+-InP tunnel junction.Then 1.3μm vertical-cavity surface-emitting laser (VCSEL) structure which employs p+-AlInAs-n+-InP buried tunnel junction and multiple quantum wells is grown on InP (100) substrates.The VCSEL structure demonstrates low threshold voltage.The gain peak position measured from electro-luminescence is at 1.29μm at room temperature.

  • Electrical Shock Effects on MCT Long-Wavelength PC Detectors

    Liu Dafu, Wu Ligang, Xu Guosen, Zhang Lianmei, Jin Xiufang, Gong Haimei

    Chin. J. Semicond.  2006, 27(S1): 314

    Abstract PDF

    This study is concerned with electrical shock effect on performance of the n-type HgCdTe photoconductive detector with a composition of x≈0.2 in order to improve the reliability under this certain situation.An electrical shock was applied on long wavelength PC MCT detectors.Before and after the shock the resistance,response spectra,blackbody signal and minority carrier lifetime of detectors were measured at normal conditions.Experimental results show that short time shock has no obvious effects on detector performance and the composition have a tendency of decrease.When shock time increase the composition have a tendency of increase,and the detectors performance are decreasing,even wear out.Analysis proves the effect of electrical shock mainly is Joule heat,which is similar to laser irradiation effects

  • An OPAMP with High DC Gain in 0.18μm Digital CMOS

    Wang Han, Ye Qing

    Chin. J. Semicond.  2006, 27(S1): 318

    Abstract PDF

    When scaled down to the ultra deep sub-micron field,the condition that the system-on-a-chip(SOC) needs analog circuits on the chip encounters serious challenges.Based on a SMIC 0.18μm digital process,the operational amplifier is designed with the gain-boosted,also with the bulk regulator.The design widens the input range.Furthermore,the performance limited by pipelined ADC is analyzed in detail.The simulated result shows an open-loop gain of over 100dB,an unit gain bandwidth of 322MHz with a 8.5pF load,and a power consumption of 1.9mW

  • Study of Improved Performance of SOI Devices and Circuits

    Hai Chaohe, Han Zhengsheng, Zhou Xiaoyin, Zhao Lixin, Li Duoli, Bi Jinshun

    Chin. J. Semicond.  2006, 27(S1): 322

    Abstract PDF

    Based on the analysis of floating body effect (FBE),breakdown characteristics,back channel threshold voltage,channel edge leakage,ESD,and radiation hardness characteristics in SOI devices,we propose some methods to improve SOI device and circuit performance as followings:Body contact scheme is the best way to suppress FBE;BF2/B ion implantation into front and back channels can module the threshold voltage of front channel and avoid the turn-on of back channel at the same time;The choice of gate type influences the performance of SOI devices severely;Shallow source region contributes to the reduction of β in parasitic npn bipolar transistor;Self-align-silicidation technology is helpful for the improvement of SOI device characteristics.The total dose of hardened nMOS reaches 1E6rad(Si) in our study.

  • Solar Cells on MCZ(Ge) Silicon Substrates

    Du Yongchao, Xu Shouyan, Liu Feng

    Chin. J. Semicond.  2006, 27(S1): 328

    Abstract PDF

    MCZ(Ge)(magnetically confined Czochralski,germanium doped) silicon wafers have been used in semiconductor industry wider and wider because of its higher mechanical intensity and frequency property.In this paper,the electrical performance of solar cells on MCZ(Ge) silicon substrates is introduced.The best BOL(begin of life) AM0 efficiency of the MCZ(Ge) BSFR solar cells is 15%,and the best BOL AM0 efficiency of MCZ(Ge) BSR solar cells is 12.3%.The 1MeV electron radiation experiment is carried for some MCZ(Ge) solar cells.For comparison,normal CZ BSFR solar cells and BSR solar cells are fabricated and tested.The electrical performance and radiation resistance of MCZ(Ge) solar cells are almost the same as those of normal CZ solar cells.

  • Design of Continuous-Time Filter with Adjustable Bandwidth

    Mo Bangxian, Xiang Bin, Chen Jianghua, Ni Xuewen

    Chin. J. Semicond.  2006, 27(S1): 332

    Abstract PDF

    The circuit configuration and principle of continuous-time low pass filter is discussed.The frequency of continuous-time filter is adjusted by capacitance controlled coding circuit.Its simulation result is well agreed with the theoretical result.The continuous-time filter circuit is fabricated using a 1.2μm double-poly double metal CMOS process,with satisfied results.

  • An Integrated Four Quadrant CMOS Analog Multiplier

    Huo Mingxue, Tan Xiaoyun, Liu Xiaowei, Wang Yonggang, Ren Lianfeng, Qi Xiangkun

    Chin. J. Semicond.  2006, 27(S1): 335

    Abstract PDF

    A four quadrant CMOS analog multiplier is presented.It consists of active attenuator and Gilbert cell.The simulation results based on CSMC 0.6μm n well 2p2m process SPICE BSIM3v3 MOS model (level=49) at 0~5V power supply.The simulation results and layout are given.

  • Application on Sidewall Chrome Attenuated NewStructure Phase Shift Mask

    Xie Changqing, Liu Ming, Chen Baoqin, Ye Tianchun

    Chin. J. Semicond.  2006, 27(S1): 340

    Abstract PDF

    A new type phase shift mask--sidewall chrome attenuated phase shift mask(SCAPSM) is presented.Compared to conventional attenuated phase shift mask,only two process steps are added,but its lithography resolution can be improved greatly.With reference to exposure parameters of ArF scanner TWINSCAN XT:1400E,the SCAPSM exposure process is studied using optical lithography simulation software PROLITH.The resolution of dry 193nm optical lithography can be improved to 50nm when using SCAPSM+OAI.

  • Fabrication of 8×8 MEMS Optical Switch Array

    Jia Cuiping, Dong Wei, Zhou Jingran, Liu Caixia, Zang Huidong, Xuan Wei, Xu Baokun, Chen Weiyou

    Chin. J. Semicond.  2006, 27(S1): 343

    Abstract PDF

    Torsion beam 8×8 optical switch array driven by electrostatic,including upper and under electrodes,was fabricated by MEMES technique.According to crystal characteristics of (110) silicon and anisotropic etching in KOH solution,8×8 micro-mirror array was fabricated.Moreover,the structure of optical switches is rectified by a consideration of undercut when micro-mirrors are etched.The Slant electrode was fabricated in tilting (111) silicon.The whole fabrication technology is characterized by simple technique and low cost.Life time is about 1E7 cycles and tested switch time is less than 10ms.

  • Wet Etching and Releasing of MEMS

    Ou Yi, Shi Shali, Li Chaobo, Jiao Binbin, Chen Dapeng

    Chin. J. Semicond.  2006, 27(S1): 347

    Abstract PDF

    The FP resonant cavity as a microelectromechanical system (MEMS) device based on silicon is introduced.It is fabricated using silicon micro-machined technology.According the specifications of this kind micro-structure,analyzed some questions in the wet etching and releasing.According to the different situation,the design of the device and the technology are improved.And its feasibility is confirmed by the experiment

  • FEA Method in the 3D Thermal Simulation of MCM

    Hu Xiuzhen, Li Zhiguo, Guo Chunsheng, Wu Yuehua, Liao Jingning

    Chin. J. Semicond.  2006, 27(S1): 351

    Abstract PDF

    The reliability of multi-chip module (MCM),especially thermal reliability,has become one of the keys to the reliability research of electronic product.Finite element analysis is an important tool in the thermal analysis of MCM.A three dimensional thermal model of a kind of MCM was built with ANSYS to calculate the temperature distribution.By thermal simulation and thermal analysis,we can raise a project to improve the temperature field

  • Principle,Practice,and Failure Analysis of IC Test Based on ATE

    Pan Shujuan, Zhong Jie

    Chin. J. Semicond.  2006, 27(S1): 354

    Abstract PDF

    This paper introduces the principle and method of IC test,including the electronic and functional characteristics.This paper also introduces the failure analysis based on the ZSX01,which is a typical circuit,referring to scan test.

  • Investigation on Interface Planarization of Driver ICfor Storage Cells of MRAM

    Du Huan, Zhao Yuyin, Han Zhengsheng, Xia Yang, Zhang Zhichun

    Chin. J. Semicond.  2006, 27(S1): 358

    Abstract PDF

    Surface planarization for storage cells of magnetic random access memory (MRAM) is investigated by atomic force microscope (AFM) and scan electron microscope (SEM).AFM images indicate that the surface of Al films deposited by magnetron consists of many particles with size of tens of nanometers.The roughness of surface depicted with root mean square (RMS) is more than 10nm.The roughness of surface is improved after the film of refractory metal Ti or Ta deposited on Al film.Under the conditions of small pressure and low rotate speed,the roughness of surface (the value of RMS) reaches less than 1nm by applying chemical mechanical planarization (CMP).SEM images show that the surface of the whole chip can be planarized greatly by coating photoresist on surface.The photoresist is removed by reactive ion etch under the same etch rate to photoresist and oxide.

  • Small Size,Low Power RFID RF Front End Circuit Design

    Zhou Shenghua, Yang Zhichao, Wu Nanjian, Li Meiyun

    Chin. J. Semicond.  2006, 27(S1): 361

    Abstract PDF

    This paper presents an RFID RF front end circuit,which is compatible with EPC Gen2 protocol.The front end circuit includes rectifier,ASK demodulator,ASK and BPSK modulator.The working frequency is 860~960MHz.The front end circuit is based on NVM and Schottky diode 0.35μm CMOS process.It is found that switched capacitor circuit can reduce power consumption and die area.

  • Study on High-Speed Digital-to-Analog Converter Basedon BiCMOS Technology

    Li Rongqiang, Liu Daoguang, Yan Gang, He Kaiquan, Liu Yukui, Tan Kaizhou, Zhang Jing, Yang Qiudong, Zhong Yi, Shu Man, Xu Wanjing, Xu Shiliu

    Chin. J. Semicond.  2006, 27(S1): 365

    Abstract PDF

    The design of 12bit high-speed D/A converter was described in this study.By using 2μm isoplanar,high-speed bipolar process technology,the 12bit D/A converter circuit has been developed.The performance of the converter is as follows:the refresh rate ≥80MHz,linear error ≤3LSB,differential nonlinearity ≤3LSB.

  • Design and Optimization of Low-Power Processor for Wireless Sensor Network

    Zhao Gang, Hou Ligang, Luo Rengui, Liu Yuan, Wu Wuchen

    Chin. J. Semicond.  2006, 27(S1): 370

    Abstract PDF

    A low power processor (LPP) for wireless sensor network (WSN) is implemented,based on 90nm technology.In order to reduce power consumption,two methods are selected in the design.Clock gating technique is used to reduce the dynamic power dissipations,and multiple threshold voltage library is adopted to depress leakage power consumption.This paper reports the design results with a brief discussion.

  • A Speech Feature Extraction Circuit Suitable for Chip Technology

    Wang Yang

    Chin. J. Semicond.  2006, 27(S1): 374

    Abstract PDF

    A speech feature extraction circuit that is simple and suitable for chip technology is designed.It consists of a filter bank,rectifying circuit, and low pass filters.Meanwhile,an idea of the device characteristics efficient for designing circuits is illustrated with this circuit.The idea takes implementation of the functions rather than the algorithms as the purpose.Although the mathematical models are complicated,the circuits designed according to this idea are simple,suitable for chip implementation, and more efficient for the limited resources on chip.The results show that the circuit can obtain the features similar to the linear system through the SPICE simulation for practical speech signals.

  • Ohmic Contact on SiC Using n+ Polysilicon/n+ SiC Heterojunction

    Zhang Lin, Zhang Yimen, Zhang Yuming, Tang Xiaoyan

    Chin. J. Semicond.  2006, 27(S1): 378

    Abstract PDF

    A novel SiC ohmic contact of n+ polysilicon/n+ SiC heterojunction is simulated with the numerical simulator ISE TCAD.The simulated results show that the n+ polysilicon/n+ SiC heterojunction can form excellent ohmic contact and has the advantages of simple process and excellent performance.

  • Etching Characteristics of PECVD SiC

    Chen Sheng, , Li Zhihong, Zhang Guobing, Guo Hui, Wang Yu

    Chin. J. Semicond.  2006, 27(S1): 381

    Abstract PDF

    In this paper,we use reactive ion etching (RIE) and inductive coupled plasma reactive ion etching (ICP) method to test the etching characteristics in PECVD SiC under different pressures and powers.We prove the feasibility of using SF6 and He to etch PECVD SiC,discuss the relationship between pressure/power and etch rate in RIE,investigate the influence of hydrogen content in PECVD SiC etch rate under certain parameters,testify the existence of load efficiency in ICP.

  • Amorphization Implant Technology in NiSi SALICIDE Process

    Jiang Yulong, Ru Guoping, Qu Xinping, Li Bingzong

    Chin. J. Semicond.  2006, 27(S1): 385

    Abstract PDF

    After the formation of pn junction,the surface layer of crystalline Si substrate can be amorphized by Si ion implant.The influence of the amorphization implant on nickel silicidation is studied in this paper.The experimental results show that the amorphization implant can enhance the Ni/Si reaction at low temperatures and NiSi can even directly form after low temperature annealing.It is also revealed that the amorphization implant will not induce extra dopant redistribution.However,the transmission electron microscopy demonstrates that the amorphization implant energy should be optimized.

  • Two Kinds of Patterned SiGe Epitaxial Growth Technologies

    Xu Yang, Wang Fei, Xu Jun, Liu Zhihong, Qian Peixin

    Chin. J. Semicond.  2006, 27(S1): 389

    Abstract PDF

    We lucubrate on the patterned SiGe epitaxial growth technology based on Tsinghua’s UHV/CVD system.We develop different applied technologies of the patterned SiGe epitaxial growth by using the SiO2 single-film or SiO2/Poly-Si double-film as the patterned-window isolated layer.

  • Direct Bonded SOI Wafers Technology

    Huang Chenhung, Chiou Herngde

    Chin. J. Semicond.  2006, 27(S1): 392

    Abstract PDF

    This paper reports the direct bonded SOI wafers technology.It discusses how the wafer cleanliness and surface flatness result in the voids of bonded SOI wafers.By growing oxide on different layer of bonded wafers,we demonstrate the warpage variation.Dimples on wafers results in the bonding voids,which can be inspected by infrared light.

  • Double Side Fine CMP of Silicon Wafer

    Zhang Kailiang, Song Zhitang, Zhong Min, Zheng Mingjie, Feng Songlin

    Chin. J. Semicond.  2006, 27(S1): 396

    Abstract PDF

    Based on the analysis of double side fine CMP process,new type of polishing slurry named SIMIT8030-I was first prepared in order to improve the polishing rate for double side fine CMP, which contained colloidal silica nano-abrasives with large particle.Polishing tests were performed with the double side polisher,and the properties including the size of abrasives,thickness,planarization (TTV and TIR) and roughness were characterized by SEM,wafer thickness measurements ADE-9520,AFM and so on.Results show that comparing with Nalco2350 slurry,polishing rate was increased 40%(14μm/h vs 10μm/h);TTV and TIR were also less than those of Nalco2350 slurry;the RMS of roughness was reduced from 0.4728nm to 0.2874nm.In all,new type of slurry not only increased the removal rate,but also improved the surface planarization and roughness simultaneously.

  • Research on CMP Slurry for Fine Polishing of Si Substrate

    Zhong Min, Zhang Kailiang, Song Zhitang, Feng Songlin

    Chin. J. Semicond.  2006, 27(S1): 400

    Abstract PDF

    Chemical mechanical polishing is one of the most important processes in IC fabrication.In order to increase the polishing rate and get smooth surface, a series of polishing experiments about the effect of slurry components were done by using self-made colloidal silica nanometer slurry with large particle abrasives,and its thickness and surface were characterized by atomic profiler、AFM and thickness tester.Results show that after the recipes of slurry including the pH value,the concentration of abrasive and other additives were optimized,higher removal rate and smoother surface were achieved.The removal rate was 697nm/min,and the RMS of surface roughness was 0.4516nm.In sum,higher removal rate and ultra-fine surface were achieved simultaneously.

  • Relationship Between Annealing Temperature and Thermal Stress

    Wu Yuehua, Li Zhiguo, Liu Zhimin, Ji Yuan, Hu Xiuzhen, Liao Jingning

    Chin. J. Semicond.  2006, 27(S1): 403

    Abstract PDF

    The residual strains and stresses of 1μm/0.5μm aluminum interconnects are observed by using two dimension XRD.The tensile stress of the deposited interconnects decreases with increasing interconnect width.The longitudinal stress is obvious lager than transverse stress.Stresses in every directions decrease after 2.5h annealing.The decreasing amplitude of 1μm-aluminum is much lager than that of 0.5μm.The image quality (IQ) of Kikuch is carried out by using EBSD fore-and-aft annealing.The result reveals that lattice distortion decreases by annealing,and the stress is released.

  • Si-Glass Hermetic Package with the Benzo-Cyclo-Butene Material

    Liu Yufei, Liu Wenping, Li Sihua, Wu Yaming, Luo Le

    Chin. J. Semicond.  2006, 27(S1): 407

    Abstract PDF

    The characteristics of the wafer level low-temperature bonding with the benzo-cyclo-butene(BCB) material are studied experimentally and compared with the 300℃ anodic bonding.The results show that the bonding temperature with BCB is below 250℃,the hermeticity is (5.5±0.5)E-4Pa cc/s He,the shear strength is from 9.0 to 13.4MPa,and the yield is 100%.It shows that using the BCB material is an effective way for wafer level low-temperature hermetic package.According to the simplified seepage model,the relationship between the leakage rate and the distance from the hole to the device border is also studied.

  • Epitaxial Growth of Er2O3 Films and Its Band Offsets on Si

    Zhu Yanyan, Xu Run, Chen Sheng, Fang Zebo, Xue Fei, Fan Yongliang, Jiang Zuimin

    Chin. J. Semicond.  2006, 27(S1): 411

    Abstract PDF

    The epitaxial growth of Er2O3 films is achieved on Si(001) and Si (111) substrates by MBE at the growth temperature of 700℃ in an oxygen pressure of 0.93mPa.The crystalline structure and orientation of the as-deposited films are strongly dependent on the growth temperature and oxygen pressure.Silicide is formed in the films grown at the lower temperature and lower oxygen pressure.In addition,the oxide phase in the films grown at the lower temperature is polycrystalline.The valence band offset and the conduction band offset between the epitaxial Er2O3 film and the Si substrate are also obtained based on X-ray photoelectron spectroscopy measurements.

  • Characteristics of Nanometer MOSFETs with Mechanical Strain in the Channel

    Wu Tao, Du Gang, Liu Xiaoyan, Kang Jinfeng, Han Ruqi

    Chin. J. Semicond.  2006, 27(S1): 415

    Abstract PDF

    The characteristics of typical nanometer p- and n-channel strained Si MOSFETs with mechanical stress applied in the channel are simulated by a commercial device simulator ISE. The impacts of the direction and magnitude of the stress on the device performances such as threshold voltage and sub-threshold characteristics are investigated.

  • 1mm SiC Multi-Finger Gate Microwave Power Device

    Chen Gang, Qian Wei, Chen Bin, Bai Song

    Chin. J. Semicond.  2006, 27(S1): 419

    Abstract PDF

    We report our research on 1mm multi-finger gate 4H-SiC metal-semiconductor field-effect transistors (MESFETs). We design our own device process to fabricate n-channel 4H-SiC MESFETs with 100μm single gate,1mm total gate periphery,0.8μm gate length. The RF characteristics are studied. At fo=2GHz,Vds=30V,the maximum output power is measured to be 1.14W,with a gain of 4.58dB,power added efficiency 19%, and drain efficiency 28.7%.

  • Magnetic Field Optimization of a Reactive Ion Etching Device with Magnetic Containment

    Jing Xiaocheng, Yao Ruohe, Lin Yushu

    Chin. J. Semicond.  2006, 27(S1): 422

    Abstract PDF

    The FEM (finite element mothod) is used for building the magnetic field model in the MERIE (magnetically enhanced reactive ion etcher) apparatus. Investigation reveals that the value and distribution of the magnetic field can be optimized using proper configuration of the magnetic poles and adjust of the magnetization direction,then the best process can be achieved by improving dry etching uniformity as well as the etching rate.


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