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Volume 28, Issue 9, Sep 2007


  • Ti/4H-SiC Schottky Barrier Diodes with Field Plate and B+ Implantation Edge Termination Technology

    Chen Gang, Li Zheyang, Bai Song, Ren Chunjiang

    Chin. J. Semicond.  2007, 28(9): 1333

    Abstract PDF

    This paper describes the fabrication and electrical characteristics of Ti/4H-SiC Schottky barrier diodes (SBDs).The ideality factor n=1.08 and effective Schottky barrier height φ=1.05eV of the SBDs were measured with the method of forward current density-voltage (J-V).A low reverse leakage current below 5.96e-3A/cm2 at a bias voltage of -1.1kV was obtained.By using B+ implantation,an amorphous layer as the edge termination was formed.We used the PECVD SiO2 as the field plate dielectric.The SBDs have an on-state current density of 430A/cm2 at a forward voltage drop of about 4V.The specific on-resistance Ron was found to be 6.77mΩ·cm2.

  • Driving Circuit for AMOLED with Fault Tolerance

    Li Dayong, Liu Ming, Wei Wang

    Chin. J. Semicond.  2007, 28(9): 1337

    Abstract PDF

    The defects of an OLED-based display,mainly electrical shorts,cause pixels to stay dark,decrease the brightness of a panel,severely influence the display uniformity,and also consume a considerable amount of power.In this paper,for AM-OLEDs,a novel circuit employing p-type low-temperature poly-Si thin-film transistors is introduced to offer fault-tolerant capabilities for such defects.The results show that this circuit can save significant power and maintain the luminance of the pixel without changing the driving current.

  • A High Speed,12-Channel Parallel,Monolithic IntegratedCMOS OEIC Receiver

    Zhu Haobo, Mao Luhong, Yu Changliang, Chen Hongda, Tang Jun

    Chin. J. Semicond.  2007, 28(9): 1341

    Abstract PDF

    The design and fabrication of a high speed,12-channel monolithic integrated CMOS optoelectronic integrated circuit (OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the -3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8~1.4Gb/s.Altogether,the 12-channel OEIC receiver chip can be operated at 15Gb/s.

  • A Novel Power Supply Solution of a Passive RFID Transponder

    Jia Hailong, Ni Weining, Shi Yin, Dai F F

    Chin. J. Semicond.  2007, 28(9): 1346

    Abstract PDF

    This paper presents a power supply solution for fully integrated passive radio-frequency identification (RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.


  • Subsurface Damage in the Monocrystal Silicon Grinding on Atomic Scale

    Guo Xiaoguang, Guo Dongming, Kang Renke, Jin Zhuji

    Chin. J. Semicond.  2007, 28(9): 1353

    Abstract PDF

    A molecular dynamics (MD) simulation is carried out to analyze the effect of cutting edge radius,cut-depth,and grinding speed on the depth of subsurface damage layers in monocrystal silicon grinding processes on an atomic scale.The results show that when the cutting edge radius decreases in the nanometric grinding process with the same cut-depth and grinding speed,the depth of the damage layers and the potential energy between the silicon atoms decrease too.Also,when the cut depth increases,both the depth of the damage layers and the potential energy between silicon atoms increase.When the grinding speed is between 20 and 200m/s,the depth of the damage layers does not change much with the increase of the grinding speed under the same cutting edge radius and cut depth conditions.This means that the MD simulation is not sensitive to changes in the grinding speed,and thus increasing the grinding speed properly can shorten the simulation time and enlarge the simulation scale.In conclusion,the subsurface damage of monocrystal silicon is mainly based on the change of the potential energy between silicon atoms,which is verified by the ultra-precision grinding and CMP experiments.

  • A Novel Fully-Depleted Dual-Gate MOSFET

    Zhang Guohe, Shao Zhibiao, Han Bin, Liu Derui

    Chin. J. Semicond.  2007, 28(9): 1359

    Abstract PDF

    A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed.The hetero-material gate,which consists of a main gate and two side-gates,is used to control the surface potential distribution.The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately.Compared to a common DG fully depleted SOI MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope.The on/off current ratio is about 1e10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.

  • CMOS Quadrature Modulator and Up-Conversion Mixer for802.11a Wireless LAN Systems

    Li Wenyuan, Wang Zhigong, Mao Yinwei

    Chin. J. Semicond.  2007, 28(9): 1364

    Abstract PDF

    A quadrature modulator and an up-conversion mixer for an 802.11a wireless LAN system are designed and fabricated in 0.18μm gate length standard CMOS technology.A current feedback loop with a transconductor is used to improve the linearity of the quadrature modulator;An LC resonant tank is used as the load of the up-conversion mixer to improve its gain and increase the voltage swing.The measurement results show that the input P1dB achieves -3.6dBm,the transducer power gain of the circuit is -3.6dB,and the current consumes about 45.8mA with a 1.8V power supply.

  • Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

    Wang Pei, Long Shanli, Wu Jianhui

    Chin. J. Semicond.  2007, 28(9): 1369

    Abstract PDF

    Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described.The calibration circuit works in parallel with the SA-ADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption,and the calibrated resolution can be up to 14bit.This circuit is used in a 10bit 3Msps successive approximation ADC.This chip is realized with an SMIC 0.18μm 1.8V process and occupies 0.25mm2.It consumes 3.1mW when operating at 1.8MHz.The measured SINAD is 55.9068dB,SFDR is 64.5767dB,and THD is -74.8889dB when sampling a 320kHz sine wave.

  • Combined Novel Gate Level Model and Critical Primary Input Sharing for Genetic Algorithm Based Maximum Power Supply Noise Estimation

    Tian Zhixin, Liu Yongpan, Yang Huazhong

    Chin. J. Semicond.  2007, 28(9): 1375

    Abstract PDF

    A gate level maximum power supply noise (PSN) model is defined that captures both IR drop and di/dt noise effects.Experimental results show that this model improves PSN estimation by 5.3% on average and reduces computation time by 10.7% compared with previous methods.Furthermore,a primary input critical factor model that captures the extent of primary inputs’ PSN contribution is formulated.Based on these models,a novel niche genetic algorithm is proposed to estimate PSN more effectively.Compared with general genetic algorithms,this novel method can achieve up to 19.0% improvement on PSN estimation with a much higher convergence speed.

  • Interband Optical Transitions in Semiconducting Iron Disilicide β-FeSi2

    Yan Wanjun, Xie Quan, Zhang Jinmin, Xiao Qingquan, Liang Yan, Zeng Wuxian

    Chin. J. Semicond.  2007, 28(9): 1381

    Abstract PDF

    The geometric parameters and the electric and optical properties of β-FeSi2 are calculated using first principle methods based on plane-wave pseudo-potential theory in detail. The results indicate that:(1) β-FeSi2 is a quasi-direct semiconductor and the band gap is 0.74eV.The density of states is mainly composed of Fe 3d and Si3p.(2) The valences electronic state of β-FeSi2 is asymmetric and has a strong local area characteristic.These have an important influence on the electronic structure and the bonding characteristics of β-FeSi2.(3) The calculation of the dielectric function reveals that β-FeSi2 is anisotropic,the biggest peak of absorption is 2.67e5cm-1,the extinction coefficient shows strong absorption characteristic near the band edge,and the mechanism of the electric and optical properties of β-FeSi2 dominated by electron inter-band transitions are analyzed in terms of calculated band structure and density of states.

  • Photoluminescence Properties of Er-Doped HfO2 Films

    Xia Yan, Wang Junzhuan, Shi Zhuoqiong, Shi Yi, Pu Lin, Zhang Rong, Zheng Youdou, Tao Zhensheng, Lu Fang

    Chin. J. Semicond.  2007, 28(9): 1388

    Abstract PDF

    Er-doped HfO2 films were grown by pulsed laser deposition (PLD) and ion implantation.The room-temperature and varied-temperature PL spectra were observed.By analyzing the PL peak intensity of Er3+ at 1535nm as a function of annealing temperature,we found that annealing at 800℃ can reduce the nonradiative decay channels in HfO2 films such as implantation-induced defects and optically activate Er ions at best,causing the strongest photoluminescence.The PL excitation spectrum of Er3+ in HfO2 film at room temperature shows that there is also indirect excitation besides the direct excitation during the light-emitting process of Er3+.HfO2 films will be a good host material for Er implantation.

  • Theoretical Calculation of Conversion Efficiency of InGaN Solar Cells

    Wen Bo, Zhou Jianjun, Jiang Ruolian, Xie Zili, Chen Dunjun, Ji Xiaoli, Han Ping, Zhang Rong, Zheng Youdou

    Chin. J. Semicond.  2007, 28(9): 1392

    Abstract PDF

    Based on the current-voltage equation for pn junction solar cells,the conversion efficiency under ideal conditions for an InGaN solar cell was calculated.The conversion efficiencies of one-junction,two-junction,and three-junction InxGa1-xN solar cells were calculated to 27.3%,36.6%,and 41.3%,respectively,all of which are higher than those of common materials.The optimal band gaps and the indium contents of these InxGa1-xN solar cells were also obtained,giving a theoretical basis for the design of InxGa1-xN solar cells.

  • Conductivity and Conducting Mechanism of Polypyrrole via Chemical Oxidative Polymerization

    Ren Li, Zhang Xuefeng, Wang Lixin, Zhang Fuqiang

    Chin. J. Semicond.  2007, 28(9): 1396

    Abstract PDF

    Polypyrrole was synthesized by chemical oxidative polymerization.Its morphology was characterized by SEM and TEM,and its conductivity was measured by a four-probe instrument.Influences on its conductivity and conducting mechanism were studied.It was found that the conductivity and morphology are greatly influenced by the amount of oxidant,reaction temperature and time,and the kind of dopants.The conductivity of polypyrrole doped with BSNa was the highest under the condition of molar tation of FeCl3/Py 1.0,for a reaction time of 0.5h in an ice-bath.It was shown that the polymer chain of the fiber PPy-NSA was identical to that of PPy doped with other sulfonic dopants.The higher conductivity of polypyrrole was due to its doping condition,the narrow gap between the conduction band and valence band,the freer movement of current carriers,and the doping-undoping of anions.

  • Influence of Ag Layer Thickness on the Properties of ZnO/Ag/ZnO Films

    Li Jun, Yan Jinliang, Sun Xueqing, Li Kewei, Yang Chunxiu

    Chin. J. Semicond.  2007, 28(9): 1402

    Abstract PDF

    ZnO(60nm)/Ag/ZnO(60nm) multilayer films with different Ag thicknesses were prepared by alternate RF magnetron sputtering of ZnO and DC magnetron sputtering of Ag.The structural,optical,and electrical properties of samples were studied with an X-ray diffractometer,a UV-vis spectrophotometer,and a four-point probe,respectively.The results indicate that increasing the thickness of the Ag layer enhances the polycrystalline structure of the ZnO(60nm)/Ag/ZnO(60nm) and the intensity of the Ag (111) peak.When the thickness of the Ag film is 11nm,the ZnO(60nm)/Ag/ZnO(60nm) film has a high optical transmittance of 92.3% at 554nm.As the thickness of the Ag film increases,red shift and broadening effects of the characteristic absorption peak of Ag occur,and the sheet resistance of the multilayer film decreases and then levels off to a steady value.

  • Bi2O3-ZnO-Nb2O5 Film Fabricated by Sol-Gel Technique and C-V Characteristic of GaN MIS Structure

    Shu Bin, Zhang Heming, Wang Qing, Huang Dapeng, Xuan Rongxi

    Chin. J. Semicond.  2007, 28(9): 1406

    Abstract PDF

    Bi2O3-ZnO-Nb2O5 (BZN) film with a high dielectric constant,which can be used as a gate medium in GaN metal-insulator-semiconductor field effect transistors (MISFETs),was fabricated by the sol-gel technique.Process parameters such as raw material proportioning,sinter temperature,and heat preservation time were obtained.The problems of the dissolvability,viscosity,and soakage of the raw material were also solved.A GaN MIS structure with the BZN film was also fabricated;and from the measured C-Vcurve,εr of the BZN film was 91,and the reverse voltage and CFB of this MIS structure were -3.4 and -1.9V,respectively.

  • Growth of AlGaAs on GaAs (110) Surface by Molecular Beam Epitaxy

    Liu Linsheng, Wang Wenxin, Liu Su, Zhao Hongming, Liu Baoli, Jiang Zhongwei, Gao Hanchao, Wang Jia, Huang Qing’an, Chen Hong, Zhou Junming

    Chin. J. Semicond.  2007, 28(9): 1411

    Abstract PDF

    A series of samples with different growth temperatures and different BEP ratios were grown on GaAs (110) substrates by molecular beam epitaxy.The samples were investigated via room temperature and low temperature photoluminescence spectra and high resolution X-ray diffraction.Then the optimized growth conditions of Al0.4Ga0.6As films on GaAs (110) substrates were found.

  • Fabrication of a Novel SOI Material with Non-Planar Buried Oxide Layer

    Guo Yufeng, Li Zhaoji, Zhang Bo, Liu Yong

    Chin. J. Semicond.  2007, 28(9): 1415

    Abstract PDF

    A fabrication process of a novel SOI material with a non-planar buried oxide layer was developed using a series of key processes.A high quality non-planar buried oxide film was made by dry etching,thermal growth,and chemical-vapor deposition.A poly-silicon buffer layer for bonding was deposited by CVD and was planarized by photoresist block masking and chemical mechanical polishing.The active and substrate wafers were bonded by vacuum contacting at room temperature,with pre-bonding at a moderate temperature and final firming bonding at a high temperature.Based on these key processes,a novel SOI material with a non-planar buried oxide layer was fabricated.The structure includes an active layer with a thickness of 21μm,a buried oxide with a thickness of 0.943μm,and self-aligned top and bottom trenches with thicknesses of about 0.9μm.The measurements indicate a high quality bonded interface with a large combining intensity and excellent electrical performance with a high breakdown electric field.

  • Recess-Gate AlGaN/GaN HFET

    Zhang Zhiguo, Feng Zhen, Yang Mengli, Feng Zhihong, Mo Jianghui, Cai Shujun, Yang Kewu

    Chin. J. Semicond.  2007, 28(9): 1420

    Abstract PDF

    A recessed gate AlGaN/GaN HFET with a total gate length of 100μm is studied.The device demonstrates an increase in transconductance from 260.3 to 314.8mS/mm compared to the unrecessed device,while the saturation current changes slightly.Moreover,the ideality is improved from 2.3 to 1.7.An output power density of 11.74W/mm is achieved at 8GHz and 40V using a load pull system.

  • Monolithic Integration of 0.8μm Gate-Length GaAs-Based InGaP/AlGaAs/InGaAs Enhancement- and Depletion-Mode PHEMTs

    Xu Jingbo, Zhang Haiying, Yin Junjian, Liu Liang, Li Xiao, Ye Tianchun, Li Ming

    Chin. J. Semicond.  2007, 28(9): 1424

    Abstract PDF

    The material structure of GaAs-based InGaP/AlGaAs/InGaAs PHEMTs was optimized to obtain the positive threshold voltage of an enhancement-mode PHEMT.Contact-mode photolithography was used for realizing the monolithic integration of 0.8μm gate length GaAs-based InGaP/AlGaAs/InGaAs enhancement- and depletion-mode PHEMTs.Excellent DC and high frequency performance are achieved.VT,gm,JDSS,fT,and fmax are 0.1V,330mS/mm,245mA/mm,14.9GHz,and 18GHz for E-mode PHEMTs,and -0.5V,260mS/mm,255mA/mm,14.5GHz,and 20GHz for D-mode PHEMTs,respectively.DCFL inverters based on monolithic integration of GaAs-based InGaP/AlGaAs/InGaAs enhancement- and depletion-mode PHEMTs are fabricated.The supply voltage is 1V.When the input voltages are 0.15 and 0.3V,the output voltages are 0.98 and 0.18V, respectively.

  • Breakdown Characteristic of Multiregion Double RESURF LDMOS with High Voltage Interconnection

    Qiao Ming, Zhou Xianda, Duan Mingwei, Fang Jian, Zhang Bo, Li Zhaoji

    Chin. J. Semicond.  2007, 28(9): 1428

    Abstract PDF

    A multiregion double RESURF LDMOS with a high voltage interconnection of over 600V is experimentally realized.Using the effects of a junction termination extension of the P-top layer and the curvature of a circular structure,the breakdown voltage of the lateral high voltage device is improved by spreading the depletion region.Two- and three-dimensional simulation results are presented.The breakdown voltage of the LDMOS with high voltage interconnection is not exact in the two-dimensional simulation.In agreement with the 3D simulation,the experimental results show that the breakdown voltage of the LDMOS,which depends strongly on the concentration of the P-top layer,will increase with the reduction of the width of the high voltage interconnection.When the width is 30μm,the breakdown voltage is 640V without adding additional masks or process steps.As a result,the structure can be used in conventional level shifting and high voltage junction isolation termination for high voltage applications.

  • Analysis of Early Voltage in 4H-SiC BJTs

    Han Ru, Li Cong, Yang Yintang, Jia Hujun

    Chin. J. Semicond.  2007, 28(9): 1433

    Abstract PDF

    The Early voltage of 4H-SiC BJT,which has an exponential impurity profile in the base,is calculated,taking into account the current gain of the device and four recombination processes in the device.The effects of temperature on the Early voltage and the current gain of the 4H-SiC BJT are investigated.Simulation results show that,keeping the other parameters unchanged,the Early voltage increases with NE (emitter doping density),and decreases when NC (collector doping density) increases and W(base width) decreases.The incomplete ionization of the impurities in 4H-SiC can affect the temperature dependences of the Early voltage and current gain.

  • A 22-Element Small-Signal Model of GaN HEMT Devices

    Liu Dan, Chen Xiaojuan, Liu Xinyu, Wu Dexin

    Chin. J. Semicond.  2007, 28(9): 1438

    Abstract PDF

    This paper uses a new GaN HEMT small signal model that includes 22 elements and increases the conductance of Ggsf and Ggdf and has parallel gate-source capacitance Cgs and gate-drain capacitance Cgd,which can reflect the gate’s leakage current.The results show that this model can improve the fitting precision and makes more sense in the physical domain.This paper improves the extraction method for extrinsic capacitance parameters,which can extract the new gate-field plate and source-field plate devices’ small-signal parameters effectively.It can reflect the physical characteristics of GaN devices accurately from the extracted parameters.

  • RTS Amplitude of 90nm MOS Devices in Sub-Threshold Region

    Bao Li, Zhuang Yiqi, Ma Xiaohua, Bao Junlin

    Chin. J. Semicond.  2007, 28(9): 1443

    Abstract PDF

    Based on research on the amplitude of RTS in SMIC 90nm CMOS nMOS 0.18μm×0.15μm devices with a 1.4nm gate oxide,an approach to diffusion that fits MOS operation principles better is proposed.Furthermore,a new mechanism in which a border trap changes the charge distribution of the gate and thus influences the channel current is also involved.Research shows that this method not only explains the experiment results,but also can be used to explain the distribution of RTS amplitude.

  • RF-CMOS Modeling:An Improved Accumulation-Mode MOS Varactor Model

    Liu Jun, Sun Lingling, Wen Jincai

    Chin. J. Semicond.  2007, 28(9): 1448

    Abstract PDF

    An improved model for accumulation-mode MOS varactor RF devices that can describe the characteristics of the device with simple equations valid in all operating regions is presented.Equations of the improved model are continuous and differentiable to any order.Derivative results fit measurements accurately to three orders at least.Drawbacks,such as derivability but with wrong results and noncontinuous voltage dependent resistance,are solved.The model is finally used to model a 30-gate-finger (channel mask length,L=1μm,finger width,W=4.76μm) accumulation-mode MOS varactor,which is fabricated with a 0.25μm RF-CMOS process supplied by Chartered Semiconductor Manufacture Ltd.(CSM) RF-CMOS technology.Comparison between the simulated and measured C-V,R-V,Q-factor characteristics,and S-parameters up to 39GHz demonstrates the excellent accuracy of the model.

  • A Tunable Micromechanical Capacitor Driven by Electrostatic Force

    Fang Dongming, Fu Shi, Zhou Yong, Zhao Xiaolin

    Chin. J. Semicond.  2007, 28(9): 1454

    Abstract PDF

    A radio frequency (RF) tunable micromechanical capacitor with a high quality factor driven by the electrostatic force was fabricated using simple MEMS technology.The surface profile and the displacement of the variable capacitor at different values of applied voltage are measured by using a WYKO NT1100 optical surface profiler.The measured results show that the pull-in voltage is 13.5V,the tuning ratio of the capacitor is 13.1∶1,and the quality factor and the capacitance are 51.6 and 0.79pF at 1GHz,respectively.

  • Analytical Solutions for Thermal Stresses in the Core of Silica-on-Silicon Waveguide

    Huang Huamao, Huang Dexiu, Liu Wen

    Chin. J. Semicond.  2007, 28(9): 1459

    Abstract PDF

    Elastic multilayer theory and stress concentration in buried channel waveguides are combined to obtain analytical solutions for thermal stress in the core of silica-on-silicon waveguides.Then the closed-form expression of stress anisotropy is obtained.It is shown that the anisotropy of thermal stress in conventional AWG comes from the initial warp and the thermal-expansion mismatch between waveguide layers.A complete analysis shows that the stress anisotropy can be minimized by tuning one of four parameters,including the thermal expansion coefficients of the substrate and upper cladding,and the thicknesses of the substrate and lower cladding,or by attaching a metal plate with proper thickness on the bottom of the arrayed waveguide.

  • Simulation of SU-8 Photoresist Profile in Deep UV Lithography

    Feng Ming, Huang Qing’an, Li Weihua, Zhou Zaifa, Zhu Zhen

    Chin. J. Semicond.  2007, 28(9): 1465

    Abstract PDF

    A new simulation method is proposed which considers diffraction,reflection,refraction,energy loss,absorption coefficient change,post-bake,and development.Compared with previous simulation methods,the present results show good agreement with experimental results.This shows that the simulation accuracy is increased.It is useful for the research of SU-8 phoptoresist deep UV lithography processes and micro-electro-mechanical system design.

  • CMOS UHF Rectifier

    Zhou Shenghua, Wu Nanjian

    Chin. J. Semicond.  2007, 28(9): 1471

    Abstract PDF

    This paper presents an RF CMOS rectifier for a passive UHF RFID tag chip.The rectifier includes an RF-DC converter,a bias,a DC-DC converter,and an oscillator.The operating frequency range of the rectifier is 860~960MHz.The design of the rectifier is based on 0.18μm,1p6m standard digital CMOS process.A switched capacitor circuit technique is used to provide active bias to solve the threshold voltage problem in CMOS transistors.The size of the rectifier is 180μm×140μm.Under -16dBm,900MHz input RF power,the rectifier creates 1.2V Vpp output,and the startup time is 980μs.

  • Novel Driver for Class-D Audio Power Amplifier

    Ye Qiang, Lai Xinquan, Dai Guoding, Wang Hui, Xu Luping

    Chin. J. Semicond.  2007, 28(9): 1477

    Abstract PDF

    In order to improve driver efficiency,a high power supply in the design of class-D audio power amplifiers is needed to drive the high-side LDNMOS of H-bridges.A novel driver circuit is presented to solve this problem.A charge pump circuit is used in the design.With the operation of the chip,the power supply for the low-side LDNMOS transistor of the H-bridge is clamped at 5.5V by a charge pump capacitor,and the power supply for the high-side LDNMOS transistor of the H-bridge reaches 18.8V by a bootstrap capacitor.The bootstrapped power supply minimizes the number of high-voltage power-supply levels externally supplied to the system and improves the efficiency.A stereo class-D audio power amplifier with this circuit is implemented in a TSMC06BCD process.The results indicate that its efficiency could be as high as 89.67%,and the high-side and low-side RDSON is 320mΩ,PSRR is -62dB,and its THD is as low as 0.1%.This shows that the circuit works effectively.

  • Design,Fabrication,and Characterization of a High-Performance Monolithic Triaxial Piezoresistive High-gAccelerometer

    Dong Peitao, Li Xinxin, Zhang Kun, Wu Xuezhong, Li Shengyi, Feng Songlin

    Chin. J. Semicond.  2007, 28(9): 1482

    Abstract PDF

    A silicon machined high-performance monolithic triaxial piezoresistive accelerometer is developed for measurements on the order of 100,000g.A three-beam-mass scheme with tiny beams is developed for the xand yaxial elements,and a three-beam-twin-mass structure is developed for thez axial element.Both of these structures feature high sensitivity and high resonance frequency compared with a conventional cantilever structure or cantilever-mass structure.ANSYS is used to analyze and optically design the accelerometer.The three sensing elements are monolithically integrated by micromachining techniques of double-sided deep etching combined with piezoresistive processes.The middle structure silicon layer is anodic bonded with glass substrate and BCB bonded with a top cap silicon layer for the purpose of plastic packaging to improve the reliability of the accelerometer.A dropping-bar system is used to characterize the accelerometer.The sensitivities in the x,y,and z axes are measured to be 2.28,2.36,and 2.52μV/g,respectively,while the corresponding resonant frequencies are 309,302,and 156kHz.Using a Dongling shock test machine,the nonlinearity is tested by comparison calibration and measured to be 1.4% and 1.8% for the y and z axial elements,respectively.

  • A CMOS Sampling Switch for 14bit 50MHz Pipelined A/D Converter

    Hu Xiaoyu, Zhou Yumei

    Chin. J. Semicond.  2007, 28(9): 1488

    Abstract PDF

    We discuss major factors that affect the performance of a CMOS analog sampling switch.We also propose a novel architecture that is aimed to compensate the effects of clock feedthrough in Bootstrapped switches.It breaks the tradeoff between speed and resolution in Bootstrapped switch design.The entire circuit is simulated by Hspice in SMIC’s 0.25μm standard CMOS AMS process.The proposed sampling switch achieves a spurious free dynamic range of 92dB and signal to noise and distortion ratio of 82dB for a 233MHz,2V Vp-p input signal,sampled at a rate of 50MS/s,clock rise/fall time 0.1ns.Also,the maximum hold step error is reduced from 5.5mV to 90μV.This method is especially useful for high speed high resolution ADCs.


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