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Volume 29, Issue 8, Aug 2008


  • Room Temperature Blue-UV Electroluminescence from ZnO Light-Emitting Diodes Involving Na-Doped p-Type ZnO and ZnO/ZnMgO Multi-Quantum Wells

    Ye Zhizhen, Lin Shisheng, He Haiping, Gu Xiuquan, Chen Lingxiang, Lü Jianguo, Huang Jingyun, Zhu Liping, Wang Lei, Zhang Yinzhu, Li Xianhang

    J. Semicond.  2008, 29(8): 1433

    Abstract PDF

    Using ZnO/Zn0.9Mg0.1O multi-quantum wells as active layer and Na as acceptor dopant of ZnO, we fabricate ZnO light-emitting diode (LED) on silicon substrate. We observe strong blue-violet emission and negligible defect emission from this device under low current injection at room temperature. This work could have significant impact on the practical application of ZnO LED.

  • Preparation of (SiFe)C DMS Based 4H-SiC Substrate

    Jiang Yanfeng, Wang Jianping

    J. Semicond.  2008, 29(8): 1436

    Abstract PDF

    A diluted magnetic 4H-SiC has been prepared by implanting Fe ions into the substrate.Its Curie temperature reaches as high as 320K and its technology is compatible with current IC.Moreover,the process includes three annealing steps,named HNH annealing in this paper.Each step during this annealing has been analyzed.Comparisons have been made with different Fe concentrations and experimental results demonstrate that when the concentration of Fe is 0.051,the Curie temperature is the highest.According to measurements,some explanation of this phenomenon is given.

  • A Monolithic InGaP/GaAs HBT Power Amplifier Design with Improved Gain Flatness

    Zhu Min, Yin Junjian, Zhang Haiying

    J. Semicond.  2008, 29(8): 1441

    Abstract PDF

    A monolithic power amplifier designed for 3GHz communication applications with improved gain flatness is studied based on InGaP/GaAs hetero-junction bipolar transistor technology in a commercial foundry.To improve gain flatness in a simple way,no external component was used in the real circuit except the decoupled bypass capacitors and RF choke.The measured linear gain is 23dB with gain flatness of ±0.25dB,satisfying the design goal and matching well with simulation results.This 2-stage power amplifier can deliver 31dBm linear output power and 44% power-added efficiency in the 400MHz bandwidth.The successful design with improved gain flatness is the result of superior distortion compensation and a coil model used as the RF choke.

  • An 8GHz Internally Matched AlGaN/GaN HEMT Power Amplifier with RC Stability Network

    Zeng Xuan, Chen Xiaojuan, Liu Guoguo, Yuan Tingting, Chen Zhongzi, Zhang Hui, Wang Liang, Li Chengzhan, Pang Lei, Liu Xinyu, Liu Jian

    J. Semicond.  2008, 29(8): 1445

    Abstract PDF

    8GHz 20W internally matched AlGaN/GaN HEMTs have been developed.The input and output matching networks are realised with microstrip lines on a 0.381mm thick alumina substrate.To improve the stability factor K of the device,a lossy RC network is used at the input of the device.The developed internally matched power amplifier module exhibits 43dBm (20W) power output with a 7.3dB linear gain,38.1% PAE,and combined power efficiency of 70.6% at 8GHz.

  • A Novel 4/5 Prescaler with Automatic Power Down

    Zeng Longyue, Zhu Siqi, Yan Yuepeng

    J. Semicond.  2008, 29(8): 1449

    Abstract PDF

    An "automatic power down" method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode.Implemented with the TSMC 0.25μm mixed-signal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique.The simulation results show that the new 4/5 prescaler is immune to the "wake-up" issue and thereby retains the same maximum operating frequency as the conventional prescaler.An integer-N divider with this proposed prescaler and with the division ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the conventional 4/5 prescaler.

  • Laterally Electrostatically Driven Poly 3C-SiC Folded-Beam Resonant Microstructures

    Wang Liang, Zhao Yongmei, Ning Jin, Sun Guosheng, Wang Lei, Liu Xingfang, Zhao Wanshun, Zeng Yiping, Li Jinmin

    J. Semicond.  2008, 29(8): 1453

    Abstract PDF

    Micromachined comb-drive electrostatic resonators with folded-cantilever beams were designed and fabricated.A combination of Rayleigh’s method and finite-element analysis was used to calculate the resonant frequency drift as we adjusted the device geometry and material parameters.Three micromachined lateral resonant resonators with different beam widths were fabricated.Their resonant frequencies were experimentally measured to be 64.5,147.2,and 2555kHz,respectively,which are in good agreement with the simulated resonant frequency.It is shown that an improved frequency performance could be obtained on the poly 3C-SiC based device structural material systems with high Young’s modulus.

  • A Ka Broadband High Gain Monolithic LNA with a Noise Figure of 2dB

    Huang Qinghua, Liu Xunchun, Hao Mingli, Zhang Zongnan, Yang Hao

    J. Semicond.  2008, 29(8): 1457

    Abstract PDF

    A four-stage monolithic microwave integrated circuits (MMIC) low noise amplifier (LNA) operating from 23 to 36GHz is reported using commercially available 0.15μm PHEMT technology.The LNA is self-biased.To achieve a low noise characteristic,careful optimizations of gate width are performed to reduce gate resistance.Absorption circuits and an elaborate bias structure with a resistor-capacitor network are employed to improve stability.Multiple resonance points and negative feedback technologies are used to widen the bandwidth.Measurements show a noise figure (NF) of less than 2.0dB,and the lowest NF is only 1.6dB at a frequency of 31GHz.In the whole operation band,the LNA has a gain of higher than 26dB,and an input return loss and output return loss of more than 11 and 13dB,respectively.The output power at 1dB compression gain of 36GHz is about 14dBm.The chip area is 2.4mm×1mm.

  • A Frequency-Independent Equivalent Circuit for High-kStacked Monolithic Transformers

    Xia Jun, Wang Zhigong, Li Wei

    J. Semicond.  2008, 29(8): 1461

    Abstract PDF

    A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed.The model parameters are extracted with high precision,mainly based on analytical methods.The developed model enables fast and accurate time domain transient analysis and noise analysis in RFIC simulation since all elements in the model are frequency independent.The validity of the proposed model has been demonstrated by a fabricated monolithic stacked transformer in TSMC's 0.13μm mixed-signal (MS)/RF CMOS process.


  • Growth Mechanism of Microcrystalline Silicon Films by Scaling Theory and Monte Carlo Simulation

    Zi Wei, Zhou Yuqin, Liu Fengzhen, Zhu Meifang

    J. Semicond.  2008, 29(8): 1465

    Abstract PDF

    Hydrogenated microcrystalline silicon (μc-Si:H) films with a high deposition rate of 1.2nm/s were prepared by hot-wire chemical vapor deposition (HWCVD).The growth-front roughening processes of the μc-Si:H films were investigated by atomic force microscopy.According to the scaling theory,the growth exponent β≈0.67,the roughness exponent α≈0.80,and the dynamic exponent 1/z=0.40 are obtained.These scaling exponents cannot be explained well by the known growth models.An attempt at Monte Carlo simulation has been made to describe the growth process of μc-Si:H film using a particle reemission model where the incident flux distribution,the type and concentration of growth radical,and sticking,reemission,shadowing mechanisms all contributed to the growing morphology.

  • Low-Temperature Growth and Photoluminescence of SnO2 Nanowires

    Wang Bing, Xu Ping, Yang Guowei

    J. Semicond.  2008, 29(8): 1469

    Abstract PDF

    SnO2 nanowires with a diameter of 25nm are synthesized at 550℃ by Au-Ag catalyst assisted thermal evaporation of SnO powders.The room-temperature photoluminescence spectra (PL) of the prepared nanowires are measured.Among the four PL peaks,the peak of 418nm is newly observed.This peak is caused by the plane defects of the twinned crystal nanowires.The formation of SnO2 nanowires at low temperature is pursued on the basis of the VLS mechanism and application of the reaction source of SnO.We suggest that the chemical reactions of the low temperature and low concentration of the vaporized species are responsible for the thinner size of the SnO2 nanowires.

  • Optimization and Analysis of Magnesium Doping in MOCVD Grown p-GaN

    Zhang Xiaomin, Wang Yanjie, Yang Ziwen, Liao Hui, Chen Weihua, Li Ding, Li Rui, Yang Zhijian, Zhang Guoyi, Hu Xiaodong

    J. Semicond.  2008, 29(8): 1475

    Abstract PDF

    p-type conductivity and crystal quality of Mg-doped GaN grown by MOCVD have been improved through optimization of the magnesium flow rate.The hole concentration first increased and then decreased with the magnesium flow rate while the mobility decreased monotonously.The optimum sample reached a hole concentration of 4.1E17cm-3 and a resistivity of 1Ω·cm.Based on a self-compensation model involving the deep donor MGaVN,we calculate the hole concentration as a function of magnesium doping concentration NA,which indicates that the self-compensation coefficient increases with NA;the hole concentration first increases with NA and reaches a maximum at NA≈4E19,then decreases rapidly as doping concentration increases.XRD also indicate that dislocation density decreased as magnesium flow rate decreased.

  • Effect of Surface Potential Barrier on the Electron Energy Distribution of NEA Photocathodes

    Zou Jijun, Yang Zhi, Qiao Jianliang, Chang Benkang, Zeng Yiping

    J. Semicond.  2008, 29(8): 1479

    Abstract PDF

    By calculating the energy distribution of electrons reaching the photocathode surface and solving the Schrdinger equation that describes the behavior of an electron tunneling through the surface potential barrier,we obtain an equation to calculate the emitted electron energy distribution of transmission-mode NEA GaAs photocathodes.According to the equation,we study the effect of cathode surface potential barrier on the electron energy distribution and find a significant effect of the barrier-I thickness or end height,especially the thickness,on the quantum efficiency of the cathode.Barrier II has an effect on the electron energy spread,and an increase in the vacuum level will lead to a narrower electron energy spread while sacrificing a certain amount of cathode quantum efficiency.The equation is also used to fit the measured electron energy distribution curve of the transmission-mode cathode and the parameters of the surface barrier are obtained from the fitting.The theoretical curve is in good agreement with the experimental curve.

  • Field Emission from a Mixture of Amorphous Carbon and Carbon Nanotubes Films

    Zhang Xinyue, Yao Ning, Wang Yingjian, Zhang Binglin

    J. Semicond.  2008, 29(8): 1484

    Abstract PDF

    A mixture of amorphous carbon and carbon nanotubes films was synthesized on stainless steel plates by a microwave plasma enhanced chemical vapor deposition system.The source gases were hydrogen and methane with flow rates of 100 and 16sccm,respectively,with a total pressure of 5.0kPa.The surface morphology and the structure of the films were characterized by field emission scanning electron microscopy (SEM) and Raman scattering spectroscopy.Field emission properties of as-deposited film were measured in a vacuum room below 5E-5 Pa.The experimental results show that the initial turn-on field is 0.9V/μm;The current density is 4.0mA/cm2 and the emission sites are dense and uniform at an electric field of 3.7V/μm.These results indicate that such a mixture of amorphous carbon and carbon nanotubes films is a promising material for field emission applications.

  • Gate Annealing of an Enhancement-Mode InGaP/AlGaAs/InGaAs PHEMT

    Li Ming, Zhang Haiying, Xu Jingbo, Li Xiao, Liu Liang, Fu Xiaojun

    J. Semicond.  2008, 29(8): 1487

    Abstract PDF

    For enhancement-mode InGaP/AlGaAs/InGaAs PHEMTs,gate annealing is conducted between gate structures of Ti/Pt/Au and Pt/Ti/Pt/Au.Comparison is made after thermal annealing and an optimum annealing process is obtained.Using the structure of Ti/Pt/Au,about a 200mV positive shift of threshold voltage is achieved by thermal annealing at 320℃ for 40min in N2 ambient.Finally,a stable and consistent enhancement-mode PHEMT is produced successfully with higher threshold voltage

  • Influence of Heterojunction Position on SiGe HBTs with Graded BC Junctions

    Luo Rui, Zhang Wei, Fu Jun, Liu Daoguang, Yan Liren

    J. Semicond.  2008, 29(8): 1491

    Abstract PDF

    The influence of a heterojunction in the vicinity of a graded BC junction on the performance of npn SiGe HBTs is studied.SiGe HBTs differing only in heterojunction position in the vicinity of a graded BC junction are simulated by means of 2D Medici software for DC current gain and frequency characteristics.In addition,the simulated DC current gains and cut-off frequencies are compared at different collector-emitter bias voltages.Through the simulation results,both DC and HF device performance are found to be strongly impacted by degree of confinement of the neutral base in the SiGe layer, even in the absence of a conduction band barrier.This conclusion is of significance for designing and analyzing SiGe HBTs.

  • A 16×16 Micro Mirror Array for Optical Switches

    Chen Qinghua, Wu Wengang, Wang Ziqian, Yan Guizhen, Hao Yilong

    J. Semicond.  2008, 29(8): 1496

    Abstract PDF

    This paper reports on the design,fabrication,and performance of a high-reflectivity large-rotation mirror array for MEMS (micro-electro-mechanical system) 16×16 optical switches.The mirror in the array can enlarge its rotation angles up to 90. and keep a steady state to steer the optical signal.According to the large-rotation behavior,an electro-mechanical model of the mirror is presented.By monolithic integration of fiber grooves and mirrors fabricated by a surface and bulk hybrid micromachining process,the coarse passive alignment of fiber-mirror-fiber can be achieved.The reflectivity of the mirror is measured to be 93.1%~96.3%.The switches demonstrate that the smallest fiber-mirror-fiber insertion loss is 2.1dB using OptiFocusTM collimating lensed fibers.Moreover,only about ±0.01dB oscillating amplitude of insertion loss is provoked after the device is tested for 15min for 5~90Hz in the vertical vibration amplitude of 3mm.

  • Triplexers Based on SOI Flattop AWGs

    An Junming, Wu Yuanda, Li Jian, Wang Hongjie, Li Jianguang, Li Junyi, Hu Xiongwei

    J. Semicond.  2008, 29(8): 1504

    Abstract PDF

    Triplexers are designed based on SOI flattop arrayed waveguide gratings (AWGs).Three wavelengths (1310,1490,and 1550nm) operate at three diffraction orders of AWGs.Simulation shows that the 3dB bandwidth,crosstalk,and loss are 6nm,less than -40dB,and 5dB,respectively.The output optical fields of the device fabricated in our laboratory are clear and show a good triplexing function.

  • A Capacitor-Free CMOS Low-Dropout Regulator for System-on-Chip Application

    Han Peng, Wang Zhigong, Xu Yong, Li Wei

    J. Semicond.  2008, 29(8): 1507

    Abstract PDF

    A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presented.By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique,high stability is achieved without an off-chip capacitor.The chip was implemented in CSMC's 0.5μm CMOS technology and the die area is 600μm×480μm.The error of the output voltage due to line variation is less than ±0.21%,and the quiescent current is 39.8μA.The power supply rejection ratio at 100kHz is -33.9dB,and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV/Hz,respectively.

  • A Low Jitter PLL in a 90nm CMOS Digital Process

    Yin Haifeng, Wang Feng, Liu Jun, Mao Zhigang

    J. Semicond.  2008, 29(8): 1511

    Abstract PDF

    A low jitter phase-locked loop (PLL) that does not need analog resistors and capacitors is designed and fabricated in a 90nm CMOS digital process.The metal parasitic capacitor is used in the PLL loop filter.Test results show that when the PLL is locked on 1.989GHz,the RMS jitter is 3.7977ps,the peak-to-peak jitter is 31.225ps,and the power consumption is about 9mW.The locked output frequency range is from 125MHz to 2.7GHz.

  • A High-PSRR CMOS Bandgap Reference Without Resistor

    Zhou Qianneng, Wang Yongsheng, Yu Mingyan, Ye Yizheng, Li Hongjuan

    J. Semicond.  2008, 29(8): 1517

    Abstract PDF

    A CMOS bandgap reference (BGR) without a resistor,with a high power supply rejection ratio and output below 1V is proposed.The circuit is suited for on-chip voltage down converters.The BGR is designed and fabricated using an HJTC 0.18μm CMOS process.The silicon area is only 0.031mm2 excluding pads and electrostatic-discharge (ESD) protection circuits.Experimental results show that the PSRR of the proposed BGR at 100Hz and 1kHz achieves,respectively,-70 and -62dB using the pre-regulator.The proposed BGR circuit generates an output voltage of 0.5582V with a variation of 1.5mV in a temperature range from 0 to 85℃.The deviation of the output voltage is within 2mV when the power supply voltage VDD changes from 2.4 to 4V.

  • A CMOS Voltage Reference Based on VGS and ΔVGS in the Weak Inversion Region

    Xia Xiaojuan, Xie Liang, Sun Weifeng

    J. Semicond.  2008, 29(8): 1523

    Abstract PDF

    A CMOS voltage reference,which is based on VGS and ΔVGS in the weak inversion region,has been designed and implemented in standard 0.6μm CMOS technology.No diodes and parasitic bipolar junction transistors (BJTs) are used.The proposed voltage reference uses a current-mode topology by summing a PTAT current and a CTAT current into a resistor to generate the required reference voltage.It can also provide more than one reference voltage output,which is quite suitable for systems requiring many different reference voltages simultaneously.The occupied chip area is 0.023mm2.The operation supply voltage is from 2.5 to 6V,and the maximum supply current is 8.25μA.The designed three different outputs are respectively about 203mV,1.0V,and 2.05V at room temperature when the supply voltage is 4V.The circuit achieves a temperature coefficient of 31ppm/℃ in the temperature range of 0 to 100℃ and an average line regulation of ±0.203%/V.The voltage reference has been successfully applied in a white LED backlight driver chip.

  • Design of a Bandgap Reference with a Wide Supply Voltage Range

    Sun Yueming, Zhao Menglian, Wu Xiaobo

    J. Semicond.  2008, 29(8): 1529

    Abstract PDF

    An on-chip voltage reference with a wide supply voltage range is required by some applications,especially that of power management (PM) controller chips applied to telecommunication,automotive,lighting equipment,etc.,when high power supply voltage is needed.Accordingly,a new bandgap reference with a wide supply voltage range is proposed.Due to the improved structure,it features a high power supply rejection ratio (PSRR) and high temperature stability.In addition,an auxiliary micro-power reference is introduced to support the sleep mode of the PM chip and reduce its standby power consumption.The auxiliary reference provides bias currents in normal mode and a 1.28V reference voltage in sleep mode to replace the main reference and save power.Simulation results show that the reference provides a reference voltage of 1.27V,which has a 3.5mV drift over the temperature range from -20 to 120℃ and 56μV deviation over a supply voltage range from 3 to 40V.The PSRR is higher than 100dB for frequency below 10kHz.The circuit was completed in 1.5μm BCD (Bipolar-CMOS-DMOS) technology.The experimental results show that all main expectations are achieved.

  • Bound Polaron in Wurtzite Nitrides Semiconductor and Pressure Effect

    Xue Yaguang, Yan Zuwei, Huangfu Yanfang

    J. Semicond.  2008, 29(8): 1535

    Abstract PDF

    A variational approach is used to study the polaron effect from both the abnormal optical LO-like and TO-like phonons on the binding energies of impurity states in wurtzite nitrides semiconductor crystals by considering the uniaxial anisotropy.Taking the variations of electronic effective mass,material dielectric constants and crystal lattice vibrational frequencies with hydrostatic pressure into account,the pressure effect on the binding energy of bound polaron is discussed.The numerical results show that the polaron effect obviously decreases the binding energy,and the contributions from impurity-LO-like phonon interaction to the polaron effect are dominant.It is also found that pressure enhances the binding energy and its anisotropy.

  • Bulk Single Crystal Growth and Properties of In-Doped ZnO

    Zhang Fan, Zhao Youwen, Dong Zhiyuan, Zhang Rui, Yang Jun

    J. Semicond.  2008, 29(8): 1540

    Abstract PDF

    The Hall effect,XPS,optical absorption,Raman scattering,and cathode luminescence have been used to study the electrical properties,crystal quality,and defects of indium-doped bulk ZnO single crystals grown by the chemical vapor transport (CVT) method.Indium doped n-type ZnO single crystals with a carrier concentration of 1E18~1E19cm-3 have been obtained reproducibly by CVT.The doped indium exhibits high activation efficiency as a shallow donor in a ZnO single crystal.As doping concentration increases,the optical absorption and electrical properties of the In-ZnO change significantly.Defects and their influence on the In-ZnO single crystals have been analyzed.

  • An Experimental Study of Aluminum-Induced Crystallization of Amorphous Silicon Thin Film in Different Atmospheres

    Wang Chenglong, Fan Duowang, Sun Shuo, Zhang Fujia

    J. Semicond.  2008, 29(8): 1544

    Abstract PDF

    The influence of annealing atmosphere on the aluminum-induced crystallization (AIC) of a-Si film has been studied by X-ray diffraction spectroscopy,Raman spectroscopy,and scanning electron microscopy.The films were annealed in different annealing atmospheres,i.e.,H2,N2 and air.The Al and amorphous silicon films were deposited by DC magnetron sputtering on glass substrate.The XRD results indicate that the a-Si film was crystallized to poly-Si when the sample was annealed in H2 at 400℃ for 90min.The results of Raman spectroscopy show that the crystallinity of the samples after annealing in H2 is the maximum and the samples after annealing in air is the lowest under the same conditions,such as annealing temperature (500℃) and annealing time.The experimental results indicate that H2 stimulates the crystallization of a-Si films during high temperature annealing in hydrogen by both breaking the weak bonding of Si-Si and accelerating the overflow rate of O.2 from the a-Si films.

  • Effect of n Doped Layers in an Amorphous Silicon Top Solar Cell on the Performance of "Micromorph" Tandem Solar Cells

    Han Xiaoyan, Li Guijun, Hou Guofu, Zhang Xiaodan, Zhang Dekun, Chen Xinliang, Wei Changchun, Sun Jian, Xue Junming, Zhang Jianjun, Zhao Ying, Geng Xinhua

    J. Semicond.  2008, 29(8): 1548

    Abstract PDF

    Pin/pin "micromorph" tandem solar cells were deposited by very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD).Tunnel recombination junctions of the "micromorph" tandem solar cells consisting of two microcrystalline-doped layers with a defect rich interface were developed.While the solar cells performed reasonably well under AM 1.5 lights,we found through spectral response measurements that the first deposited cell of the tandem structures was leaking under low light conditions.The insertion of a thin protection layer of n-type amorphous silicon is presented in this paper.The results shown that the introduced n-type amorphous silicon could improve the leakage phenomenon.The leakage phenomenon disappeared when the thickness of the n-type amorphous silicon was 6nm,leading to an increase in open-circuit voltage.The open-circuit voltage increased from 1.27 to 1.33V and FF increased from 60% to 63%.

  • TEM Observation on the Ground Damage of Monocrystalline Silicon Wafers

    Zhang Yinxia, Gao Wei, Kang Renke, Guo Dongming

    J. Semicond.  2008, 29(8): 1552

    Abstract PDF

    In order to understand the damage mechanism of the wafer rotation ground surface layer,this paper analyzes the ground damage characteristic with the aid of TEM.The results show that rough ground wafer surface layer damage is composed of a large quantity of microcracks and high density dislocations.Apart from the microcracks and dislocations,amorphous silicon and polycrystalline silicon (Si-I phase and Si-III phase) exist in the semi-fine and fine ground wafer surface layer damage.From rough grinding to semi-fine grinding,the amorphous layer depth increases from about 0 to about 110nm.From semi-fine grinding to fine grinding,the amorphous layer depth decreases from about 110 to about 30nm and the amorphous layer depth becomes uniform.From rough grinding to fine grinding,the subsurface damage depth,the depth of the microcracks,and the dislocation glide decrease gradually.From rough grinding to fine grinding,the material removal mode gradually changes from micro-fracture mode to ductile mode.

  • Development and Characteristic Analysis of MOS AlGaN/GaN HEMTs

    Wang Chong, Yue Yuanzheng, Ma Xiaohua, Hao Yue, Feng Qian, Zhang Jincheng

    J. Semicond.  2008, 29(8): 1557

    Abstract PDF

    The fabrication of MOS high electron mobility transistors on AlGaN/GaN heterostructures grown on sapphire substrates is reported.The gate-length is 1μm and the distance between the source and drain is 4μm.The 4nm SiO2 dielectric is evaporated by electron beam.These devices exhibit a maximum drain current of 718mA/mm at 4V,a maximum transconductance of 172mS/mm,an ft of 8.1GHz,and an fmax of 15.3GHz.The gate leakage current of the MOS HEMT is 2 orders lower than a Schottky gate HEMT.The thin SiO2 dielectric between gate and semiconductor is used to ensure the reduction of gate leakage current and to ensure the transconductance of the devices is not impacted.

  • A Macromodel and Parameter Optimization for the I-V Characteristics of High-Voltage MOSFETs

    Xu Jiayi, Shi Yanling, Ren Zheng, Hu Shaojian, Wan Xinggong, Ding Yanfang, Lai Zongsheng

    J. Semicond.  2008, 29(8): 1561

    Abstract PDF

    This paper presents a macromodel applied to a high-voltage double diffused drain MOSFET (HV DDDMOSFET) after analyzing the distortion between measured curves and simulated curves obtained by the SPICE BSIM model.The macromodel is composed of regular SPICE devices,such as general nMOSFETs,MESFETs and diodes.The structure of the macromodel is simple.It is convenient to use,and it can describe the I-V characteristics correctly.In order to improve the scalability of the macromodel,the MESFET’s parameter K1 (threshold voltage sensitivity to bulk node) has been optimized.A quasi-empirical expression between K1 and W/L of MOSFET has been obtained,which allows the macromodel to fit devices in different dimensions.The practicality of the model has been improved greatly.This scalable macromodel can be widely used in general EDA tools based on the SPICE model.

  • Transient Characteristic Analysis of a Double-Gate Dual-Strained-Channel SOI CMOS

    Sun Liwei, Gao Yong, Yang Yuan, Liu Jing

    J. Semicond.  2008, 29(8): 1566

    Abstract PDF

    Transient characteristic analysis of a CMOS circuit based on a double-gate dual-strained channel SOI MOSFET with the effective gate length scaling down to 25nm is presented.As a result of simulations,by the adoption of a single-gate (SG) control mechanism,the conversion time from logic 1 to logic 0 is shorter for conventional strained-Si CMOS than unstrained CMOS.Furthermore,the conversion time from logic 0 to logic 1 can be reduced by the application of a strained-SiGe CMOS circuit.However,the CMOS circuit based on the novel structure can reduce tHL and tLH simultaneously.By the adoption of a double-gate (DG) control mechanism,the conversion time of the CMOS circuit shows a dramatic reduction compared with the SG control mechanism and the performance of the CMOS circuit can be improved significantly.

  • A New Hydrodynamic Model Method for Semiconductor Device Simulation

    Liu Zhan, Gu Xiaofeng, Yu Zongguang, Hu Xiduo, Zang Jiafeng

    J. Semicond.  2008, 29(8): 1570

    Abstract PDF

    The solution using a spline procedure,SADI,and a high-order compact finite difference (HOC) method is presented for the hydrodynamic (HD) model for semiconductor device simulation.We compare the numerical results with two of the most popular simulation methods currently,CGS and Newton-SOR.Our method decreases the number of iterations by 40% and reduces the computation time greatly.

  • An Electroluminescence and Emission Mechanism for Small Molecular Doped Polymer Light-Emitting Diodes

    Nie Hai, Tang Xianzhong, Chen Zhu, Wu Lijuan

    J. Semicond.  2008, 29(8): 1575

    Abstract PDF

    Small-molecule doped polymer light-emitting diodes have been fabricated using a novel PTPD (poly-TPD) as the hole transport material and highly fluorescent Rubrene as the dopant.Electroluminescent characteristics of different doped concentrations are studied at different voltages.The results indicate doping can control luminescence color.EL spectra and PL spectra have been investigated in Rubrene doped PTPD devices.Experiments indicate the presence of energy transfer and charge transfer from PTPD to Rubrene for PL and the presence of energy transfer and carrier trapping from PTPD to Rubrene for EL.The EL emission mechanism for doped devices is carrier trapping and Forster energy transfer processes working together.

  • Thermal Crosstalk of Micro Hotplate Arrays

    Yu Jun, Tang Zhen’an, Huang Zhengxing, Chen P C H

    J. Semicond.  2008, 29(8): 1581

    Abstract PDF

    In the chips of integrated micro hotplate (MHP) arrays,thermal crosstalk affects the accuracy of MHP temperature control.In silicon chips,thermal crosstalk effect is mainly dependant on the distance between the elements in the system and the thermal properties of the package.This paper constructs a thermal circuit for an MHP array and discusses the thermal crosstalk.The results show that the thermal resistance of the MHP structure is 3 magnitudes higher than the thermal resistance of the silicon substrate.Thus,the thermal crosstalk is not dependant on the distance between the MHPs but mainly depends on the thermal resistance of the package.Three MHP arrays with different layouts are fabricated and packaged in TO5 or DIP16.The experimental data support the results of the thermal circuit.Therefore,the key to reducing the thermal crosstalk of the integrated MHP systems is to use a low thermal resistance package and to enlarge the thermal resistance of the MHP structure as much as possible.

  • A New Photoionization Cross Section Measurement Technique Based on PID Control

    Wang Ying, Li Xinhua

    J. Semicond.  2008, 29(8): 1585

    Abstract PDF

    A new method based on proportional-integral-derivative (PID) control is proposed to measure photoionization cross sections in GaN materials by analysis of release and recaptures carriers of deep centers by incident light.The measurement results of photoionization cross sections on GaN by this method are consistent with the photoionization spectrum in HEMTs reported by Klein.These results indicate that the photoionization cross section technology based on PID control can measure precisely deep level photoionization cross sections in GaN material.Compared with existing techniques,this method is more operable and applicable.It can serve as a new ‘fingerprint’ analysis method in deep level center detection in GaN .

  • Development of a Displacement Sensor with a Sidewall Piezoresistor and Its Typical Application

    Sun Lining, Wang Jiachou, Rong Weibin, Li Xinxin

    J. Semicond.  2008, 29(8): 1589

    Abstract PDF

    For improving displacement sensor sensitivity to detect the motion in-plane and to improve the vertical sidewall surface,a new displacement sensor used for detecting motion in-plane is proposed.Piezoresistor technology is compatible with the other micromachining technology.This sensor can be integrated with other devices easily and fabricated with ion implantation technology combined with deep reactive ion etching technology.This design doubles the sensitivity compared with the conventional design because it puts the piezoresistor on the surface of the vertical sidewall of the detection beam.Besides using vertical sidewall piezoresistor technology,this displacement sensor has been applied to a micro xy-stage to detect the stage motion successfully.The experimental results verify that the sensitivity of the fabricated displacement sensors is better than 0.903mV/μm,the linearity is better than 0.814%,and the displacement resolution is better than 12.3nm.

  • CMOS Implementation of an RF PLL Synthesizer for Use in RFID Systems

    Xie Weifu, Li Yongming, Zhang Chun, Wang Zhihua

    J. Semicond.  2008, 29(8): 1595

    Abstract PDF

    An integrated RF PLL frequency synthesizer for use in RFID systems is presented.It integrates a voltage-controlled oscillator,phase frequency detector,charge pump,high-frequency dual-modulus divider,and digital programmable divider.The frequency synthesizer was implemented in a 0.18μm CMOS process.It uses a 13MHz crystal oscillator as input.The output range is from 860 to 960MHz,the phase margin is -123dBc/1MHz,the frequency step is 200kHz,and the change frequency is within 150μs.

  • A Novel Fully On-Chip CMOS Low-Dropout Linear Regulator with Ultra Low Noise

    Mao Cui, He Lenian, Yan Xiaolang

    J. Semicond.  2008, 29(8): 1602

    Abstract PDF

    A fully on-chip low-dropout linear regulator (LDO) with ultra low noise is presented.This regulator uses a Vt/R based voltage reference rather than a commonly used bandgap reference to minimize the noise introduced by the reference voltage. The Vt/R based voltage reference employs a digital calibration schema to increase the accuracy of the output voltage.This fully on-chip LDO is designed in a TSMC 0.18μm RF CMOS process for the power supply of a low phase noise phase lock loop (PLL) with 10mA of DC current consumption.The simulation results indicate that the total output noise of the LDO is 26nV/Hz@100kHz and 14nV/Hz@1MHz,and the power supply reject ratio is -40dB@1MHz and less than -34dB in all frequency bands.The test results show that the phase noise of the PLL using this LDO is 6dBc@1kHz less and 2dBc@200kHz less than using conventional LDO.

  • A Stable Super-Regenerative Oscillator for Wireless Receivers

    Wang Huan, Wang Zhigong, Xu Jian, Meng Qiao, Yang Siyong, Li Wei

    J. Semicond.  2008, 29(8): 1608

    Abstract PDF

    A stable super-regenerative oscillator (SRO) for industrial scientific and medical wireless receivers has been implemented in standard 0.5μm CMOS technology.The startup time of the SRO is locked by a loop composed of a voltage-controlled SRO,an efficient envelope detector,and an accurate charge pump,which is similar to a phase-locked loop without input clock.This paper presents a discrete model with stability analysis and the key circuits of the loop.Under a 2.4~5.5V supply,the measured results indicate that the startup time of the SRO is independent of changes in technology,temperature,operating frequency,and supply voltage.

  • A 750mA,Dual-Mode PWM/PFM Step-Down DC-DC Converter with High Efficiency

    Chen Dongpo, He Lenian, Yan Xiaolang

    J. Semicond.  2008, 29(8): 1614

    Abstract PDF

    A 750mA output current,high stability,high efficiency step-down DC-DC converter with pulse-width modulation and pulse-frequency modulation modes is presented.Under nominal load current (>80mA),the converter operates in PWM mode with a fixed switching frequency of 1MHz.At light load current (<80mA),the converter enters PFM mode operation with reduced switching frequency and less quiescent current.Therefore,the converter achieves the highest efficiency over the entire load current range from 0.02 to 750mA.Moreover,an advanced fast response voltage mode control scheme achieves superior line and load regulation.The chip was implemented using a CSMC 0.5μm CMOS 2P3M mix-signal process.Simulation results indicate that the converter can automatically switch between PWM-mode and PFM-mode according to the load current.The maximum conversion efficiency is up to 96.5% and it is more than 55% at 0.02mA of load current.The proposed chip is especially suitable for portable systems powered by batteries.

  • Design of an On-Chip Gate Pulse Modulate Controller for a TFT-LCD

    Ye Qiang, Lai Xinquan, Chen Fuji, Li Yanming, Yuan Bing

    J. Semicond.  2008, 29(8): 1620

    Abstract PDF

    To prevent the flicker phenomenon on a liquid crystal and the feed through phenomenon in a gate driving unit of a liquid crystal display device,a gate pulse modulate controller is designed.It can minimize power consumption and reduce the coupling effect between gate line and pixel.It applies an output voltage with a time delay to the gate driving unit,thereby preventing erroneous operation of the liquid crystal display device.A current mode PWM Boost DC-DC converter and a charge pump employing this gate pulse modulate controller circuit have been implemented in a UMC 0.6μm-BCD process.The efficiency of the DC-DC converter is up to 93%,the output of the adjustable charge pump is 10~30V,and the results indicate that the circuit works well and effectively.The chip area of the gate pulse modulator circuit is 0.3mm2 and it consumes less than 1μA of quiescent current.

  • An Integrated Current-Sensing Circuit for Current-Mode DC-DC Buck Converters

    Yuan Bing, Lai Xinquan, Ye Qiang, Li Yanming, Jia Xinzhang

    J. Semicond.  2008, 29(8): 1627

    Abstract PDF

    A novel integrated CMOS current-sensing circuit for current-mode DC-DC buck converters is presented.The circuit is concise and simple to implement,and the power loss is low.Also,the achieved sense ratio is almost independent of temperature,model,and supply voltage after matching the MOSFETs.Through optimization,the response speed is faster and the minimum input voltage is lower.A current-mode DC-DC buck converter with the proposed structure has been fabricated in a 0.5μm CMOS process for validation.With a 2.5~5.5V input range,the chip works steadily in the load current range of 0~2A.It has a good transient response and the measured maximum efficiency is up to 96%.


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