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Volume 30, Issue 1, Jan 2009


  • Solution of the time-dependent Schrodinger equation with absorbing boundary conditions

    Chen Zhidong, Zhang Jinyu, Yu Zhiping

    J. Semicond.  2009, 30(1): 012001

    doi: 10.1088/1674-4926/30/1/012001

    Abstract PDF Get Citation

    The performances of absorbing boundary conditions (ABCs) in four widely used finite difference time domain (FDTD) methods, i.e. explicit, implicit, explicit staggered-time, and Chebyshev methods, for solving the time-dependent Schrdinger equation are assessed and compared. The computation efficiency for each approach is also evaluated. A typical evolution problem of a single Gaussian wave packet is chosen to demonstrate the performances of the four methods combined with ABCs. It is found that ABCs perfectly eliminate reflection in implicit and explicit staggered-time methods. However, small reflection still exists in explicit and Chebyshev methods even though ABCs are applied.


  • Improved optical performance of GaN grown on pattered sapphire substrate

    Yao Guangrui, Fan Guanghan, Li Shuti, Zhang Yong, Zhou Tianmin

    J. Semicond.  2009, 30(1): 013001

    doi: 10.1088/1674-4926/30/1/013001

    Abstract PDF Get Citation

    An improved GaN film with low dislocation density was grown on a C-face patterned sapphire substrate (PSS) by metalorganic chemical vapor deposition (MOCVD). The vapor phase epitaxy starts from the regions with no etched pits and then spreads laterally to form a continuous GaN film. The properties of the GaN film have been investigated by double crystal X-ray diffraction (DCXRD), atomic force microscopy (AFM) and photoluminescence (PL), respectively. The full-width at half-maximum (FWHM) of the X-ray diffraction curves (XRCs) for the GaN film grown on PSS in the (0002) plane and the (102) plane are as low as 312.80 arcsec and 298.08 acrsec, respectively. The root mean square (RMS) of the GaN film grown on PSS is 0.233 nm and the intensity of the PL peak is comparatively strong.


  • A novel GAAC FinFET transistor: device analysis, 3D TCAD simulation,and fabrication

    Xiao Deyuan, Wang Xi, Yuan Haijiang, Yu Yuehui, Xie Zhifeng, Chi Minhwa

    J. Semicond.  2009, 30(1): 014001

    doi: 10.1088/1674-4926/30/1/014001

    Abstract PDF Get Citation

    We report the analysis and TCAD results of a gate-all-around cylindrical (GAAC) FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. Thee Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-10 nm sizes.

  • Ultra high-speed InP/InGaAs DHBTs with ft of 203 GHz

    Su Yongbo, Jin Zhi, Cheng Wei, Liu Xinyu, Xu Anhuai, Qi Ming

    J. Semicond.  2009, 30(1): 014002

    doi: 10.1088/1674-4926/30/1/014002

    Abstract PDF Get Citation

    InP/InGaAs/InP double heterojunction bipolar transistors (DHBTs) were designed for wide band digital and analog circuits, and fabricated using a conventional mesa structure with benzocyclobutene (BCB) passivation and planarization process techniques. Our devices exhibit a maximum of 203 GHz, which is the highest for DHBTs in mainland China. The emitter size is 1.0*20 μm2. The DC current gain is 166, and BVCEO = 4.34 V. The devices reported here employ a 40 nm highly doped InGaAs base region and a 203 nm InGaAsP composite structure. They are suitable for high speed and intermediate power applications.

  • Characterization of the triple-gate flash memory endurancedegradation mechanism

    Cao Zigui, Sun Ling, Lee Elton

    J. Semicond.  2009, 30(1): 014003

    doi: 10.1088/1674-4926/30/1/014003

    Abstract PDF Get Citation

    Write/erase degradation after endurance cycling due to electron trapping events in triple-gate flash memory have been detected and analyzed using a UV erasure method. Different from the commonly degradation phenomenon, write-induced electron trapping in the floating gate oxide, electron trapping in tunneling oxide is observed in triple-gate flash memory. Further, the degradation due to single-electron locally trapping/de-trapping in horn-shaped SuperFlash does not occur in the triple-gate flash cell. This is because of planar poly-to-poly erasing in the triple-gate flash cell instead of tip erasing in the horn-shaped SuperFlash cell. Moreover, by TCAD simulation, the trap location is identified and the magnitude of its density is quantified roughly.

  • Effect of total ionizing dose radiation on the 0.25 μm RF PDSOI nMOSFETs with thin gate oxide

    Liu Mengxin, Han Zhengsheng, Bi Jinshun, Fan Xuemei, Liu Guang, Du Huan

    J. Semicond.  2009, 30(1): 014004

    doi: 10.1088/1674-4926/30/1/014004

    Abstract PDF Get Citation

    Thin gate oxide radio frequency(RF) PDSOI nMOSFETs that are suitable for integration with 0.1μm SOI CMOS technology are fabricated, and the total ionizingdose radiation responses of the nMOSFETs having four differentdevice structures are characterized and compared for an equivalentgamma dose up to 1 Mrad (Si), using the front and back gatethreshold voltages, off-state leakage, transconductance and outputcharacteristics to assess direct current (DC) performance. Moreover,the frequency response of these devices under total ionizing doseradiation is presented, such as small-signal current gain andmaximum available/stable gain. The results indicate that all the RFPDSOI nMOSFETs show significant degradation in both DC and RFcharacteristics after radiation, in particular to the float bodynMOS. By comparison with the gate backside body contact (GBBC)structure and the body tied to source (BTS) contact structure, the low barrier body contact (LBBC) structure is more effective and excellent in the hardness of total ionizing dose radiation although there are some sacrifices in drive current, switching speed and high frequency response.

  • Monolithic white LED based on AlxGaN1-x/InyGa1-yN DBR resonant-cavity

    Chen Yu, Huang Lirong, Zhu Shanshan

    J. Semicond.  2009, 30(1): 014005

    doi: 10.1088/1674-4926/30/1/014005

    Abstract PDF Get Citation

    A monolithic white light-emitting diode (LED) with blue and yellow light active regions has been designed and studied. With the AlGaN/InGaN distributed Bragg reflector (DBR) resonant-cavity, the extraction efficiency and power of the yellow light are enhanced so that high quality white light can be obtained.

  • Design and fabrication of an embedded wire-grid nanograting

    Zhou Libing, Zhu Wei

    J. Semicond.  2009, 30(1): 014006

    doi: 10.1088/1674-4926/30/1/014006

    Abstract PDF Get Citation

    An embedded wire-grid nanograting was designed and fabricated for using as a broadband polarizing beam splitter to reflect s-polarized light and transmit p-polarized light. A protected cladding layer of the same material as the grating’s was deposited on the ridge, whereas the wire-grid is deposited in the grating trenches, which makes it more firm during application. High polarization extinction ratios of above 40 and 20 dB for transmission and reflection, respectively, with a broad wavelength range for the whole optical communication bandwidth (850-1700 nm) and a wide angular tolerance (>±20°) are obtained by optimization of the designed structures, and the grating period is 200 nm.


  • Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

    Yang Yi, Gao Zhuo, Yang Liqiong, Huang Lingyi, Hu Weiwu

    J. Semicond.  2009, 30(1): 015001

    doi: 10.1088/1674-4926/30/1/015001

    Abstract PDF Get Citation

    An ultra-wideband (3.1–10.6 GHz) low-noise amplifier using the 0.18 μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev filers for input matching are analyzed and compared in detail. The measured power gain is 12.4–14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1–10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW (without output buffer for measurement) with a 1.8 V power supply and occupies 0.88 mm

  • A 0.18 μm CMOS fluorescent detector system for bio-sensing application

    Liu Nan, Chen Guoping, Hong Zhiliang

    J. Semicond.  2009, 30(1): 015002

    doi: 10.1088/1674-4926/30/1/015002

    Abstract PDF Get Citation

    A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 mm standard CMOS process. Some special techniques, such as a “contact imaging” detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

  • Design and measurement of a 53 GHz balanced Colpitts oscillator

    Zhao Yan, Wang Zhigong, Li Wei, Zhang Li

    J. Semicond.  2009, 30(1): 015003

    doi: 10.1088/1674-4926/30/1/015003

    Abstract PDF Get Citation

    A 53 GHz Colpitts oscillator implemented in a SiGe:C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer down-converted the oscillating frequency to an intermediate frequency (IF) below 26.5 GHz. By adjusting the local oscillating (LO) frequency and recording the changes of IF frequency, the oscillator's output frequency (RF) was determined. Additionally, using phase noise theory of mixers, the oscillator's phase noise was estimated as -58 dBc/Hz at 1 MHz offset and the output power was about -21 dBm. The chip is 270×480 μm2 in size.

  • A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS

    Gao Zhuo, Yang Yi, Zhong Shiqiang, Yang Xu, Huang Lingyi, Hu Weiwu

    J. Semicond.  2009, 30(1): 015004

    doi: 10.1088/1674-4926/30/1/015004

    Abstract PDF Get Citation

    This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186 μm2 and consumes 5.3 mW power.

  • A 3.1–4.8 GHz CMOS receiver for MB-OFDM UWB

    Yang Guang, Yao Wang, Yin Jiangwei, Zheng Renliang, Li Wei, Li Ning, Ren Junyan

    J. Semicond.  2009, 30(1): 015005

    doi: 10.1088/1674-4926/30/1/015005

    Abstract PDF Get Citation

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  • A fully integrated BPSK amplitude and spectrum tunable transmitter for IR-UWB system

    Xia Lingli, Huang Yumei, Hong Zhiliang

    J. Semicond.  2009, 30(1): 015006

    doi: 10.1088/1674-4926/30/1/015006

    Abstract PDF Get Citation

    A 3–5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13 μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2×1.4 mm2.

  • A low-power monolithic CMOS transceiver for 802.11b wireless LANs

    Li Weinan, Xia Lingli, Zheng Yongzheng, Huang Yumei, Hong Zhiliang

    J. Semicond.  2009, 30(1): 015007

    doi: 10.1088/1674-4926/30/1/015007

    Abstract PDF Get Citation

    A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (ΣΔ) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in receiving mode and 81 mW in transmitting mode under supply voltage of 1.8 V, respectively, including 30 mW consumed by frequency synthesizer. Total chip area with pads is 2.7 mm × 4.2 mm.

  • 5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

    Zhang Xuelian, Yan Jun, Shi Yin, Dai Fa Foster

    J. Semicond.  2009, 30(1): 015008

    doi: 10.1088/1674-4926/30/1/015008

    Abstract PDF Get Citation

    A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 µm SiGe BiCMOS technology and occupy 1.12 × 1.25 mm2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85  converges within ±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.

  • A novel low-voltage operational amplifier for low-power pipelined ADCs

    Fan Mingjun, Ren Junyan, Guo Yao, Li Ning, Ye Fan, Li Lian

    J. Semicond.  2009, 30(1): 015009

    doi: 10.1088/1674-4926/30/1/015009

    Abstract PDF Get Citation

    A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion –94.3 dB with Nyquist input signal frequency.

  • Design of a 16 gray scales 320×240 pixels OLED-on-silicon driving circuit

    Huang Ran, Wang Xiaohui, Wang Wenbo, Du Huan, Han Zhengsheng

    J. Semicond.  2009, 30(1): 015010

    doi: 10.1088/1674-4926/30/1/015010

    Abstract PDF Get Citation

    A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4×28.4 μm2 and the display area is 10.7×8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.

  • Modeling and analysis of power extraction circuits for passive UHF RFID applications

    Fan Bo, Dai Yujie, Zhang Xiaoxing, Lü Yingjie

    J. Semicond.  2009, 30(1): 015011

    doi: 10.1088/1674-4926/30/1/015011

    Abstract PDF Get Citation

    Modeling and analysis of far field power extraction circuits for passive UHF RF identification (RFID) applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.


  • Microtrenching effect of SiC ICP etching in SF6/O2 plasma

    Ding Ruixue, Yang Yintang, Han Ru

    J. Semicond.  2009, 30(1): 016001

    doi: 10.1088/1674-4926/30/1/016001

    Abstract PDF Get Citation

    Inductively coupled plasma (ICP) etching of single crystal 6H-silicon carbide (SiC) is investigated using oxygen (O-added sulfur hexafluoride (SF plasmas. The relations between the microtrenching effect and ICP coil power, the composition of the etch gases and different bias voltages are discussed. Experimental results show that the microtrench is caused by the formation of a SiFO layer, which has a greater tendency to charge than SiC, after the addition of O. The microtrenching effect tends to increase as the ICP coil power and bias voltage increase. In addition, the angular distribution of the incident ions and radicals also affects the shape of the microtrench.


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