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Volume 33, Issue 4, Apr 2012


  • Influence of absorber doping in a-SiC:H/a-Si:H/a-SiGe:H solar cells

    Muhammad Nawaz, Ashfaq Ahmad

    J. Semicond.  2012, 33(4): 042001

    doi: 10.1088/1674-4926/33/4/042001

    Abstract PDF Get Citation

    This work deals with the design evaluation and influence of absorber doping for a-Si:H/a-SiC:H/a-SiGe:H based thin-film solar cells using a two-dimensional computer aided design (TCAD) tool. Various physical parameters of the layered structure, such as doping and thickness of the absorber layer, have been studied. For reliable device simulation with realistic predictability, the device performance is evaluated by implementing necessary models (e.g., surface recombinations, thermionic field emission tunneling model for carrier transport at the heterojunction, Schokley-Read Hall recombination model, Auger recombination model, bandgap narrowing effects, doping and temperature dependent mobility model and using Fermi-Dirac statistics). A single absorber with a graded design gives an efficiency of 10.1% for 800 nm thick multiband absorption. Similarly, a tandem design shows an efficiency of 10.4% with a total absorber of thickness of 800 nm at a bandgap of 1.75 eV and 1.0 eV for the top a-Si and bottom a-SiGe component cells. A moderate n-doping in the absorber helps to improve the efficiency while p doping in the absorber degrades efficiency due to a decrease in the VOC (and fill factor) of the device.

  • Nanoporous characteristics of sol-gel-derived ZnO thin film

    Anees A. Ansari, M. A. M. Khan, M. Alhoshan, S. A. Alrokayan, M. S. Alsalhi

    J. Semicond.  2012, 33(4): 042002

    doi: 10.1088/1674-4926/33/4/042002

    Abstract PDF Get Citation

    Sol-gel-derived nanoporous ZnO film has been successfully deposited on glass substrate at 200℃ and subsequently annealed at different temperatures of 300, 400 and 600℃. Atomic force micrographs demonstrated that the film was crack-free, and that granular nanoparticles were homogenously distributed on the film surface. The average grain size of the nanoparticles and RMS roughness of the scanned surface area was 10 nm and 13.6 nm, respectively, which is due to the high porosity of the film. Photoluminescence (PL) spectra of the nanoporous ZnO film at room temperature show a diffused band, which might be due to an increased amount of oxygen vacancies on the lattice surface. The observed results of the nanoporous ZnO film indicates a promising application in the development of electrochemical biosensors due to the porosity of film enhancing the higher loading of bio-macromolecules (enzyme and proteins).


  • Structural and optical properties of Zn3N2 films prepared by magnetron sputtering in NH3-Ar mixture gases

    Wu Jiangyan, Yan Jinliang, Yue Wei, Li Ting

    J. Semicond.  2012, 33(4): 043001

    doi: 10.1088/1674-4926/33/4/043001

    Abstract PDF Get Citation

    Zinc nitride films were prepared by RF magnetron sputtering a metallic zinc target in NH3-Ar mixture gases on glass substrate at room temperature. The effects of NH3 ratio on the structural and optical properties of the films were examined. X-ray diffraction (XRD) analysis indicates that the films are polycrystalline and have a preferred orientation of (321). An indirect optical band gap increased from 2.33 to 2.70 eV when the NH3 ratio varied from 5% to 25%. The photoluminescence (PL) spectrum shows two emission peaks; the peak located at 437 nm is attributed to the incorporation of oxygen, and the other at 459 nm corresponds to the intrinsic emission.

  • Nanoindentation study of a Cu/Ta/SiO2/Si multilayer system

    Zhang Xin, Lu Qian, Wu Zijing, Wu Xiaojing, Shen Weidian, Jiang Bin

    J. Semicond.  2012, 33(4): 043002

    doi: 10.1088/1674-4926/33/4/043002

    Abstract PDF Get Citation

    Tantalum and copper layers were deposited on a thermally oxidized Si substrate in a magnetron sputtering process. Nanoindentation was adopted to investigate the hardness and elastic modulus of the Cu/Ta/SiO2/Si multilayer system. The hardness shows an apparent dependence on the film thickness, and decreases with the increase of film thickness, whereas the elastic modulus does not. To reveal the structural change, a trench through the center of a residual indent was cut by a focused ion beam, and then examined using an ion-microscope. TEM analysis showed that delamination occurs at the interface between the Ta and the SiO2 layer of the residual indent, suggesting that the destruction under a relatively large load is due to weak bonding.

  • Application of ZnO nanopillars and nanoflowers to field-emission luminescent tubes

    Ye Yun, Guo Tailiang, Jiang Yadong

    J. Semicond.  2012, 33(4): 043003

    doi: 10.1088/1674-4926/33/4/043003

    Abstract PDF Get Citation

    Zinc oxide (ZnO) nanopillars on a ZnO seed layer and ZnO nanoflowers were synthesized by electrochemical deposition on linear wires. The morphologies and crystal orientation of the ZnO nanostructures were investigated by a scanning electron microscopy and an X-ray diffraction pattern, respectively. Detailed study on the field-emission properties of ZnO nanostructures indicates that nanopillars with a high aspect ratio show good performance with a low turn-on field of 0.16 V/μm and a high field enhancement factor of 2.86CcCc104. A luminescent tube with ZnO nanopillars on a linear wire cathode and a transparent anode could reach a luminance of about 1.5CcCc104 cd/m2 under an applied voltage of 4 kV.

  • Novel method of separating macroporous arrays from p-type silicon substrate

    Peng Bobo, Wang Fei, Liu Tao, Yang Zhenya, Wang Lianwei, Ricky K. Y. Fu, Paul K. Chu

    J. Semicond.  2012, 33(4): 043004

    doi: 10.1088/1674-4926/33/4/043004

    Abstract PDF Get Citation

    This paper presents a novel method to fabricate separated macroporous silicon using a single step of photo-assisted electrochemical etching. The method is applied to fabricate silicon microchannel plates in 100 mm p-type silicon wafers, which can be used as electron multipliers and three-dimensional Li-ion microbatteries. Increasing the backside illumination intensity and decreasing the bias simultaneously can generate additional holes during the electrochemical etching which will create lateral etching at the pore tips. In this way the silicon microchannel can be separated from the substrate when the desired depth is reached, then it can be cut into the desired shape by using a laser cutting machine. Also, the mechanism of lateral etching is proposed.


  • An analytical model for the drain-source breakdown voltage of RF LDMOS power transistors with a Faraday shield

    Zhang Wenmin, Zhang Wei, Fu Jun, Wang Yudong

    J. Semicond.  2012, 33(4): 044001

    doi: 10.1088/1674-4926/33/4/044001

    Abstract PDF Get Citation

    An analytical model for the drain-source breakdown voltage of an RF LDMOS power transistor with a Faraday shield is derived on the basis of the solution of the 2D Poisson equation in a p-type epitaxial layer, as well as an n-type drift region by means of parabolic approximation of electrostatic potential. The model captures the influence of the p-type epitaxial layer doping concentration on the breakdown voltage, compared with the previously reported model, as well as the effect of the other device parameters. The analytical model is validated by comparing with a numerical device simulation and the measured characteristics of LDMOS transistors. Based on the model, optimization of LDMOS device parameters to achieve proper trade-off between the breakdown voltage and other characteristic parameters such as on-resistance and feedback capacitance is analyzed.

  • A novel structure for improving the SEGR of a VDMOS

    Tang Zhaohuan, Hu Gangyi, Chen Guangbing, Tan Kaizhou, Liu Yong, Luo Jun, Xu Xueliang

    J. Semicond.  2012, 33(4): 044002

    doi: 10.1088/1674-4926/33/4/044002

    Abstract PDF Get Citation

    The mechanism of single-event gate-rupture in an N-channel VDMOS in a space radiation environment was analyzed. Based on the mechanism, a novel structure of VDMOS for improving single-event gate-rupture is proposed, and the structure is simulated and it is demonstrated that it can improve a VDMOS SEGR threshold voltage by 120%. With this structure, the specific on-resistance value of a VDMOS is reduced by 15.5% as the breakdown voltage almost maintains the same value. As only one mask added, which is local oxidation of silicon instead of an active processing area, the new structure VDMOS it is easily fabricated. The novel structure can be widely used in high-voltage VDMOS in a space radiation environment.

  • Determination of channel temperature for AlGaN/GaN HEMTs by high spectral resolution micro-Raman spectroscopy

    Zhang Guangchen, Feng Shiwei, Li Jingwan, Zhao Yan, Guo Chunsheng

    J. Semicond.  2012, 33(4): 044003

    doi: 10.1088/1674-4926/33/4/044003

    Abstract PDF Get Citation

    Channel temperature determinations of AlGaN/GaN high electron mobility transistors (HEMTs) by high spectral resolution micro-Raman spectroscopy are proposed. The temperature dependence of the E2 phonon frequency of GaN material is calibrated by using a JYT-64000 micro-Raman system. By using the Lorentz fitting method, the measurement uncertainty for the Raman phonon frequency of ±0.035 cm-1 is achieved, corresponding to a temperature accuracy of ±3.2℃ for GaN material, which is the highest temperature resolution in the published works. The thermal resistance of the tested AlGaN/GaN HEMT sample is 22.8℃/W, which is in reasonably good agreement with a three dimensional heat conduction simulation. The difference among the channel temperatures obtained by micro-Raman spectroscopy, the pulsed electrical method and the infrared image method are also investigated quantificationally.

  • A 700 V BCD technology platform for high voltage applications

    Qiao Ming, Jiang Lingli, Zhang Bo, Li Zhaoji

    J. Semicond.  2012, 33(4): 044004

    doi: 10.1088/1674-4926/33/4/044004

    Abstract PDF Get Citation

    A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mΩ·cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.

  • Theoretical analysis and concept demonstration of a novel MOEMS accelerometer based on Raman-Nath diffraction

    Zhang Zuwei, Wen Zhiyu, Hu Jing

    J. Semicond.  2012, 33(4): 044005

    doi: 10.1088/1674-4926/33/4/044005

    Abstract PDF Get Citation

    The design and simulation of a novel microoptoelectromechanical system (MOEMS) accelerometer based on Raman-Nath diffraction are presented. The device is planned to be fabricated by microelectromechanical system technology and has a different sensing principle than the other reported MOEMS accelerometers. The fundamental theories and principles of the device are discussed in detail, a 3D finite element simulation of the flexural plate wave delay line oscillator is provided, and the operation frequency around 40 MHz is calculated. Finally, a lecture experiment is performed to demonstrate the feasibility of the device. This novel accelerometer is proposed to have the advantages of high sensitivity and anti-radiation, and has great potential for various applications.

  • High-temperature (T=80℃) operation of a 2 μm InGaSb-AlGaAsSb quantum well laser

    Zhang Yu, Wang Yongbin, Xu Yingqiang, Xu Yun, Niu Zhichuan, Song Guofeng

    J. Semicond.  2012, 33(4): 044006

    doi: 10.1088/1674-4926/33/4/044006

    Abstract PDF Get Citation

    An InGaSb/AlGaAsSb compressively strained quantum well laser emitting at 2 μm has been fabricated. An output power of 82.2 mW was obtained in continuous wave (CW) mode at room temperature. The laser can operate at high temperature (T=80℃), with a maximum output power of 63.7 mW in CW mode.

  • ESD protection design for the gate oxide of an RF-LDMOS

    Jiang Yibo, Du Huan, Zeng Chuanbin, Han Zhengsheng

    J. Semicond.  2012, 33(4): 044007

    doi: 10.1088/1674-4926/33/4/044007

    Abstract PDF Get Citation

    This paper presents the investigation of integrated electro-static discharge (ESD) protection design for the gate oxide of an RF-LDMOS (radio frequency lateral double diffusion MOS). Through a comprehensive discussion of experimental and simulated results, a cascoded NMOS is presented as appropriate integrated gate oxide ESD protection with a high holding voltage and a flexible ESD design window.

  • Influence of drain and substrate bias on the TID effect for deep submicron technology devices

    Huang Huixiang, Liu Zhangli, Hu Zhiyuan, Zhang Zhengxuan, Chen Ming, Bi Dawei, Zou Shichang

    J. Semicond.  2012, 33(4): 044008

    doi: 10.1088/1674-4926/33/4/044008

    Abstract PDF Get Citation

    This paper presents a study of the total ionization effects of a 0.18 μm technology. The electrical parameters of NMOSFETs were monitored before and after irradiation with 60Co at several dose levels under different drain and substrate biases. Key parameters such as off-state leakage current and threshold voltage shift were studied to reflect the ionizing radiation tolerance, and explained using a parasitic transistors model. 3D device simulation was conducted to provide a better understanding of the dependence of device characteristics on drain and substrate biases.

  • Dependence of transient performance on potential distribution in a static induction thyristor channel

    Liu Chunjuan, Liu Su, Bai Yajie

    J. Semicond.  2012, 33(4): 044009

    doi: 10.1088/1674-4926/33/4/044009

    Abstract PDF Get Citation

    The impact of potential barrier distribution on the transient performance of a static induction thyristor (SITH) in a channel determined by geometrical parameters and applied bias voltage is studied theoretically and experimentally. The analytical expressions of potential barrier height and the I-V characteristics of the SITH are also derived. The main factors that influence the transient performance of the SITH between the blocking and conducting states, as well as the mechanism underlying the transient process, is thoroughly investigated. This is useful in designing, fabricating, optimizing and applying SITHs properly.


  • A SiGe BiCMOS multi-band tuner for mobile TV applications

    Hu Xueqing, Gong Zheng, Zhao Jinxin, Wang Lei, Yu Peng, Shi Yin

    J. Semicond.  2012, 33(4): 045001

    doi: 10.1088/1674-4926/33/4/045001

    Abstract PDF Get Citation

    This paper presents the circuit design and measured performance of a multi-band tuner for mobile TV applications. The tuner RFIC is composed of a wideband front-end, an analog baseband, a full integrated fractional-N synthesizer and an I2C digital interface. To meet the stringent adjacent channel rejection (ACR) requirements of mobile TV standards while keeping low power consumption and low cost, direct conversion architecture with a local AGC scheme is adopted in this design. Eighth-order elliptic active-RC filters with large stop band attenuation and a sharp transition band are chosen as the channel select filter to further improve the ACR preference. The chip is fabricated in a 0.35-μm SiGe BiCMOS technology and occupies a silicon area of 5.5 mm2. It draws 50 mA current from a 3.0 V power supply. In CMMB application, it achieves a sensitivity of-97 dBm with 1/2 coding QPSK signal input and over 40 dB ACR.

  • Analysis and implementation of derivative superposition for a power amplifier driver

    Li Yilei, Han Kefeng, Yan Na, Tan Xi, Min Hao

    J. Semicond.  2012, 33(4): 045002

    doi: 10.1088/1674-4926/33/4/045002

    Abstract PDF Get Citation

    A new expression is proposed to analyze the linearization effectiveness of derivative superposition (DS) with large and small signal inputs, and different optimization methods of DS are found for different input magnitudes. A power amplifier driver (PAD) with large-signal optimized DS was implemented in 0.13 μm technology within a reconfigurable RF transmitter. The PAD is compatible with the GSM band at 900 MHz and the WCDMA band at 1.95 GHz, and it has a gain range of 44 dB with a step of 2 dB. Measurement results show that the overall OIP3 of the transmitter is better than 19 dBm, and the output referred 1-dB compression point is better than 7.5 dBm.

  • A low-power high-swing voltage-mode transmitter

    Chen Shuai, Li Hao, Shi Xiaobing, Yang Liqiong, Yang Zongren, Zhong Shiqiang, Huang Lingyi

    J. Semicond.  2012, 33(4): 045003

    doi: 10.1088/1674-4926/33/4/045003

    Abstract PDF Get Citation

    A low-power voltage-mode-logic (VML) transmitter fabricated in TSMC 28 nm CMOS technology is presented. The VML driver outputs a high-swing signal and consumes less power than a current-mode-logic (CML) driver. To further reduce power, the driver is divided into two voltage domains by level shifters. Moreover, the proposed driver topology can achieve mutually decoupled impedance self-calibration and equalization control. The measurement result shows that the transmitter merely dissipates 23 mW/channel while exhibiting an 880 mV differential eye height at 4.488 Gb/s.

  • Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

    Lou Wenfeng, Feng Peng, Wang Haiyong, Wu Nanjian

    J. Semicond.  2012, 33(4): 045004

    doi: 10.1088/1674-4926/33/4/045004

    Abstract PDF Get Citation

    A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 μs over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about-115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than-52 dBc. The whole frequency synthesizer consumes only 4.35 mA@1.8 V.

  • Design of an LED driver based on hysteretic-current-control mode in a 0.6 μm BCD process

    Liu Lianxi, Zhu Zhangming, Yang Yintang

    J. Semicond.  2012, 33(4): 045005

    doi: 10.1088/1674-4926/33/4/045005

    Abstract PDF Get Citation

    Based on the 0.6 μm BCDMOS process a hysteretic-current-control mode white light LED driver with high accuracy and efficiency is presented. The driver can work with a 6-40 V power supply, the maximum output current is up to 1.0 A, the maximum switching frequency is up to 1 MHz, the output current error is less than ±5%, and the efficiency is greater than 80%. The circuit details of the high-side-current sensor and high-speed comparator, which greatly affect the accuracy of the whole driver, are emphasized. Then, the simulation and test results of this work are presented.

  • On-chip frequency compensation with a dual signal path operational transconductance amplifier for a voltage mode control DC/DC converter

    Ye Qiang, Liu Jie, Yuan Bing, Lai Xinquan, Liu Ning

    J. Semicond.  2012, 33(4): 045006

    doi: 10.1088/1674-4926/33/4/045006

    Abstract PDF Get Citation

    A novel on-chip frequency compensation circuit for a voltage-mode control DC/DC converter is presented. By employing an RC network in the two signal paths of an operational transconductance amplifier (OTA), the proposed circuit generates two zeros to realize high closed-loop stability. Meanwhile, full on-chip integration is also achieved due to its simple structure. Hence, the number of off-chip components and the board space is greatly reduced. The structure of the dual signal path OTA is also optimized to help get a better transition response. Implemented in a 0.5 μ m CMOS process, the voltage mode control DC/DC converter with the proposed frequency compensation circuit exhibits good stability. The test results show that both load and line regulations are less than 0.3%, and the output voltage can be recovered within 15 μ s for a 400 mA load step. Moreover, the compensation components area is less than 2% of the die’s area and the board space is also reduced by 11%. The efficiency of the whole chip can be up to 95%.

  • A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

    Yin Xizhen, Xiao Shimao, Jin Yuhua, Wu Qiwu, Ma Chengyan, Ye Tianchun

    J. Semicond.  2012, 33(4): 045007

    doi: 10.1088/1674-4926/33/4/045007

    Abstract PDF Get Citation

    A constant loop bandwidth fractional-N frequency synthesizer for portable civilian global navigation satellite system (GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete working regions, the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an in-band phase noise lower than-93 dBc at a 10 kHz offset and a spur less than-70 dBc; the bandwidth varies by ±3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area (without the LO tested buffer) is 0.5 mm2.

  • An optimized analog to digital converter for WLAN analog front end

    Ye Mao, Zhou Yumei, Wu Bin, Jiang Jianhua

    J. Semicond.  2012, 33(4): 045008

    doi: 10.1088/1674-4926/33/4/045008

    Abstract PDF Get Citation

    A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multi-bit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 μm 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz.

  • A new algorithm of inverse lithography technology for mask complexity reduction

    Li Yanghuan, Shi Zheng, Geng Zhen, Yang Yiwei, Yan Xiaolang

    J. Semicond.  2012, 33(4): 045009

    doi: 10.1088/1674-4926/33/4/045009

    Abstract PDF Get Citation

    A new complexity penalty term called the global wavelet penalty is introduced, which evaluates the high-frequency components of masks more profoundly by applying four distinctive Haar wavelet transforms and choosing the optimal direction on which the highest frequency components of the mask will be removed. Then, a new gradient-based inverse lithography technology (ILT) algorithm is proposed, with the computation of the global wavelet penalty as the emphasis of its first phase for mask complexity reduction. Experiments with three typical 65 nm flash ROM patterns under existing 90 nm lithographic conditions show that compared with the gradient-based algorithm, which relies on the so-called local wavelet penalty, the total vertices of the three results created by the proposed algorithm can be reduced by 12.89%, 12.63% and 12.64%, respectively, while the accuracy of the lithography results remains the same.


  • An advanced alkaline slurry for barrier chemical mechanical planarization on patterned wafers

    Wang Chenwei, Liu Yuling, Niu Xinhuan, Tian Jianying, Gao Baohong, Zhang Xiaoqiang

    J. Semicond.  2012, 33(4): 046001

    doi: 10.1088/1674-4926/33/4/046001

    Abstract PDF Get Citation

    We have developed an alkaline barrier slurry (named FA/O slurry) for barrier removal and evaluated its chemical mechanical planarization (CMP) performance through comparison with a commercially developed barrier slurry. The FA/O slurry consists of colloidal silica, which is a complexing and an oxidizing agent, and does not have any inhibitors. It was found that the surface roughness of copper blanket wafers polished by the FA/O slurry was lower than the commercial barrier slurry, demonstrating that it leads to a better surface quality. In addition, the dishing and electrical tests also showed that the patterned wafers have a lower dishing value and sheet resistance as compared to the commercial barrier slurry. By comparison, the FA/O slurry demonstrates good planarization performance and can be used for barrier CMP.

  • A theoretical model of the femtosecond laser ablation of semiconductors considering inverse bremsstrahlung absorption

    Lin Xiaohui, Zhang Chibin, Ren Weisong, Jiang Shuyun, Ouyang Quanhui

    J. Semicond.  2012, 33(4): 046002

    doi: 10.1088/1674-4926/33/4/046002

    Abstract PDF Get Citation

    The mechanism of the femtosecond laser ablation of semiconductors is investigated. The collision process of free electrons in a conduction band is depicted by the test particle method, and a theoretical model of nonequilibrium electron transport on the femtosecond timescale is proposed based on the Fokker-Planck equation. This model considers the impact of inverse bremsstrahlung on the laser absorption coefficient, and gives the expressions of electron drift and diffusion coefficients in the presence of screened Coulomb potential. Numerical simulations are conducted to obtain the nonequilibrium distribution function of the electrons. The femtosecond laser ablation thresholds are then calculated accordingly, and the results are in good agreement with the experimental results. This is followed by a discussion on the impact of laser parameters on the ablation of semiconductors.


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