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Volume 33, Issue 6, Jun 2012

    SEMICONDUCTOR PHYSICS

  • Stacking fault energy in some single crystals

    Aditya M.Vora

    J. Semicond.  2012, 33(6): 062001

    doi: 10.1088/1674-4926/33/6/062001

    Abstract PDF Get Citation

    The stacking fault energy of single crystals has been reported using the peak shift method. Presently studied all single crystals are grown by using a direct vapor transport (DVT) technique in the laboratory. The structural characterizations of these crystals are made by XRD. Considerable variations are shown in deformation (α) and growth (β) probabilities in single crystals due to off-stoichiometry, which possesses the stacking fault in the single crystal.

  • SEMICONDUCTOR MATERIALS

  • Simultaneous quality improvement of the roughness and refractive index of SiC thin films

    Gh. Sareminia, H. Simchi, A. Ostovari, L. Lavasanpour

    J. Semicond.  2012, 33(6): 063001

    doi: 10.1088/1674-4926/33/6/063001

    Abstract PDF Get Citation

    We deposited silicon carbide thin layers on cleaned Si (100) substrates using the plasma enhanced chemical vapor deposition method, and show that the RFTIR spectrum is periodic in the near and medium infrared ranges. It is shown that both the deposition rate and the uniformity of the thin films are decreased by increasing the substrate temperature, and that the refractive index is increased by increasing the substrate temperature. This shows that there is a trade-off between the quality improvement of the uniformity and refractive index.

  • Tungsten oxide nanostructures: controllable growth and field emission

    Yue Shuanglin, Xu Tingting, Li Wei, Yan Ji, Yi He

    J. Semicond.  2012, 33(6): 063002

    doi: 10.1088/1674-4926/33/6/063002

    Abstract PDF Get Citation

    Non-fully oxidized tungsten oxide (WO3-x) nanostructures with controllable morphology were fabricated by adjusting the gas pressure in chemical vapor deposition. The comparative field emission (FE) measurements showed that the obtained W18O49 nanowires have excellent FE property. The turn-on field was 7.1 V/μ m for 10 μA/cm2 and the observed highest current density was 4.05 mA/cm2 at a field of 17.2 V/μm. Good electron emission reproducibility was also observed during thermal evaporation and desorption testing.

  • SEMICONDUCTOR DEVICES

  • The design of electroabsorption modulators with negative chirp and very low insertion loss

    Kambiz Abedi

    J. Semicond.  2012, 33(6): 064001

    doi: 10.1088/1674-4926/33/6/064001

    Abstract PDF Get Citation

    Electroabsorption modulators (EAMs) with negative chirp and very low insertion loss are numerically designed with asymmetric intra-step-barrier coupled double strained quantum wells (AICD-SQWs) based on InGaAlAs material. For this purpose, the electroabsorption coefficient is calculated over a range of wells layer strain from compressive (CS) to tensile (TS). The chirp parameter and insertion loss for TE input light polarization are evaluated from the calculated electroabsorption spectra, and their Kramers-Krönig transformed refractive index changes. The results of the numerical simulation show that the best range of left and right wells strain for EAMs based on AICD-SQWs with negative chirp and very low insertion loss are from 0.032% to 0.05% (TS) and -0.52% to -0.50% (CS), respectively.

  • A 150% enhancement of PMOSFET mobility using hybrid orientation

    Tang Zhaohuan, Tan Kaizhou, Cui Wei, Zhang Jing, Zhong Yi, Xu Shiliu, Hao Yue, Zhang Heming, Hu Huiyong, Zhang Zhengfan, Hu Gangyi

    J. Semicond.  2012, 33(6): 064002

    doi: 10.1088/1674-4926/33/6/064002

    Abstract PDF Get Citation

    A high-performance PMOSFET based on silicon material of hybrid orientation is obtained. Hybrid orientation wafers, integrated by (100) and (110) crystal orientation, are fabricated using silicon-silicon bonding, chemical mechanical polishing, etching silicon and non-selective expitaxy. A PMOSFET with W/L = 50 μm/8 μm is also processed, and the measured results show that the drain-source current and peak mobility of the PMOSFET are enhanced by up to 50.7% and 150% at Vgs = -15 V and Vds = -0.5 V, respectively. The mobility values are higher than that reported in the literature.

  • Hot-carrier reliability in OPTVLD-LDMOS

    Cheng Junji, Chen Xingbi

    J. Semicond.  2012, 33(6): 064003

    doi: 10.1088/1674-4926/33/6/064003

    Abstract PDF Get Citation

    An improved structure that eliminates hot-carrier effects (HCE) in optimum variation lateral doping (OPTVLD) LDMOS is proposed. A formula is proposed showing that the surface electric field intensity of the conventional structure is strong enough to make a hot-carrier injected into oxide. However, the proposed structure effectively reduces the maximum surface electric field from 268 to 100 kV/cm and can be realized without changing any process, and thereby reduces HCE significantly.

  • Enhancement-mode InAlN/GaN MISHEMT with low gate leakage current

    Gu Guodong, Cai Yong, Feng Zhihong, Liu Bo, Zeng Chunhong, Yu Guohao, Dong Zhihua, Zhang Baoshun

    J. Semicond.  2012, 33(6): 064004

    doi: 10.1088/1674-4926/33/6/064004

    Abstract PDF Get Citation

    We report an enhancement-mode InAlN/GaN MISHEMT with a low gate leakage current by a thermal oxidation technique under gate. The off-state source-drain current density is as low as ~10-7 A/mm at VGS = 0 V and VDS = 5 V. The threshold voltage is measured to be +0.8 V by linear extrapolation from the transfer characteristics. The E-mode device exhibits a peak transconductance of 179 mS/mm at a gate bias of 3.4 V. A low reverse gate leakage current density of 4.9 × 10-7 A/mm is measured at VGS = -15 V.

  • Analysis of the ohmic contacts of Ti/Al/Ni/Au to AlGaN/GaN HEMTs by the multi-step annealing process

    Yan Wei, Zhang Renping, Du Yandong, Han Weihua, Yang Fuhua

    J. Semicond.  2012, 33(6): 064005

    doi: 10.1088/1674-4926/33/6/064005

    Abstract PDF Get Citation

    The multi-step rapid thermal annealing process of Ti/Al/Ni/Au can make good ohmic contacts with both low contact resistance and smooth surface morphology for AlGaN/GaN HEMTs. In this work, the mechanism of the multi-step annealing process is analyzed in detail by specific experimental methods. The experimental results show that annealing temperature and time are very important parameters when optimizing the Ti/Al layer for lower resistance and the Ni/Au layer for smooth surface morphology. It is very important for good ohmic contacts to balance the rate of various reactions by adjusting the annealing temperature and time. We obtained a minimum specific contact resistance of 3.22 × 10-7 Ω·cm2 on the un-doped AlGaN/GaN structure with an optimized multi-step annealing process.

  • Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

    Ding Lili, Guo Hongxia, Chen Wei, Fan Ruyu

    J. Semicond.  2012, 33(6): 064006

    doi: 10.1088/1674-4926/33/6/064006

    Abstract PDF Get Citation

    Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation. There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies. To reanalyze this problem and make it beyond argument, every possible variable is considered using theoretical analysis, not just the change of electric field or oxide thickness independently. Among all possible inter-device leakage paths, parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region. Since N-well regions are commonly connected to the same power supply, these kinds of structures will not be a problem in a real CMOS integrated circuit. Generally speaking, conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

  • Characterization of the nanosized porous structure of black Si solar cells fabricated via a screen printing process

    Tang Yehua, Zhou Chunlan, Wang Wenjing, Zhou Su, Zhao Yan, Zhao Lei, Li Hailing, Yan Baojun, Chen Jingwei, Fei Jianming, Cao Hongbin

    J. Semicond.  2012, 33(6): 064007

    doi: 10.1088/1674-4926/33/6/064007

    Abstract PDF Get Citation

    A silicon (Si) surface with a nanosized porous structure was formed via simple wet chemical etching catalyzed by gold (Au) nanoparticles on p-type Cz-Si (100). The average reflectivity from 300 to 1200 nm was less than 1.5%. Black Si solar cells were then fabricated using a conventional production process. The results reflected the output characteristics of the cells fabricated using different etching depths and emitter dopant profiles. Heavier dopants and shallower etching depths should be adopted to optimize the black Si solar cell output characteristics. The efficiency at the optimized etching time and dopant profile was 12.17%. However, surface passivation and electrode contact due to the nanosized porous surface structure are still obstacles to obtaining high conversion efficiency for the black Si solar cells.

  • Far-infrared electroluminescence characteristics of an InGaP/InGaAs/Ge triple-junction solar cell under forward DC bias

    Xiao Wenbo, He Xingdao, Gao Yiqing, Zhang Zhimin, Liu Jiangtao

    J. Semicond.  2012, 33(6): 064008

    doi: 10.1088/1674-4926/33/6/064008

    Abstract PDF Get Citation

    The far-infrared electroluminescence characteristics of an InGaP/InGaAs/Ge solar cell are investigated under forward DC bias at room temperature in dark conditions. An electroluminescence viewgraph shows the clear device structures, and the electroluminescence intensity is shown to increases exponentially with bias voltage and linearly with bias current. The results can be interpreted using an equivalent circuit of a single ideal diode model for triple-junction solar cells. The good fit between the measured and calculated data proves the above conclusions. This work is of guiding significance for current solar cell testing and research.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

    Zhou Kaimin, Wang Ziqiang, Zhang Chun, Wang Zhihua

    J. Semicond.  2012, 33(6): 065001

    doi: 10.1088/1674-4926/33/6/065001

    Abstract PDF Get Citation

    A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch, a symmetrical readout circuit is realized. The linear input range is increased, and the systematic offsets of two input op-amps are cancelled. The common-mode noise and even-order distortion are also rejected. A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps, and a Verilog-A-based varactor is used to model the real variable sensing capacitor. Simulation results show that the output voltage of this proposed readout circuit responds correctly, while the under-test capacitance changes with a frequency of 1 kHz. A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF, linearity error below 1% and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.

  • A novel circuit architecture for fourth subharmonic mixers

    Yao Changfei, Xu Conghai, Zhou Ming, Luo Yunsheng

    J. Semicond.  2012, 33(6): 065002

    doi: 10.1088/1674-4926/33/6/065002

    Abstract PDF Get Citation

    A circuit topology for high-order subharmonic (SH) mixers is described. By phase cancellation of idle frequency components, the SH mixer circuit can eliminate the complicated design procedure of idle frequency circuits. Similarly, the SH mixer circuit can achieve a high port isolation by phase cancellation of the leakage LO, RF and idle frequency signals. Based on the high-order SH mixer architecture, a new Ka-band fourth SH mixer is analyzed and designed, it shows the lowest measured conversion loss of 8.3 dB at 38.4 GHz and the loss is lower than 10.3 dB in 34-39 GHz. Measured LO-IF, RF-LO, RF-IF port isolation are better than 30.7 dB, 22.9dB and 46.5 dB, respectively.

  • A 6th order wideband active-RC LPF for LTE application

    Wei Baoyue, Li Hongkun, Wang Yunfeng, Zhang Haiying

    J. Semicond.  2012, 33(6): 065003

    doi: 10.1088/1674-4926/33/6/065003

    Abstract PDF Get Citation

    A low power, highly linear active-RC filter is presented. This filter is synthesized from a low pass 6 order Chebyshev RLC ladder, and exhibits a reconfigurable bandwidth (10 MHz, 50 MHz). In order to meet the high cutoff frequency (50 MHz) and strict adjacent channel rejection requirements, a novel operational amplifier based on a new compensation technique is used, which optimizes high frequency filter performance and minimizes current consumption. This filter is fabricated in a 0.18 μm CMOS process, the measurement results indicate that the filter provides 10 MHz and 50 MHz selectable bandwidth, and excellent adjacent channel rejection: -15.3 dB at 12.5 MHz with 10 MHz cutoff frequency, -8.3 dB at 60 MHz with 50 MHz cutoff frequency, three times out-band rejection more than 60 dB while the in-band ripple is less than 1 dB.

  • Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    Nie Zedong, Zhang Fengjuan, Li Jie, Wang Lei

    J. Semicond.  2012, 33(6): 065004

    doi: 10.1088/1674-4926/33/6/065004

    Abstract PDF Get Citation

    A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW @ 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing.

  • Adaptive IF selection and IQ mismatch compensation in a low-IF GSM receiver

    Zhang Cheng, Wang Lifang, Tan Xi, Min Hao

    J. Semicond.  2012, 33(6): 065005

    doi: 10.1088/1674-4926/33/6/065005

    Abstract PDF Get Citation

    This paper presents an algorithm that can adaptively select the intermediate frequency (IF) and compensate the IQ mismatch according to the power ratio of the adjacent channel interference to the desired signal in a low-IF GSM receiver. The IF can be adaptively selected between 100 and 130 kHz. Test result shows an improvement of phase error from 6.78° to 3.23°. Also a least mean squares (LMS) based IQ mismatch compensation algorithm is applied to improve image rejection ratio (IRR) for the desired signal along with strong adjacent channel interference. The IRR is improved from 29.1 to 44.3 dB in measurement. The design is verified in a low-IF GSM receiver fabricated in SMIC 0.13 μm RF CMOS process with a working voltage of 1.2 V.

  • High voltage generator circuit with low power and high efficiency applied in EEPROM

    Liu Yan, Zhang Shilin, Zhao Yiqiang

    J. Semicond.  2012, 33(6): 065006

    doi: 10.1088/1674-4926/33/6/065006

    Abstract PDF Get Citation

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (Vth) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.

  • A fast combination calibration of foreground and background for pipelined ADCs

    Sun Kexu, He Lenian

    J. Semicond.  2012, 33(6): 065007

    doi: 10.1088/1674-4926/33/6/065007

    Abstract PDF Get Citation

    This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters (MDACs). The considered calibration technique takes the advantages of both foreground and background calibration schemes. In this combination calibration algorithm, a novel parallel background calibration with signal-shifted correlation is proposed, and its calibration cycle is very short. The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC. The high convergence speed of this background calibration is achieved by three means. First, a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code. Second, before correlating the signal, it is shifted according to the input signal so that the correlation error converges quickly. Finally, the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants. Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2 × 221 conversions.

  • A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

    Bai Na, Lü Baitao

    J. Semicond.  2012, 33(6): 065008

    doi: 10.1088/1674-4926/33/6/065008

    Abstract PDF Get Citation

    A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage (200 mV) applications. Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes. To minimize leakage, a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty. Combined with buffering circuit and reconfigurable operation, the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region. Compared to the referenced subthreshold SRAM bitcell, the proposed bitcell shows: (1) a better critical state noise margin, and (2) smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13 μW power consumption at 138 kHz frequency.

  • An AES chip with DPA resistance using hardware-based random order execution

    Yu Bo, Li Xiangyu, Chen Cong, Sun Yihe, Wu Liji, Zhang Xiangmin

    J. Semicond.  2012, 33(6): 065009

    doi: 10.1088/1674-4926/33/6/065009

    Abstract PDF Get Citation

    This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm2. A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance.

  • Analysis and modeling of on-chip transformers under two ground conditions

    Wei Jiaju, Wang Zhigong, Li Zhiqun, Tang Lu

    J. Semicond.  2012, 33(6): 065010

    doi: 10.1088/1674-4926/33/6/065010

    Abstract PDF Get Citation

    Two fabricated on-chip transformers under different ground conditions (i.e., CG and IG types) have been measured to compare their different characteristics. With the aid of the electromagnetic (EM) solver, we have analyzed the differences from the electric and magnetic aspects, and different effects in these aspects can be described with the lumped capacitor and inductor from the perspective of the equivalent circuit model. A physics-based equivalent circuit model is proposed to model transformers under different ground conditions. In addition, the simple parameter extraction procedure for the corresponding model is also provided. All the model parameters are extracted and agree with the analysis. In order to verify the model's validity and accuracy, we have compared the modeled and measured S-parameters, and an excellent agreement has been found over a broad frequency range.

  • SEMICONDUCTOR TECHNOLOGY

  • Anodic bonding using a hybrid electrode with a two-step bonding process

    Luo Wei, Xie Jing, Zhang Yang, Li Chaobo, Xia Yang

    J. Semicond.  2012, 33(6): 066001

    doi: 10.1088/1674-4926/33/6/066001

    Abstract PDF Get Citation

    A two-step bonding process using a novel hybrid electrode is presented. The effects of different electrodes on bonding time, bond strength and the bonded interface are analyzed. The anodic bonding is studied using a domestic bonding system, which carries out a detailed analysis of the integrity of the bonded interface and the bond strength measurement. With the aid of the hybrid electrode, a bubble-free anodic bonding process could be accomplished within 15-20 min, with a shear strength in excess of 10 MPa. These results show that the proposed method has a high degree of application value, including in most wafer-level MEMS packaging.

  • Statistical key variable analysis and model-based control for improvement performance in a deep reactive ion etching process

    Chen Shan, Pan Tianhong, Li Zhengming, Jang Shi-Shang

    J. Semicond.  2012, 33(6): 066002

    doi: 10.1088/1674-4926/33/6/066002

    Abstract PDF Get Citation

    This paper proposes to develop a data-driven via's depth estimator of the deep reactive ion etching process based on statistical identification of key variables. Several feature extraction algorithms are presented to reduce the high-dimensional data and effectively undertake the subsequent virtual metrology (VM) model building process. With the available on-line VM model, the model-based controller is hence readily applicable to improve the quality of a via's depth. Real operational data taken from a industrial manufacturing process are used to verify the effectiveness of the proposed method. The results demonstrate that the proposed method can decrease the MSE from 2.2×10-2 to 9×10-4 and has great potential in improving the existing DRIE process.

  • H-plasma-assisted aluminum induced crystallization of amorphous silicon

    Li Juan, Liu Ning, Luo Chong, Meng Zhiguo, Xiong Shaozhen, Hoi Sing Kwok

    J. Semicond.  2012, 33(6): 066003

    doi: 10.1088/1674-4926/33/6/066003

    Abstract PDF Get Citation

    A technique to improve and accelerate aluminum induced crystallization (AIC) by using hydrogen plasma is proposed. Raman spectroscopy and secondary ion mass spectrometry of crystallized poly-Si thin films show that hydrogen plasma radicals reduce the crystallization time of AIC. This technique shortens the annealing time from 10 to 4 h and increases the Hall mobility from 22.1 to 42.5 cm2/(V·S). The possible mechanism of AIC assisted by hydrogen radicals is also discussed.

  • Rapid thermal annealing effects on vacuum evaporated ITO for InGaN/GaN blue LEDs

    Ding Yan, Guo Weiling, Zhu Yanxu, Liu Jianpeng, Yan Weiwei

    J. Semicond.  2012, 33(6): 066004

    doi: 10.1088/1674-4926/33/6/066004

    Abstract PDF Get Citation

    8 mil × 10 mil InGaN/GaN blue LEDs with indium tin oxide (ITO) emitting at 460 nm were fabricated. A vacuum evaporation technique was adopted to deposit ITO on P-GaN with thickness of 240 nm. The electrical and optical properties of ITO films on P-GaN wafers, as well as rapid thermal annealing (RTA) effects at different temperatures (100 to 550 ℃) were analyzed and compared. It was found that resistivity of 450 ℃ RTA was as low as 1.19 × 10-4 Ω·cm, along with a high transparency of 94.17% at 460 nm. AES analysis indicated the variation of oxygen content after 450 ℃ annealing, and ITO contact resistance showed a minimized value of 3.9 × 10-3 Ω·cm2. With 20 mA current injection, it was found that forward voltage and output power were 3.14 V and 12.57 mW. Furthermore, maximum luminous flux of 0.49 lm of ITO RTA at 550 ℃ was measured, which is the consequence of a higher transparency.

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