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Volume 33, Issue 7, Jul 2012

    SEMICONDUCTOR PHYSICS

  • First-principles study of the electronic structures and optical properties of C–F–Be doped wurtzite ZnO

    Zuo Chunying, Wen Jing, Zhong Cheng

    J. Semicond.  2012, 33(7): 072001

    doi: 10.1088/1674-4926/33/7/072001

    Abstract PDF Get Citation

    The electronic structure and optical properties of pure, C-doped, CF codoped and CFBe cluster-doped ZnO with a wurtzite structure were calculated by using the density functional theory with the plane-wave ultrasoft pseudopotentials method. The results indicate that p-type ZnO can be obtained by C incorporation, and the energy level of Cm O above the valence band maximum is 0.36 eV. The ionization energy of the complex Zn16O14CF and Zn15BeO14CF can be reduced to 0.23 and 0.21 eV, individually. These results suggest that the defect complex of Zn15BeO14CF is a better candidate for p-type ZnO. To make the optical properties clear, we investigated the imaginary part of the complex dielectric function of undoped and CFBe doped ZnO. We found that there is strong absorption in the energy region lower than 2.7 eV for the CFBe doped system compared to pure ZnO.

  • The conductive path in HfO2: first principles study

    Zhou Maoxiu, Zhao Qiang, Zhang Wei, Liu Qi, Dai Yuehua

    J. Semicond.  2012, 33(7): 072002

    doi: 10.1088/1674-4926/33/7/072002

    Abstract PDF Get Citation

    The conductive path formed by the interstitial Ag or substitutional Ag in HfO2 was investigated by using the Vienna ab initio simulation package based on the DFT theory. The calculated results indicated that the ordering of interstitial Ag ions at special positions can form a conductive path, and it cannot form at other positions. The orientation dependence of this conductive path was then investigated. Various types of super cells are also built to study the rupture of the path, which corresponds to some possible “off” states.

  • SEMICONDUCTOR MATERIALS

  • Humidity sensing properties of Cu2O-PEPC nanocomposite films

    Kh. S. Karimov, M. Saleem, Z. M. Karieva, A. Mateen, M. Tariq Saeed Chani, Q. Zafar

    J. Semicond.  2012, 33(7): 073001

    doi: 10.1088/1674-4926/33/7/073001

    Abstract PDF Get Citation

    A blend of copper oxide nanopowder (Cu2O), 3 wt.%, and poly-N-epoxypropylcarbazole (PEPC), 2 wt.%, in benzol was drop-casted on glass substrates with pre-deposited surface-type silver electrodes for the fabrication of Cu2O-PEPC nanocomposite thin films. The thicknesses of the Cu2O-PEPC films were in the range of 10--13 μm. The effect of humidity on the electrical properties of the nanocomposite films was investigated by measuring the capacitance and dissipation of the samples at two different frequencies of the applied voltage: 120 Hz and 1 kHz. The AC resistance of the samples was determined from the dissipation values, and the DC resistance was measured directly. The effect of ageing on the humidity sensing properties of the nanocomposite was observed. After ageing, it was observed that at 120 Hz and 1 kHz, under a humidity of up to 86% RH, the capacitance of the cell increased by 85 and 8 times, and the resistance decreased by 345 and 157 times, accordingly, with respect to 30% RH conditions. It was found that with an increase in frequency, the capacitance and resistance of the samples decreased. It is assumed that the humidity response of the cell is associated with the diffusion of water vapors and doping of the semiconductor nanocomposite by water molecules.

  • Microstructural properties of over-doped GaN-based diluted magnetic semiconductors grown by MOCVD

    Tao Zhikuo, Zhang Rong, Xiu Xiangqian, Cui Xugao, Li Li, Li Xin, Xie ZiLi, Zheng Youdou, Zheng Rongkun, Simon P Ringer

    J. Semicond.  2012, 33(7): 073002

    doi: 10.1088/1674-4926/33/7/073002

    Abstract PDF Get Citation

    We have grown transition metal (Fe, Mn) doped GaN thin films on c-oriented sapphire by metal-organic chemical vapor deposition. By varying the flow of the metal precursor, a series of samples with different ion concentrations are synthesized. Microstructural properties are characterized by using a high-resolution transmission electron microscope. For Fe over-doped GaN samples, hexagonal Fe3N clusters are observed with Fe3N (0002) parallel to GaN (0002) while for Mn over-doped GaN, hexagonal Mn6N2.58 phases are observed with Mn6N2.58(0002) parallel to GaN (0002). In addition, with higher concentration ions doping into the lattice matrix, the partial lattice orientation is distorted, leading to the tilt of GaN (0002) planes. The magnetization of the Fe over-doped GaN sample is increased, which is ascribed to the participation of ferromagnetic iron and Fe3N. The Mn over-doped sample displays very weak ferromagnetic behavior, which probably originates from the Mn6N2.58.

  • Structural and optical properties of Zn-doped β-Ga2O3 films

    Yue Wei, Yan Jinliang, Wu Jiangyan, Zhang Liying

    J. Semicond.  2012, 33(7): 073003

    doi: 10.1088/1674-4926/33/7/073003

    Abstract PDF Get Citation

    Intrinsic β-Ga2O3 and Zn-doped β-Ga2O3 films were prepared using RF magnetron sputtering. The effects of the Zn doping and thermal annealing on the structural and optical properties are investigated. In comparison with the intrinsic β-Ga2O3 films, the microstructure, optical transmittance, optical absorption, optical energy gap, and photoluminescence of Zn-doped β-Ga2O3 films change significantly. The post-annealed β-Ga2O3 films are polycrystalline. After Zn doping, the crystallization deteriorates, the optical band gap shrinks, the transmittance decreases and the UV, blue, and green emission bands are enhanced.

  • SEMICONDUCTOR DEVICES

  • Fabrication and characterization of a low frequency electromagnetic energy harvester

    Abu Riduan Md. Foisal, Gwiy-Sang Chung

    J. Semicond.  2012, 33(7): 074001

    doi: 10.1088/1674-4926/33/7/074001

    Abstract PDF Get Citation

    This paper presents the fabrication and characterization of an AA size electromagnetic energy transducer based on vibration. A magnetic spring technique is used to scavenge energy from low frequency external vibration. The output of the harvester is maximized by optimizing the mass of moving and fixed magnets, coil width, coil position and load resistance through a comprehensive experimental analysis. The prototype can generate an open circuit voltage of 3.961 V and 1.18 mW average power at a load resistance of 97 Ω with 9 Hz resonance frequency and 0.5 mm displacement.

  • A different approach for determining the responsivity of n+p detectors using scanning electron microscopy

    Omeime Xerviar Esebamen, Göran Thungström, Hans-Erik Nilsson

    J. Semicond.  2012, 33(7): 074002

    doi: 10.1088/1674-4926/33/7/074002

    Abstract PDF Get Citation

    This paper explores an alternative to the standard method of studying the responsivities (the input--output gain) and other behaviours of detectors at low electron energy. The research does not aim to compare the results of differently doped n+p detectors; its purpose is to provide an alternative characterization method (using scanning electron microscopy) to those used in previous studies on the responsivity of n+p doped detectors as a function of the electron radiation energy and other interface parameters.

  • Effect of a gate buffer layer on the performance of a 4H-SiC Schottky barrier field-effect transistor

    Zhang Xianjun, Yang Yintang, Chai Changchun, Duan Baoxing, Song Kun, Chen Bin

    J. Semicond.  2012, 33(7): 074003

    doi: 10.1088/1674-4926/33/7/074003

    Abstract PDF Get Citation

    A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer.

  • An 88 nm gate-length In0.53Ga0.47As/In0.52Al0.48As InP-based HEMT with fmax of 201 GHz

    Zhong Yinghui, Wang Xiantai, Su Yongbo, Cao Yuxiong, Jin Zhi, Zhang Yuming, Liu Xinyu

    J. Semicond.  2012, 33(7): 074004

    doi: 10.1088/1674-4926/33/7/074004

    Abstract PDF Get Citation

    An 88 nm gate-length In0.53Ga0.47As/In0.52Al0.48As InP-based high electron mobility transistor (HEMT) was successfully fabricated with a gate width of 2 × 50 μm and source--drain space of 2.4 μm. The T-gate was defined by electron beam lithography in a trilayer of PMMA/Al/UVIII. The exposure dose and the development time were optimized, and followed by an appropriate residual resist removal process. These devices also demonstrated excellent DC and RF characteristics: the extrinsic maximum transconductance, the full channel current, the threshold voltage, the current gain cutoff frequency and the maximum oscillation frequency of the HEMTs were 765 mS/mm, 591 mA/mm, --0.5 V, 150 GHz and 201 GHz, respectively. The HEMTs are promising for use in millimeter-wave integrated circuits.

  • A low on-resistance SOI LDMOS using a trench gate and a recessed drain

    Ge Rui, Luo Xiaorong, Jiang Yongheng, Zhou Kun, Wang Pei, Wang Qi, Wang Yuangang, Zhang Bo, Li Zhaoji

    J. Semicond.  2012, 33(7): 074005

    doi: 10.1088/1674-4926/33/7/074005

    Abstract PDF Get Citation

    An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (Ron,sp) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and Ron,sp of 0.985 mΩ·cm2 (VGS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, Ron,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same Ron,sp.

  • Universal trench design method for a high-voltage SOI trench LDMOS

    Hu Xiarong, Zhang Bo, Luo Xiaorong, Li Zhaoji

    J. Semicond.  2012, 33(7): 074006

    doi: 10.1088/1674-4926/33/7/074006

    Abstract PDF Get Citation

    The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage (BV) and specific on-resistance (Rs,on) into account. The high-k (relative permittivity) dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs,on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

  • Giant magnetoresistance in a two-dimensional electron gas modulated by ferromagnetic and Schottky metal stripes

    Lu Jianduo, Xu Bin

    J. Semicond.  2012, 33(7): 074007

    doi: 10.1088/1674-4926/33/7/074007

    Abstract PDF Get Citation

    In this paper, by using the transfer matrix method, we theoretically investigate the magnetoresistance (MR) effect in a two-dimensional electron gas (2DEG) modulated by two Schottky metal (SM) stripes and two ferromagnetic (FM) stripes on the top and bottom of the 2DEG. From the numerical results, we find that a considerable MR effect can be achieved in this device due to the significant difference between electron transmissions through the parallel and antiparallel magnetization configurations. We also find that the MR ratio obviously depends on the magnetic strength and the electric-barrier height as well as the distance between the FM and SM stripes. These characters are very helpful for making the new type of MR devices according to their practical applications.

  • Enhanced light output power in InGaN/GaN light-emitting diodes with a high reflective current blocking layer

    Zhang Xiaojie, Yang Ruixia, Wang Jinghui

    J. Semicond.  2012, 33(7): 074008

    doi: 10.1088/1674-4926/33/7/074008

    Abstract PDF Get Citation

    The light output power of an InGaN/GaN light-emitting diode is improved by using a SiO2/TiO2 distributed Bragg reflector (DBR) and an Al mirror as a hybrid reflective current blocking layer (CBL). Such a hybrid reflective CBL not only plays the role of the CBL by enhancing current spreading but also plays the role of a reflector by preventing photons near the p-electrode pad from being absorbed by a metal electrode. At a wavelength of 455 nm, a 1.5-pair of SiO2/TiO2 DBR and an Al mirror (i.e. 1.5-pair DBR+Al) deposited on a p-GaN layer showed a normal-incidence reflectivity as high as 97.8%. With 20 mA current injection, it was found that the output power was 25.26, 24.45, 23.58 and 22.45 mW for the LED with a 1.5-pair DBR+Al CBL, a 3-pair DBR CBL, SiO2 CBL and without a CBL, respectively.

  • Investigation of the polysilicon p--i--n diode and diode string as a process compatible and portable ESD protection device

    Jiang Yibo, Du Huan, Han Zhengsheng

    J. Semicond.  2012, 33(7): 074009

    doi: 10.1088/1674-4926/33/7/074009

    Abstract PDF Get Citation

    The polysilicon p--i--n diode displays noticeable process compatibility and portability in advanced technologies as an electrostatic-discharge (ESD) protection device. This paper presents the reverse breakdown, current leakage and capacitance characteristics of fabricated polysilicon p--i--n diodes. To evaluate the ESD robustness, the forward and reverse TLP I--V characteristics were measured. The polysilicon p--i--n diode string was also investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. Finally, to explain the effects of the device parameters, we analyze and discuss the inherent properties of polysilicon p--i--n diodes.

  • Design and fabrication of an InP arrayed waveguide grating for monolithic PICs

    Pan Pan, An Junming, Wang Liangliang, Wu Yuanda, Wang Yue, Hu Xiongwei

    J. Semicond.  2012, 33(7): 074010

    doi: 10.1088/1674-4926/33/7/074010

    Abstract PDF Get Citation

    A 10-channel, 200 GHz channel spacing InP arrayed waveguide grating was designed, and the deep ridge waveguide design makes it polarization independent. Under the technologies of molecular beam epitaxy, lithography, and induced coupler plasma etching, the chip was fabricated in our laboratory. The test results show that the insertion loss is about --8 dB, and the crosstalk is less than --17 dB.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A uniform phase noise QVCO with a feedback current source

    Zhou Chunyuan, Zhang Lei, Qian He

    J. Semicond.  2012, 33(7): 075001

    doi: 10.1088/1674-4926/33/7/075001

    Abstract PDF Get Citation

    A novel integrated quadrature voltage controlled oscillator (QVCO) with a feedback current source is presented in this paper. Benefiting from the current adjusting function of the feedback current source, the proposed QVCO exhibits a uniform phase noise over the entire tuning range. This QVCO is implemented in 65-nm CMOS technology. The measurement results show that it draws less than 3-mA average current from a 1.2-V supply and the phase noise is less than -110 dBc/Hz @1MHz offset over the entire tuning range. The fluctuation of phase noise @1MHz offset from the center frequency of 2.84-GHz to 3.27-GHz is less than 1 dBc/Hz, which validates the correctness of the proposed current source feedback technique.

  • A fourth-order bandwidth-reconfigurable delta–sigma modulator for audio applications

    Wang Junqian, Yang Haifeng, Wei Rui, Xu Jun, Ren Junyan

    J. Semicond.  2012, 33(7): 075002

    doi: 10.1088/1674-4926/33/7/075002

    Abstract PDF Get Citation

    A single loop fourth-order deltasigma modulator is presented for audio applications. A reconfigurable mechanism is adopted for two bandwidth-based modes (8 kHz/16 kHz). Manufactured in the SMIC 0.13 μm CMOS mixed signal process, the chip consumes low power (153.6 μW) and occupies a core area of 0.98 × 0.46 mm2. The presented modulator achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode, as well as a 90.2 dB SNR and 86 dB dynamic range in 8 kHz mode. The designed modulator shows a very competitive figure of merit among state-of-the-art low voltage modulators.

  • A 20-GHz ultra-high-speed InP DHBT comparator

    Huang Zhenxing, Zhou Lei, Su Yongbo, Jin Zhi

    J. Semicond.  2012, 33(7): 075003

    doi: 10.1088/1674-4926/33/7/075003

    Abstract PDF Get Citation

    An ultra-high-speed, master-slave voltage comparator circuit is designed and fabricated using InP/GaInAs double heterojunction bipolar transistor technology with a current gain cutoff frequency of 170 GHz. The complete chip die, including bondpads, is 0.75 × 1.04 mm2. It consumes 440 mW from a single --4 V power supply, excluding the clock part. 77 DHBTs have been used in the monolithic comparator. A full Nyquist test has been performed up to 20 GHz, with the input sensitivity varying from 6 mV at 10 GHz to 16 mV at 20 GHz. To our knowledge, this is the first InP based integrated circuit including more than 70 DHBTs, and it achieves the highest sampling rate found on the mainland of China.

  • A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

    Gao Haijun, Sun Lingling, Kuang Xiaofei, Lou Liheng

    J. Semicond.  2012, 33(7): 075004

    doi: 10.1088/1674-4926/33/7/075004

    Abstract PDF Get Citation

    A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two-dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is --120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is --169 dBc/Hz.

  • An integrated CMOS high data rate transceiver for video applications

    Liang Yaping, Che Dazhi, Liang Cheng, Sun Lingling

    J. Semicond.  2012, 33(7): 075005

    doi: 10.1088/1674-4926/33/7/075005

    Abstract PDF Get Citation

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at --3 dBm output power.

  • A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS

    Xu Yang, Chi Baoyong, Xu Yang , Qi Nan, Wang Zhihua

    J. Semicond.  2012, 33(7): 075006

    doi: 10.1088/1674-4926/33/7/075006

    Abstract PDF Get Citation

    A low-power wideband hybrid automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers (PGAs), a differential peak detector, two comparators, a control algorithm logic, a decoder and the reference voltage source. Besides being controlled by an AGC loop, the gain of PGAs could alternatively be controlled by an off-chip digital baseband processor through the SPI interface. To obtain low power consumption and noise, an improved source degenerated amplifier is adopted, and the I/Q path phase mismatch within the ±5° range is calibrated with 0.2° accuracy. Implemented in 65 nm CMOS, the measured PGA total gains range from 9.8 to 59.5 dB with an average step of 0.95 dB and simulated bandwidth of more than 110 MHz. The settling time is about 180 μ s with 80% AM input with measured signal power from --76.7 to --56.6 dBm from a radio-frequency amplifier (RFA) input port, and also reduces to 90 μs with clock frequency doubling. The single AGC consumes almost 0.8 mA current from the 2.5-V supply and occupies an area of 750 × 300 μm2.

  • A new OLED SPICE model for pixel circuit simulation in OLED-on-silicon microdisplay design

    Zhao Bohua, Huang Ran, Bu Jianhui, Lü Yinxue, Wang Yiqi, Ma Fei, Xie Guohua, Zhang Zhensong, Du Huan, Luo Jiajun, Han Zhengsheng, Zhao Yi

    J. Semicond.  2012, 33(7): 075007

    doi: 10.1088/1674-4926/33/7/075007

    Abstract PDF Get Citation

    A new equivalent circuit model of organic-light-emitting-diode (OLED) is proposed. As the single-diode model is able to approximate OLED behavior as well as the multiple-diode model, the new model will be built based on it. In order to make sure that the experimental and simulated data are in good agreement, the constant resistor is exchanged for an exponential resistor in the new model. Compared with the measured data and the results of the other two OLED SPICE models, the simulated I--V characteristics of the new model match the measured data much better. This new model can be directly incorporated into an SPICE circuit simulator and presents good accuracy over the whole operating voltage.

  • A high-speed mixed-signal down-scaling circuit for DAB tuners

    Tang Lu, Wang Zhigong, Xuan Jiahui, Yang Yang, Xu Jian, Xu Yong

    J. Semicond.  2012, 33(7): 075008

    doi: 10.1088/1674-4926/33/7/075008

    Abstract PDF Get Citation

    A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler (DMP) with low phase noise is realized with a kind of improved source-coupled logic (SCL) D-flip-flop (DFF) in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave (CMOS MS)-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter (PS counter). Fabricated in a 0.18-μm CMOS process, the total chip size is 0.6 × 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of --118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit's core part is only 2.7 mW.

  • A new FPGA with 4/5-input LUT and optimized carry chain

    Mao Zhidong, Chen Liguang, Wang Yuan, Lai Jinmei

    J. Semicond.  2012, 33(7): 075009

    doi: 10.1088/1674-4926/33/7/075009

    Abstract PDF Get Citation

    A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources. We also develop a new carry chain structure with an optimized critical path. Finally a newly designed configurable scan-chain is inserted. The circuit is fabricated in 0.13 μm 1P8M 1.2/2.5/3.3 V logic CMOS process. The test results show a correct function of 4/5-input LUT and scan-chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 72.5%. Our results also show that the logic utilization of this work is better than that of a Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex II/Virtex 4 FPGA when implemented using only 5-LUT.

  • Worst-case total dose radiation effect in deep-submicron SRAM circuits

    Ding Lili, Yao Zhibin, Guo Hongxia, Chen Wei, Fan Ruyu

    J. Semicond.  2012, 33(7): 075010

    doi: 10.1088/1674-4926/33/7/075010

    Abstract PDF Get Citation

    The worst-case radiation effect in deep-submicron SRAM (static random access memory) circuits is studied through theoretical analysis and experimental validation. Detailed analysis about the radiation effect in different parts of circuitry is presented. For SRAM cells and a sense amplifier which includes flip-flop structures, their failure level against ionizing radiation will have a connection with the storage state during irradiation. They are inclined to store or read the same state as the one stored during irradiation. Worst-case test scheme for an SRAM circuit is presented, which contains a write operation that changes the storage states into the opposite ones after irradiation and then a read operation with opposite storage states. An irradiation experiment is designed for one 0.25 μm SRAM circuit which has a capacity of 1 k × 8 bits. The failure level against ionizing radiation concluded from this test scheme (150 krad(Si)) is much lower than the one from the simplest test scheme (1 Mrad(Si)). It is obvious that the failure level will be overestimated if the simplest test scheme is chosen as the test standard for SRAM circuits against ionizing radiation.

  • A 10 Gb/s burst-mode clock and data recovery circuit

    Gu Gaowei, Zhu En, Lin Ye, Liu Wensong

    J. Semicond.  2012, 33(7): 075011

    doi: 10.1088/1674-4926/33/7/075011

    Abstract PDF Get Citation

    We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A half-rate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS technology occupying an area of 675 × 25 μm2. The measured results show that this circuit can recover clock and data from each 10 Gbit/s burst-mode data packet within 5 bits, and the recovered data pass eye-mask test defined in IEEE standard 802.3av.

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