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Volume 38, Issue 9, Sep 2017


  • Effect of metal-fingers/doped-ZnO transparent electrode on performance of GaN/InGaN solar cell

    S.R. Routray, T.R. Lenka

    J. Semicond.  2017, 38(9): 092001

    doi: 10.1088/1674-4926/38/9/092001

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    The effect of doped-ZnO transparent conductive oxide (TCO) with metal (Ag)-fingers contact on GaN/InGaN solar cell is investigated through numerical simulations. An optical and electrical analysis of different dopant elements (such as B, Al, Ga, In and Sn) with ZnO as a top TCO layer is studied. A comparative analysis of metal square pad electrode, metal grid pattern electrode and metal-finger/ZnO type electrodes are taken into consideration to ensure the effect of anti-reflectivity by ZnO. The effect of thickness of ZnO and i-InGaN layer on performance of solar cell is also studied in detail. The proposed solar cell structure with Ag-fingers/ZnO:Al as top contact electrode shows interesting device characteristics compared to other dopants and metal top electrodes. The device achieves open circuit voltage~2.525 V, short circuit current~4.256 mA/cm2, fill factor~87.86% and efficiency~9.22% under 1 Sun, air mass 1.5 global illumination.

  • Effects of incident energy and angle on carbon cluster ions implantation on silicon substrate:a molecular dynamics study

    Ye Wei, Shengbo Sang, Bing Zhou, Xiao Deng, Jing Chai, Jianlong Ji, Yang Ge, Yuanliang Huo, Wendong Zhang

    J. Semicond.  2017, 38(9): 092002

    doi: 10.1088/1674-4926/38/9/092002

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    Carbon cluster ion implantation is an important technique in fabricating functional devices at micro/nanoscale. In this work, a numerical model is constructed for implantation and implemented with a cutting-edge molecular dynamics method. A series of simulations with varying incident energies and incident angles is performed for incidence on silicon substrate and correlated effects are compared in detail. Meanwhile, the behavior of the cluster during implantation is also examined under elevated temperatures. By mapping the nanoscopic morphology with variable parameters, numerical formalism is proposed to explain the different impacts on phrase transition and surface pattern formation. Particularly, implantation efficiency (IE) is computed and further used to evaluate the performance of the overall process. The calculated results could be properly adopted as the theoretical basis for designing nano-structures and adjusting devices' properties.


  • ZnSe/ITO thin films:candidate for CdTe solar cell window layer

    A.A. Khurram, M. Imran, Nawazish A. Khan, M. Nasir Mehmood

    J. Semicond.  2017, 38(9): 093001

    doi: 10.1088/1674-4926/38/9/093001

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    The crystal structure, electrical and optical properties of ZnSe thin films deposited on an In2O3:Sn (ITO) substrate are evaluated for their suitability as the window layer of CdTe thin film solar cells. ZnSe thin films of 80, 90, and 100 nm thickness were deposited by a physical vapor deposition method on Indium tin oxide coated glass substrates. The lattice parameters are increased to 5.834 Å when the film thickness was 100 nm, which is close to that of CdS. The crystallite size is decreased with the increase of film thickness. The optical transmission analysis shows that the energy gap for the sample with the highest thickness has also increased and is very close to 2.7 eV. The photo decay is also studied as a function of ZnSe film thickness.

  • Zinc-doped CdS nanoparticles synthesized by microwave-assisted deposition

    Abideen A. Ibiyemi, Ayodeji O Awodugba, Olusola Akinrinola, Abass A Faremi

    J. Semicond.  2017, 38(9): 093002

    doi: 10.1088/1674-4926/38/9/093002

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    Cd1-xZnxS nanoparticles were grown on pre-cleaned glass substrates using microwave-assisted chemical bath deposition technique. Nanoparticles obtained by this method were smooth, uniform, good adherent, brownish yellow in color where the brightness of the yellow color nature decreases with increasing Zn2+ content. The elemental composition analysis confirmed that the nanoparticles comprise of Cd2+, Zn2+and S2-. Scanning electron microscope images confirmed the surface uniformity of the Cd1-xZnxS nanoparticles devoid of any void, pinhole or cracks and covered the substrate well. The particle size also decreases with increasing Zn ion content. X-ray diffraction (XRD) indicates the hexagonal structure (002) without phase transition. The grain size decreases from 36.45 to 9.60 nm, dislocation density increases from 0.000745 to 0.01085 Line2/m2 and lattice parameter decreased from 6.868 to 6.155 nm with increasing Zn2+ content. The best transmittance of about 95% was achieved for x=1.0. The nanoparticles showed reduction in the absorbance as Zn ion content increased. Four point probe revealed that the electrical resistivity increased from 1.51×1010 to 6.67×1010 Ω ·cm while electrical conductivity decreases from 6.62×10-11 to 1.49×10-11 (Ω ·cm)-1 with increasing Zn2+ content. The other electrical properties such as sheet resistance increased from 1.52×108 to 1.58×108Ω, charge carrier mobility decreased from 0.777 to 0.0105 cm2/(V·s) and charge carrier density increased from 1.06×1012 to 3.95×1012 cm-3.

  • Attenuation characteristics of monolayer graphene by Pi-and T-networks modeling of multilayer microstrip line

    Pulkit Sharma, Pratap Singh, Kamlesh Patel

    J. Semicond.  2017, 38(9): 093003

    doi: 10.1088/1674-4926/38/9/093003

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    The impedances of Pi-and T-networks are obtained from the measured S-parameters of the multilayer microstrip line by modeling as an attenuator. The changes in impedances have been analyzed for the properties of various superstrates at the microwave ranges. With graphene on glass and graphene on quartz loadings, the impedances have increased and shifted towards lower frequency more in Pi-network than T-network modeling. This shift has become more prominent at higher frequency for the graphene on glass than graphene on quartz. A little increase in attenuation is found for graphene on glass or quartz than bare glass and quartz. The present study can be extended to obtain attenuation characteristic of any thin film by simple experimental method in the microwave frequencies.

  • Facile synthesis of Cu/tetrapod-like ZnO whisker compounds with enhanced photocatalytic properties

    Hong Liu, Huarong Liu, Ximei Fan

    J. Semicond.  2017, 38(9): 093004

    doi: 10.1088/1674-4926/38/9/093004

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    Cu/tetrapod-like ZnO whisker (T-ZnOw) compounds were successfully synthesized using N2H4·H2O as a reducing agent by a simple reduction method without any insert gas at room temperature. The crystal phase composition and morphology of the as-prepared samples were investigated by XRD, SEM and FESEM tests. The photocatalytic property of the as-prepared samples was detected by the degradation of methyl orange (MO) aqueous solution under UV irradiation. It can be found that Cu nanoparticles (CuNPs) dispersed on the surface of T-ZnOw increased with the increasing of Cu/Zn molar ratios (Cu/Zn MRs), and an octahedral structure of CuNPs was obtained when the sample was prepared with less than and equal to 7.30% Cu/Zn MR, but tended to a spherical or nanorod structure of CuNPs densely arranged on the surface of T-ZnOw, which is prepared by Cu/Zn MRs up to 22.00%. All the compounds exhibited excellent photocatalytic activity in decomposing of MO than T-ZnOw, the photocatalytic property of the samples increased with the increasing of Cu/Zn MRs up to 7.30%, while it decreases when further increasing the Cu/Zn MRs. The Schottky barrier of the Cu/T-ZnOw compound can effectively capture photoinduced electrons from the interface and enhanced the photocatalytic property of T-ZnOw.


  • A new RF trench-gate multi-channel laterally-diffused MOSFET on InGaAs

    M. Payal, Y. Singh

    J. Semicond.  2017, 38(9): 094001

    doi: 10.1088/1674-4926/38/9/094001

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    In this work, a new RF power trench-gate multi-channel laterally-diffused MOSFET (TGMC-LDMOS) on InGaAs is proposed. The gate-electrodes of the new structure are placed vertically in the trenches built in the drift layer. Each gate results in the formation of two channels in the p-body region of the device. The drain metal is also placed in a trench to take contact from the n+-InGaAs region located over the substrate. In a cell length of 5 μm, the TGMC-LDMOS structure has seven channels, which conduct simultaneously to carry drain current in parallel. The formation of multi-channels in the proposed device increases the drive current (ID) leading to a large reduction in the specific on-resistance (Ron-sp). Due to better control of gates on the drain current, the new structure exhibits substantially higher transconductance (gm) resulting in significant improvement in cut-off frequency (fT) and oscillation frequency (fmax). Using two-dimensional numerical simulations, a 55 V TGMC-LDMOS is demonstrated to achieve 7 times higher ID, 6.2 times lower Ron-sp, 6.3 times higher peak gm, 2.6 times higher fT, and 2.5 times increase in fmax in comparison to a conventional device for the identical cell length.

  • Few-mode vertical-cavity surface-emitting lasers for space-division multiplexing

    Yaman Su, Lijuan Yu, Xia Guo, Xing Zhang, Jianguo Liu, Ninghua Zhu

    J. Semicond.  2017, 38(9): 094002

    doi: 10.1088/1674-4926/38/9/094002

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    In order to choose the proper radius of oxide aperture for few-mode vertical-cavity surface-emitting lasers (VCSELs), the influences of oxide aperture size on the multi-transverse-mode behaviors are investigated in detail. By establishing the effective refractive index model to simulate VCSELs with different radii of oxide apertures, the wavelength and corresponding order of different modes are obtained. VCSELs with three kinds of oxide apertures are manufactured. Then the multi-transverse-mode spectra and near-field are measured. It is found that when the radius is between 1.5 and 4.5 μm, few-mode VCSELs can be implemented. The 2.5 μm VCSEL manufactured in this paper only emits LP01 mode and LP21 mode. Since the space distance between the two modes is 2 μm, it is expected to realize direct-modulation few-mode VCSELs by channel etching or ion implantation between the two modes.

  • Application research on the sensitivity of porous silicon

    Gaobin Xu, Ye Xi, Xing Chen, Yuanming Ma

    J. Semicond.  2017, 38(9): 094003

    doi: 10.1088/1674-4926/38/9/094003

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    Applications based on sensitive property of porous silicon (PSi) were researched. As a kind of porous material, the feasibility of PSi as a getter material was studied. Five groups of samples with different parameters were prepared. The gas-sensing property of PSi was studied by the test system and suitable parameters of PSi were also discussed. Meanwhile a novel structure of humidity sensor, using porous silicon as humidity-sensitive material, based on MEMS process has been successfully designed. The humidity-sensing properties were studied by a test system. Because of the polysilicon layer deposited upon the PSi layer, the humidity sensor can realize a quick dehumidification by itself. To extend service life and reduce the effect of the environment, a passivation layer (Si3N4) was also deposited on the surface of electrodes. The result indicated the novel humidity sensor presented high sensitivity (1.1 pF/RH%), low hysteresis, low temperature coefficient (0.5%RH/℃) and high stability.

  • Improved interfacial properties of GaAs MOS capacitor with NH3-plasma-treated ZnON as interfacial passivation layer

    Jingkang Gong, Jingping Xu, Lu Liu, Hanhan Lu, Xiaoyu Liu, Yaoyao Feng

    J. Semicond.  2017, 38(9): 094004

    doi: 10.1088/1674-4926/38/9/094004

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    The GaAs MOS capacitor was fabricated with HfTiON as high-k gate dielectric and NH3-plasma-treated ZnON as interfacial passivation layer (IPL), and its interfacial and electrical properties are investigated compared to its counterparts with ZnON IPL but no NH3-plasma treatment and without ZnON IPL and no plasma treatment. Experimental results show that low interface-state density near midgap (1.17×1012 cm-2eV-1) and small gate leakage current density have been achieved for the GaAs MOS device with the stacked gate dielectric of HfTiON/ZnON plus NH3-plasma treatment. These improvements could be ascribed to the fact that the ZnON IPL can effectively block in-diffusion of oxygen atoms and out-diffusion of Ga and As atoms, and the NH3-plasma treatment can provide not only N atoms but also H atoms and NH radicals, which is greatly beneficial to removal of defective Ga/As oxides and As-As band, giving a high-quality ZnON/GaAs interface.


  • A power management circuit with 50% efficiency and large load capacity for triboelectric nanogenerator

    Dechun Bao, Lichuan Luo, Zhaohua Zhang, Tianling Ren

    J. Semicond.  2017, 38(9): 095001

    doi: 10.1088/1674-4926/38/9/095001

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    Recently, triboelectric nanogenerators (TENGs), as a collection technology with characteristics of high reliability, high energy density and low cost, has attracted more and more attention. However, the energy coming from TENGs needs to be stored in a storage unit effectively due to its unstable ac output. The traditional energy storage circuit has an extremely low energy storage efficiency for TENGs because of their high internal impedance. This paper presents a new power management circuit used to optimize the energy using efficiency of TENGs, and realize large load capacity. The power management circuit mainly includes rectification storage circuit and DC-DC management circuit. A rotating TENG with maximal energy output of 106 mW at 170 rpm based on PCB is used for the experimental verification. Experimental results show that the power energy transforming to the storage capacitor reach up to 53 mW and the energy using efficiency is calculated as 50%. When different loading resistances range from 0.82 to 34.5 kΩ are connected to the storage capacitor in parallel, the power energy stored in the storage capacitor is all about 52.5 mW. Getting through the circuit, the power energy coming from the TENGs can be used to drive numerous conventional electronics, such as wearable watches.

  • An isolated SNM model for high-stability multi-port register file in 65 nm CMOS

    Yuejun Zhang, Pengjun Wang, Gang Li

    J. Semicond.  2017, 38(9): 095002

    doi: 10.1088/1674-4926/38/9/095002

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    In modern microprocessors, the multi-port register file is one of the key modules which provides fast and multiple data access for instructions. As the number of access ports in register files increases, stability becomes a key issue due to the voltage fluctuation on bit lines. We propose to apply an isolated inverter to address the voltage fluctuation. To assess the register stability, we derive a closed-form expression of static noise margin (SNM) for our register file. The proposed SNM model can be used as a guideline to predict the impact of several register parameters on the stability and optimize register file designs. To validate the proposed SNM model, we fabricated a test chip of two-write-four-read (2W4R) 1024 bits register file in a TSMC 65 nm low-power CMOS technology. The experimental result shows that the stability of our register file cells with an isolated inverter improve the conventional cells by approximately 2.4 times. Also, the supply voltage causes a fluctuation of SNM of about 65%, while temperature and transistor mismatch cause a fluctuation of SNM of about 20%.

  • The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

    Peng Xu, Zhongliang Pan

    J. Semicond.  2017, 38(9): 095003

    doi: 10.1088/1674-4926/38/9/095003

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    With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level, intermediate level and global level, respectively.Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.


  • Films surface temperature calculation during growth by sputtering technique

    F. Khelfaoui, M. S. Aida

    J. Semicond.  2017, 38(9): 096001

    doi: 10.1088/1674-4926/38/9/096001

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    A calculation of film surface temperature during thin films growth by sputtering technique is proposed. The calculation procedure is based on the conversion into heat of the total flux energy of species impinging the film surface during growth. The results indicate that the film's surface temperature depends drastically on material substrate thermal conductivity and thickness on one hand, and the plasma conditions namely the discharge power on the other. The predicted film surface temperatures were used to explain the microstructure evolution of hydrogenated amorphous silicon (a-Si:H) thin films deposited by reactive radio frequency (RF) sputtering on different substrates.

  • Design of 20 W fiber-coupled green laser diode by Zemax

    Yunfei Qi, Pengfei Zhao, Yulong Wu, Yongqi Chen, Yonggang Zou

    J. Semicond.  2017, 38(9): 096002

    doi: 10.1088/1674-4926/38/9/096002

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    We represent a design of a 20 W, fiber-coupled diode laser module based on 26 single emitters at 520 nm. The module can produce more than 20 W output power from a standard fiber with core diameter of 400 μm and numerical aperture (NA) of 0.22. To achieve a 20 W laser beam, the spatial beam combination and polarization beam combination by polarization beam splitter are used to combine output of 26 single emitters into a single beam, and then an aspheric lens is used to couple the combined beam into an optical fiber. The simulation shows that the total coupling efficiency is more than 95%.

  • Shear strength of LED solder joints using SAC-nano Cu solder pastes

    Yang Liu, Fenglian Sun, Ping Liu, Xiaolong Gu, Guoqi Zhang

    J. Semicond.  2017, 38(9): 096003

    doi: 10.1088/1674-4926/38/9/096003

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    The addition of Cu nanoparticles into the solder pastes by mechanical mixing method creates a positive effect on the microstructure refinement of the LED solder joints. The grain size of β-Sn and Cu6Sn5 decrease obviously due to the increasing concentration of the nanoparticles in the solder pastes. However, the addition of nanoparticles facilitates the formation of voids in the solder joints, especially when the concentration of nanoparticles is higher than 0.5 wt% in the solder pastes. Both the microstructure refinement and void percentage affect the shear strength of the solder joints. Since the increase of the void percentage is limited when the concentration of nanoparticles increases from 0 to 0.5 wt%, the microstructure refinement shows a dominant effect on the shear performance and thus improves the shear strength of the solder joints from 49.8 to 55 MPa. Further addition of nanoparticles in the solder pastes leads to a sharp increase of the void percentage. Consequently, the shear strength of the solder joints decreases from 55 to 48.8 MPa when the concentration of doped particles increases from 0.5 to 1 wt% in the solder pastes.

  • Method to remove wafer surface particles

    Bo Peng, Deguang Zheng, Yue Yu

    J. Semicond.  2017, 38(9): 096004

    doi: 10.1088/1674-4926/38/9/096004

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    A big yield drop has been observed during the automatic inspection (AOI) after the saw stage. A step by step AOI inspection check and defect review is made to see which step made a big yield drop and which kind of defect contributed most to the yield drop. Scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) analysis showed the shape and chemical element of the particle. From the EDS result, particles can be separated into two categories. One was the inorganic related materials, mainly including silicon (Si) element, which came from the saw stage. A design of experiment (DOE) is used to find some reasonable saw relative parameter and optimize it in order to remove the particle from the saw stage. But the quantity of this kind of particle was small. Yield was only improved by less than 5%. Our main effort was to remove another kind of particle which was organic related materials, mainly including carbon (C) and oxygen (O) element. This kind of particle was from tape residue. In order to remove the tape residual, one step was added before the saw stage. Almost all of the tape residual was removed. Finally, the final yield was improved by more than 15%.

  • Study on the failure temperature of Ti/Pt/Au and Pt5Si2-Ti/Pt/Au metallization systems

    Jie Zhang, Jianqiang Han, Yijun Yin, Lizhen Dong, Wenju Niu

    J. Semicond.  2017, 38(9): 096005

    doi: 10.1088/1674-4926/38/9/096005

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    The Ti/Pt/Au metallization system has an advantage of resisting KOH or TMAH solution etching. To form a good ohmic contact, the Ti/Pt/Au metallization system must be alloyed at 400℃. However, the process temperatures of typical MEMS packaging technologies, such as anodic bonding, glass solder bonding and eutectic bonding, generally exceed 400℃. It is puzzling if the Ti/Pt/Au system is destroyed during the subsequent packaging process. In the present work, the resistance of doped polysilicon resistors contacted by the Ti/Pt/Au metallization system that have undergone different temperatures and time are measured. The experimental results show that the ohmic contacts will be destroyed if heated to 500℃. But if a 20 nm Pt film is sputtered on heavily doped polysilicon and alloyed at 700℃ before sputtering Ti/Pt/Au films, the Pt5Si2-Ti/Pt/Au metallization system has a higher service temperature of 500℃, which exceeds process temperatures of most typical MEMS packaging technologies.


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