We investigate the growth of InP-on-GaAs combined with the advantages of double low-temperature (LT) buffers and strained layer surperlattices (SLSs).It is found that LT-InP/LT-GaAs double LT buffers are more effective for strain accommodation than a LT-InP single buffer in InP-on-GaAs.On the other hand,there is an optimal thickness for LT-GaAs for a given thickness of the LT-InP layer,at which the double LT buffers can reach the best state for strain adjustment.Furthermore,the position of insertion of SLSs should be carefully designed because the distance above the InP/buffer interface plays an important role in threading dislocation interactions for dislocation reduction.As a result,the density of threading dislocations in the InP epilayer is markedly reduced.X-ray diffraction measurements show that the full width at half maximum of the ω/2θ rocking curve for the 2μm-thick InP epilayer is less than 200" .

A buried-oxide trench-gate bipolar-mode JFET (BTB-JFET) with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed.Simulations with a resistive load circuit for power loss comparison at high frequency application are performed with 20V-rated power switching devices,including a BTB-JFET,a trench MOSFET (T-MOSFET) generally applied in present industry,and a conventional trench-gate bipolar-mode JFET (TB-JFET) without buried oxide,for the first time.The simulation results indicate that the switching power loss of the normally-on BTB-JFET is improved by 37% and 14% at 1MHz compared to the T-MOSFET and the normally-on TB-JFET,respectively.In order to demonstrate the validity of the simulation,the normally-on TB-JFET and BTB-JFET have been fabricated successfully for the first time,where the buried oxide structure is realized by thermal oxidation.The experimental results show that the Cgd of the BTB-JFET is decreased by 45% from that of the TB-JFET at zero source-drain bias.Compared to the TB-JFET,the switching time and switching power loss of the BTB-JFET decrease approximately by 7.4% and 11% at 1MHz,respectively.Therefore,the normally-on BTB-JFET could be pointing to a new direction for the R&D of low voltage and high frequency switching devices.

Monolithic GaAs pin diode single pole double throw (SPDT) switches based on the fabrication technology of IMECAS are designed,fabricated,and tested.These SPDT switches achieve an insertion loss of 1.5dB,isolation of 32dB,and input and output return losses over 10dB from 8 to 20GHz.The switch design uses 2.5μm thick I-region GaAs pin diodes and a series-shunt-shunt switch topology in each arm.These performance characteristics are measured at a normal bias setting of 1.3V,which corresponds to 7mA of series diode bias current.

This paper demonstrates the design and fabrication of a monolithic HBT power amplifier for TD-SCDMA cellular phones that achieves high efficiency and linearity.The two-stage MMIC integrates the input matching circuits,inter-stage matching circuits,and active bias circuits in a single chip with size as small as 0.91mm×0.98mm.The amplifier obtains a power-added efficiency of 43% (15%) and a gain of 28.5dB (24dB) at the high and low operation mode under the 3.4V supply.In addition,the adjacent channel leakage power is below -45dBc/-56dBc and -39dBc/-50dBc at 1.6MHz/3.2MHz offset in low and high power output modes,respectively,with QPSK modulation.The MMIC offers the potential for low cost production due to small chip size,stable voltage supply,and high performance at the same time.

A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented.The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up but is opened during normal operation.This method reduces calibration time significantly compared with its closed-loop counterpart.The dual-loop PLL architecture is adopted to achieve a process-independent damping factor and pole-zero separation.A new phase frequency detector embedded with a level shifter is introduced.Careful power partitioning is explored to minimize the noise coupling.The proposed PLL achieves 3.1ps RMS jitter running at 1.6GHz while consuming only 0.94mA.

Theoretical calculations via the transfer matrix method (TMM) are performed to investigate optical properties of one-dimensional semiconductor-organic photonic crystals (SOPC) with periodic conjugated polymer (3-octylthiophenes,P3OT)/AlN multilayer structure.The SOPC presents incomplete photonic band gap behavior in the UV region.P3OT/AlN multilayers with two pairs of 30nm-P3OT and 30nm-AlN layers exhibit a photonic band gap at a central wavelength of about 275nm,and the highest reflectivity reaches 98%.Furthermore,the band gaps are confirmed to be tunable by adjusting the lattice period and the filling fraction.As a consequence,the SOPC is important for achieving materials with an incomplete band gap in the UV region.

The electronic structure of pure and S-doped chalcopyrite CuInSe2 is investigated using a first-principles pseudopotential method in the generalized gradient approximation.The calculation indicates that the band gap of CuInSe2 broadens as S-doping concentration increases.We find that the decreased lattice volume due to isovalent S-doping in CuInSe2 has a significant impact on the band gap broadening phenomena.This physical insight is further discussed with the study of the electronic structure and bond length changes.

The temperature is a key factor for the quality of the SiGe alloy grown by D-UHV/CVD.In conventional conditions,the lowest temperature for SiGe growth is about 550℃.Generally,the pressure of the growth chamber is about 1E-5Pa when liquid nitrogen is introduced into the wall of the growth chamber with the flux of 6sccm of the disilane gas.We have succeeded in depositing SiGe films at much lower temperature using a novel method.It is about 1E-2Pa without liquid nitrogen,about 3 magnitudes higher than the traditional method,leading to much faster deposition rate.Without liquid nitrogen,the SiGe film and SiGe/Si superlattice are grown at 485℃.The DCXRD curves and TEM image show that the quality of the film is good.The experiments show that this method is efficient to deposit SiGe at low temperature.

Biaxial strain technology is a promising way to improve the mobility of both electrons and holes,while 〈100〉 channel direction appears as to be an effective booster of hole mobility in particular.In this work,the impact of biaxial strain together with 〈100〉 channel orientation on hole mobility is explored.The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain.The channel orientation was implemented with a 45° rotated design in the device layout,which changed the channel direction from 〈110〉 to 〈100〉 on Si (001) surface.The maximum hole mobility is enhanced by 30% due to the change of channel direction from 〈110〉 to 〈100〉 on the same strained Si (s-Si) p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along 〈110〉 channels.Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.

A non-micro-air-bridge InP-based heterojunction bipolar transistor (HBT) is fabricated.A very small emitter side etching (＜100nm) is developed and makes a submicron InP-based HBT possible.The current gain cutoff frequency is as high as 238GHz for the submicron HBT with an emitter area of 0.8μm×15μm due to the reduction of emitter width.A base-collector over-etching technology is developed,resulting in a reduction of base-collector junction area and an increase in the maximum oscillation frequency.A very high Kirk current density of 3.1mA/μm2 is obtained.To the best of our knowledge,the current gain cutoff frequency is the highest among three-terminal devices in China and the Kirk current density is also the highest in HBTs reported in China.This is very helpful for the application of HBTs in ultra high-speed circuits.

A new SOI high-voltage device structure with nonuniform thickness drift region (n-uni SOI) and its optimization design method are proposed.Owing to the nonuniform thickness drift region,the electric field in the SOI layer is modulated and the electric field in the buried layer is enhanced,resulting in an enhancement of breakdown voltage.An analytical model taking the modulation effect into account is presented to optimize the device structure.Based on the analytical model,the dependencies of the electric field distribution and breakdown voltage on the device parameters are investigated.Numerical simulations support the analytical model.The breakdown voltage of the n-uni SOI LDMOS with n=3 is twice as high as that of a conventional SOI while its on-resistance maintains low.

This paper reports the piezoresistive effect of a resonant tunneling diode (RTD) in a microstructure.The four-beam structure is analyzed and fabricated by positing RTDs at the stress sensitive regions.Stress along the ［110］ orientation and ［110］ orientation induces a change in the RTD’s current-voltage (I-V) curves,i.e.,the meso-piezoresistance variety,mainly in its negative different resistance (NDR) region.By different methods,the mechanic-electric coupling characteristic of RTD is studied and the consistent 1E-9Pa-1 piezoresistive coefficients are discovered.

The quenched domain mode of the photo-activated charge domain (PACD) in semi-insulating (SI) GaAs photoconductive semiconductor switches (PCSSs) is observed.We find that the quenched domain is induced by the instantaneous electric field across the PCSS being lower than the sustaining electric field of the domain during the transit of the domain.The extinction of the domain before reaching the anode can lead to a current oscillation frequency larger than the transit-time frequency when the bias electric field is lower than the threshold electric field of the nonlinear PCSS.According to the operation circuit and the physical properties of a high-field domain,an equivalent circuit of the quenched domain is presented.The equivalent circuit parameters including capacitance,resonant frequency,and inductance are calculated and measured.Our calculations agree well with the experimental results.This research provides theoretical and experimental criteria for heightening the oscillation frequency and efficiency of PACD devices.

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors.The SRAM cell is based on 32nm silicon-on-insulator (SOI) technology node.It consists of two access transistors and two pull-down transistors.The pull-down transistors have larger channel length than the access transistors.Due to the significant short channel effect of small-size MOS transistors,the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic "1" while in standby.The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable "read" operation of the cell.The use of back-gate feedback also helps to improve the static noise margin (SNM) of the cell.The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells.The speed and power dissipation of the SRAM cell are simulated and discussed.The SRAM cell can operate with a 0.5V supply voltage.

A novel large-signal equivalent circuit model of RF-SOI LDMOS based on Philips MOS Model 20 (MM20) is presented.The weak avalanche effect and the power dissipation caused by self-heating are described.The RF parasitic elements are extracted directly from measured S-parameters with analytical methods.Their final values can be obtained quickly and accurately through the necessary optimization.The model is validated in DC,AC small-signal,and large-signal analyses for an RF-SOI LDMOS of 20-fingers (channel mask length,L=1μm,finger width,W=50μm) gate with high resistivity substrate and body-contact.Excellent agreement is achieved between simulated and measured results for DC,S-parameters (10MHz~2.01GHz),and power characteristics,which shows our model is accurate and reliable.MM20 is improved for RF-SOI LDMOS large-signal applications.This model has been implemented in Verilog-A using the ADS circuit simulator (hpeesofsim).

A one-time programmable metal-molecule-metal device,with a modified Rotaxane LB film as the functional layer,is proposed for potential use in organic programmable and fault tolerant circuits like inorganic anti-fuse devices used in field programmable gate arrays.All fabrication methods involved are low temperature processes,ensuring that this device can be integrated with other organic devices.Electrical measurements show that this device has a good one-time programming capability.Its break down voltage is 2.2V,off-state resistance is 15kΩ,and on-state resistance is 54Ω.These characteristics come from the penetration of metal atoms into molecular film under high electronic field.

An integrated micro positioningxy-stage with a 2mm×2mm-area shuttle is fabricated for application in nano-meter-scale operation and nanometric positioning precision.It is mainly composed of a silicon-based xy-stage,electrostatics comb actuator,and a displacement sensor based on a vertical sidewall surface piezoresistor.They are all in a monolithic chip and developed using double-sided bulk-micromachining technology.The high-aspect-ratio comb-driven xy-stage is achieved by deep reactive ion etching (DRIE) in both sides of the wafer.The detecting piezoresistor is located at the vertical sidewall surface of the detecting beam to improve the sensitivity and displacement resolution of the piezoresistive sensors using the DRIE technology combined with the ion implantation technology.The experimental results verify the integrated micro positioning xy-stage design including the micro xy-stage,electrostatics comb actuator,and the vertical sidewall surface piezoresistor technique.The sensitivity of the fabricated piezoresistive sensors is better than 1.17mV/μm without amplification and the linearity is better than 0.814%.Under 30V driving voltage,a ±10μm single-axis displacement is measured without crosstalk and the resonant frequency is measured at 983Hz in air.

High speed and high accuracy ADC is a necessary part in large pixel scale CMOS image sensor. As evolution of technology, low power consumption design has attracted a lot attention. To reduce power consumption without losing performance, the same structure amplifiers are biased with the same bias circuit, and adopt cascode compensation to reduce power consumption. Noise and mismatch are more important error sources in pipeline ADC, so careful calculation and system simulation have been carried out by using Matlab in this paper. In this paper, a 10 bit 50MS/s pipeline ADC core has been presented, which can be used in large pixel scale CMOS image sensor. A balance between performance and power consumption has been achieved.

A fully integrated CMOS bio-chip is designed in a SMIC 0.18μm CMOS mixed signal process and successfully integrated with a novel bio-nano-system.The proposed circuit integrates an array of 4×4 (16 pixels) of 19μm×19μm electrodes,a counter electrode,a current mode preamplifier circuit (CMPA),a digital decoding circuit,and control logics on a single chip.It provides a -1.6～1.6V range of assembly voltage,8bit potential resolution,and a current gain of 398dB with supply voltage of 1.8V.The offset and noise are smaller than 5.9nA and 25.3pArms,respectively.Experimental results from on-chip selective assembly of 30nm poly (ethylene glycol) (PEG) coated magnetic nano-particles (MNPs) targeted at biosensor applications are included and discussed to verify the feasibility of the proposed circuits.

A buck DC/DC switching regulator is implemented by automatically altering the modulation mode according to the load current that ranges from 0.01 to 3A.The pseudo-PFM mode is applied when duty cycle is less than 20%,and the PWM mode is selected in a range of duty cycle from 20% to 100%.The average conversion efficiency of the regulator is about 90% when the output current varies.The proposed dual-mode-control die is implemented in a 0.5μm DPDM CMOS mixed-signal process and a power p-MOSFET is used in the chip by hybrid integration.

This paper describes a CMOS low noise amplifier (LNA) plus the quadrature mixers intended for use in the front-end of portable global positioning system (GPS) receivers.The LNA makes use of an inductively degenerated input stage and power-constrained simultaneous noise and input matching techniques.The quadrature mixers are based on a Gilbert cell type.The circuits are implemented in a TSMC 0.18μm RF CMOS process.Measurement results show that a voltage conversion gain of 35dB is achieved with a cascade noise figure of 2.4dB,an input 1dB compression point of -22dBm,and an input return loss of -22.3dB.The fully differential circuits only draw 5.4mW from a 1.8V supply.

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process.With a high Q on-chip inductor,the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage.Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112dBc/Hz at 1MHz offset from a 3.142GHz carrier.The performance of the frequency synthesizer meets the requirements of GPS applications very well.

A piecewise curvature-corrected bandgap reference (BGR) with negative feedback is proposed.It features employing a temperature-dependent resistor ratio technique to get a piecewise corrected current,which corrects the nonlinear temperature dependence of the first-order BGR.The piecewise corrected current generator also forms negative feedback to improve the line regulation and power supply rejection (PSR).Measurement results show the proposed BGR achieves a maximum temperature coefficient (TC) of 21.2ppm/℃ without trimming in the temperature range of -50~125℃ and a PSR of -60dB at 2.6V supply voltage.The line regulation is 0.8mV/V in the supply range of 2.6~5.6V.It is successfully implemented in an SMIC 0.35μm 5V n-well digital CMOS process with the effective chip area of 0.04mm2 and power consumption of 0.18mW. The reference is applied in a 3,5V optical receiver trans-impedance amplifier.

The photon-activated monopole domain in a semi-insulating multi-valley photoconductive semiconductor switch and the dipole domain in a Gunn device are compared.The generation mechanism,electric field distribution,electron concentration distribution,growth and evolution of the photon-activated monopole domain are discussed.Compared with the Gunn dipole domain,there is only an accumulation layer of photon-activated electrons in the photon-activated monopole domain,but no layer of positive ions;Because the electric field formed by the photon-activated monopole domain and the photon-activated holes is the opposite of the external electric field,the electric field before the monopole domain is enhanced and the electron concentration at the head of the domain is higher than in other regions;a monopole domain can grow until it becomes a luminous domain because of impact ionization,and a luminous domain will evolve into an avalanche luminous domain if it reaches avalanche conditions.Finally,important experimental phenomena of the switch working in nonlinear mode,such as the ultrafast rising edge,luminous current filaments,and the lock-on state of current,are explained by the model of the photon-activated monopole domain.

The oxygen precipitation behaviors in conventional and nitrogen-doped Czochralski (NCZ) silicon subjected to the rapid thermal processing (RTP) at 1250℃ for 50s followed by the ramping anneal in different temperature intervals in the range from 600 to 1000℃ and isothermal annealing at 1000℃ are investigated. The results show that the RTP-induced vacancies enhance the nucleation of oxygen precipitates most significantly during the ramping anneal from 700 to 800℃ for conventional CZ silicon.Meanwhile,for NCZ silicon,the most significant vacancy-enhancement of nucleation of oxygen precipitates occurs during the ramping anneal from 800 to 900℃. Nitrogen is superior to vacancy for enhancement of oxygen precipitate nucleation at temperatures higher than 800℃. Furthermore,the internal gettering processes appropriate for CZ and NCZ silicon wafers based on the RTP and ramping anneal in the low temperature range are proposed.

Sb-doped ZnO single crystal has been grown at 950℃ by the chemical vapor transport method.Compared to undoped ZnO,the Sb-doped ZnO single crystal is still n-type with an apparent increase of free electron concentration.X-ray photoelectron spectroscopy (XPS) measurement results suggest a possible occupation of the Zn site of the doped Sb in the ZnO single crystal,resulting in the formation of a donor.Blue emission is observed from the PL spectrum of the Sb doped ZnO single crystal,which is related with a shallow donor defect in ZnO.The results indicate that a high concentration of donor defects forms in ZnO after Sb doping at high temperature,making it difficult to obtain p-type material.

ZnO thin films were deposited on TiO2 buffer layers by electron beam evaporation.The effect of annealing temperature on crystalline quality and photoluminescence of the films was studied.The structural characteristics of the as-deposited and annealed films were investigated by an X-ray diffractometer and a scanning probe microscope.The photoluminescence was studied by fluorophotometer.The analysis results show that all the annealed ZnO thin films grown on TiO2 buffer layers are preferentially oriented along the c-axis.The film annealed at 600℃ has the highest (002) diffraction peak,the strongest ultraviolet emission,and the weakest visible emission.Its grain sizes are uniform and its grains are closed packed.The samples annealed at 500 and 700℃ have relatively strong visible emissions that originated from defects.These indicate that the film annealed at 600℃ has the best crystalline quality.

Au/Cr and Au/Ti/Al/Ti metal buffer layers were respectively deposited on Si(111) substrate by electron beam evaporation,and GaN was grown on these metal films by gas source molecular beam epitaxy(GSMBE).The as-deposited metal films have a flat and featureless surface and show diffraction peaks of (111)-oriented cubic Au.The GaN grown on Au/Cr/Si(111) breaks off when cooled to room temperature.GaN grown on Au/Ti/Al/Ti/Si(111) without an AlN buffer layer was amorphous.By adding an AlN buffer,GaN grown on AlN/Au/Ti/Al/Ti/Si(111) shows diffraction peaks of (0001)-oriented hexagonal GaN.After annealing at 800℃ for 20min,the metal films of Au/Ti/Al/Ti/Si(111) became amorphous and convert to a porous metal network.

Droplet epitaxy is a new MBE growth method for semiconductor materials,but there has been no effective research concerning the influence of patterned substrate on droplet epitaxy until now.The authors report different quantum dots and quantum rings grown on different types of μm-scale patterned substrates and analyze the influence of patterned substrate on droplet epitaxy,the formation mechanism of the quantum rings,and their distribution behavior.

Nickel-silicon alloy target is used as a source of sputtering;a new type of nickel source,called a self-released nickel source,is fabricated.Self-released nickel source can control the crystallization rate efficiently and the obtained poly-Si material has a low level of nickel residue and high quality.p-type thin film transistors are fabricated using this kind of poly-Si as active islands.They have good performance and lower leakage current.

Based on the equivalent circuit of VDMOS,the initial condition and transient response process are analyzed and the ESD transient model of the power VDMOS device is obtained.Results show that the ESD transient discharge process is correctly depicted with this model,which resolves the problem of the insufficient initial conditions of other models.Based on this model,the relationships between ESD threshold voltage and gate input protection series resistance,breakdown voltage,and parasitic dynamic resistance of the Zener diodes,and gate-source capacitance and gate oxide thickness of the power VDMOS,are obtained.This model can guide the design of ESD protection for power VDMOSs

A novel method for electrically measuring the thermal expansion coefficient of polysilicon thin films is presented.A thermal-electro-mechanical compliant model of the polysilicon thin film is established.Finite element software Coventor and ANSYS are used to verify this method.This method is convenient,and its output is in the form of an electrical signal.Thus,it is valuable for in-situ measuring the thermal expansion coefficient of polysilicon thin films

Electromigration could induce the movement of atoms/ions towards the direction of electron flow in pure metal line in chips.However,in the eutectic SnBi solder joints,the constituted elements are Sn and Bi.Due to the different drift velocity of Bi atoms and Sn atoms under high current density,the electromigration properties of eutectic SnBi are unique.With a current density of 1E4A/cm2 and the Joule heating effect,the temperature of solder joints increased from 25 to 50℃,and the Bi-rich phases grew bigger during current stressing due to the high ambient temperature (49℃).In addition,Bi atoms initially arrived at the anode side and eventually formed a barrier layer to inhibit the movement of Sn atoms towards the anode side.Sn-rich phase bulged,and a valley formed along the interface at cathode side.

This paper presents a Monte Carlo method for the simulation of the surface morphology during wet anisotropic etching.Based on the step flow model,the atomistic characteristics of the active step region of four silicon crystalline families (h+2,h,h),(h,1,1),(h+2,h+2,h),and (h,h,1) are investigated.Atoms with 3 first neighbors and 7 second neighbors on the active step region are restricted in the removal probability under the effect of both micro mask and silicate particles adherence.By applying the above conditions on the RPF function,the formation of pyramid protrusion on (100) plane,the zigzag strip structures on (110) plane,and triangular etch pits on (111) plane is explained and simulated.The simulation result on three principle planes and high index (332) plane agrees well with the surface morphology from the experiment,which provides verification of the simulation method.

This paper presents a microstrip switch using pin diodes for Ku-band applications. At high frequency, especially for millimeter-wave applications, it is hard to obtain a switch with high-isolation, so this paper makes an effort to develop isolation of the switch using a novel topology that contains multiple unit cells and optimizes parameters of the unit cell circuit. The isolation of the fabricated switch is better than 95dB from 15.75 to 16.25GHz, the insertion loss is less than 4dB, S11 is better than -12dB,S22 is better than -20dB, and the entire circuit size is only 34mm×11mm×5mm.

A nano-polysilicon thin film pressure sensor is presented.Nano-polysilicon thin film is fabricated by LPCVD at a substrate temperature of 620℃,and then MEMS is adopted to fabricate four nano-polysilicon resistors with a film thickness of 63.0nm and mixed boron,so that a Wheatstone bridge can be formed and additional pressure can be measured.The experimental results show that when the thickness of the squared silicon membrane is 75μm and the constant voltage power supply of the nano-polysilicon thin film pressure sensor is 5.0V,the full range (160kPa) output is 24.235mV,the sensitivity is 0.151mV/kPa,the precision is 0.59%F.S,and the coefficient of zero temperature and sensitivity temperature are -0.124 and -0.108%/℃,respectively.

A novel MEMS/CMOS compatible gas sensor based on spectroscopy analysis,which is fabricated on a (110) silicon wafer,is proposed.Its main principle,structure,and fabrications are introduced in detail.The gas sensor gains high sensitivity and selectivity but has low power consumption,and it should detect the grads of gas concentration for the mentioned advantages.

A third-order low-power ΣΔ modulator for a high-end 18bit audio-band analog-to-digital converter is developed.The modulator is based on a 2-1 cascaded architecture with optimized coefficients to extend the dynamic range and reduce the spectrum tones.The gate-source bootstrapping technique is employed to enhance the sampling switch linearity.A power-efficient class A/AB operational transconductance amplifier (OTA) is proposed,which achieves a high slew rate of 100V/μs with only 0.8mA current consumption.The OTA designed for the second and third integrators is a scaled version of the first OTA,which allows for further power reduction.The modulator is implemented in SMIC mixed-signal 0.18μm CMOS technology,and the area is 1.1mm × 1.0mm.Experimental results indicate a peak signal-to-noise-and-distortion ratio (SNDR) of 91dB and a dynamic range of 94dB over a 22.05kHz bandwidth.The chip operates under a 3.3V power supply with a power dissipation of 6.8mW,which is suitable for high-performance,low-power audio ADC applications.

In order to improve the accuracy of the output voltage of a LDO,which consumes low quiescent current,a novel dual active compensation technique is used to design a LDO.It can produce two system zeros varying from load current to cancel the negative effect of the pole at different loads on the system’s stability.Compared with traditional compensation,the dual active compensation does not consume current.The quiescent current of the proposed LDO is less than 1μA,and the fold back current limit reduces the power consumption of the chip.A low quiescent current LDO employing the dual active compensation technique is implemented in a Hynix 0.5μm CMOS process.The dropout voltage is 150mV when the load current is 300mA,the line regulation is 2mV/V,and the load regulation is 0.75%,indicating that the circuit works well and effectively.

The speed and delay of flip-flops are critical to the performance of digital circuit systems.Two novel structures for dual-edge triggered explicit-pulsed flip-flops are proposed in this paper.The charging and discharging times are greatly reduced due to the lower capacitance of the interval nodes in the new structures,and the short circuit power consumption is diminished by overcoming the race problem as well.The flip-flops are also superior to the structures reported in the literature in terms of both power dissipation and working speed.

Following the trend of integration in current-mode buck regulators,a soft-start circuit integrated on-chip is presented.A narrow pulse signal is generated by an oscillator.To get the ramp voltage,the on-chip capacitor is charged by a small constant current source with intervals.A multiplex comparator with low power dissipation is designed skillfully to limit the peak current,avoiding the inrush current and achieving soft-start.The presented circuit,which is concise and simple to implement,reduces the pin number and saves PCB space.A DC-DC buck converter with the proposed structure has been fabricated in a 0.5μm CMOS process for validation.The measured result shows that the chip starts up successfully in 140μs with 3.6V input,1.8V output,and 600mA load current.