The influence of substrate temperature and nozzle-to-substrate distance (NSD) on the structural, morphological, optical and electrical properties of Sb:SnO₂ thin films prepared by chemical spray pyrolysis has been analyzed. The structural, morphological, optical and electrical properties were characterized by using XRD, SEM, UV-visible spectrophotometry and Hall effect measurement techniques. It was seen that the films are polycrystalline, having a tetragonal crystal structure with strong orientation along the (200) reflection. The pyramidal crystallites formed due to coalescence were observed from SEM images. The values of highest conductivity, optical transmittance and figure of merit of about 1449 (Ω·cm)^-1, 70 % and 5.2 × 10^-3 □/Ω, respectively, were observed for a typical film deposited using optimal conditions (substrate temperature D 500 ℃ and NSD D 30 cm).

The calculation results of the surface plasmon (SP) energy and Purcell factor of ZnO/NiSi₂ demonstrate the possibility of using NiSi₂ to enhance the UV emission of ZnO by SP coupling. Experimentally, ZnO films were deposited on NiSi₂ layers synthesized by ion implantation, and the roughness of the NiSi₂ layers spans a large range from 3 to 38 nm, providing favorable conditions for investigating SP-mediated emission. An 11-fold emission enhancement from the ZnO film on the roughest NiSi₂ layer was obtained, which indicates the possibility that metal silicide layers can be used both as an electrical contact and for emission enhancement.

With ZnO nanorods doped in only one poly (vinyl alcohol) (PVA) layer, we observed different threshold voltages with reverse DC voltages for a liquid crystal cell. The length and diameter of the ZnO nanorod used in our experiment were about 180 nm and 20 nm, respectively. When the PVA layer on the anodic side was doped, the threshold voltage was larger than that of the pure cell; conversely, when the PVA layer on the cathodic side was doped, the threshold voltage was smaller than that of the pure cell. These results can be explained by the internal electric field model. We also observed a resonance phenomenon with a low frequency AC voltage.

The influence of the growth temperature, TMIn/TEGa and V/III ratio on the V-defects of InGaN/GaN multi-quantum wells (MQWs) has been investigated and discussed. When the TMIn flow increases from 180 to 200 sccm, the density of V-defects increases from 2.72 × 10¹⁸ to 5.24 × 10¹⁸ cm^-2, and the V-defect width and depth increase too. The density also increases with the growth temperature. The densities are 2.05 × 10⁸, 2.72 × 10¹⁸ and 4.23 × 10⁸ cm^-2, corresponding to a growth temperature of 748, 753 and 758 ℃ respectively. When the NH₃ flows are 5000, 6600 and 8000 sccm, the densities of the V-defects of these samples are 6.34 × 10¹⁸, 2.72 × 10¹⁸ and 4.13 × 10¹⁸ cm^-2, respectively. A proper V/III ratio is needed to achieve step flow growth mode. We get the best quality of \,InGaN/GaN MQWs at a growth temperature of 753 ℃ TMIn flow at 180 sccm, NH₃ flow at 6600 sccm, a flatter surface and less V-defects density. The depths of these V-defects are from 10 to 30 nm, and the widths are from 100 to 200 nm. In order to suppress the influence of V-defects on reverse current and electro-static discharge of LEDs, it is essential to grow thicker p-GaN to fill the V-defects.

2 μm InGaSb/AlGaAsSb strained quantum wells and a tellurium-doped GaSb buffer layer were grown by molecular beam epitaxy (MBE). The growth parameters of strained quantum wells were optimized by AFM, XRD and PL at 77 K. The optimal growth temperature of quantum wells is 440 ℃. The PL peak wavelength of quantum wells at 300 K is 1.98 μm, and the FWHM is 115 nm. Tellurium-doped GaSb buffer layers were optimized by Hall measurement. The optimal doping concentration is 1.127 × 10¹⁸ cm^-3 and the resistivity is 5.295 × 10^-3 Ω·cm.

Low-k interconnection is one of the key concepts in the development of high-speed ultra-large-scale integrated (ULSI) circuits. To determine the Young’s modulus of ultra thin, low hardness and fragile low-k porous films more accurately, a wideband differential confocal configured laser detected and laser-generated surface acoustic wave (DCC/LD LSAW) detection system is developed. Based on the light deflection sensitivity detection principle, with a novel differential confocal configuration, this DCC/LD LSAW system extends the traditional laser generated surface acoustic wave (LSAW) detection system’s working frequency band, making the detected SAW signals less affected by the hard substrate and providing more information about the thin porous low-k film under test. Thus it has the ability to obtain more accurate measurement results. Its detecting principle is explained and a sample of porous silica film on Si (100) is tested. A procedure of fitting an experimental SAW dispersion curve with theoretical dispersion curves was carried out in the high frequency band newly achieved by the DCC/LD LSAW system. A comparison of the measurement results of the DCC/LD LSAW with those from the traditional LSAW shows that this newly developed DCC/LD LSAW can dramatically improve the Young’s modulus measuring accuracy of such porous low-k films.

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs. Different short channel field effects, such as fringing fields, junction-induced lateral fields and substrate fields, are carefully investigated, and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model. Through analytical model-based simulation, the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations. Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model. The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET. The short channel effects are found to be reduced in an SON, thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope. This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.

Based on current voltage (I-V_g) and capacitance voltage (C-V_g) measurements, a reliable procedure is proposed to determine the effective surface potential V_d.V_g/ in Schottky diodes. In the framework of thermionic emission, our analysis includes both the effect of the series resistance and the ideality factor, even voltage dependent. This technique is applied to n-type indium phosphide (n-InP) Schottky diodes with and without an interfacial layer and allows us to provide an interpretation of the observed peak on the C-V_g measurements. The study clearly shows that the depletion width and the flat band barrier height deduced from C-V_g, which are important parameters directly related to the surface potential in the semiconductor, should be estimated within our approach to obtain more reliable information.

Electrostatic discharge (ESD) phenomena involve both electrical and thermal effects, and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability. Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors (BJTs) under ESD conditions has been investigated theoretically and experimentally. 100 samples have been tested for multiple pulses until a failure occurred. Meanwhile, the distributions of electric field, current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici. There is a good agreement between the simulated results and failure analysis. In the case of a thermal couple, the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects. The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure. When the ESD level increased to 1.3 kV, the collector-base junction has been burnt out first. The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic. In addition, fatigue phenomena are observed during ESD testing, with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.

An ultra-low specific on-resistance (R_on,sp) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R_on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). A BV of 93 V and a R_on,sp of 51.8 mΩ·mm² is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R_on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively.

A low-voltage triggering silicon-controlled rectifier (LVTSCR), for its high efficiency and low parasitic parameters, has many advantages in ESD protection, especially in ultra-deep sub-micron (UDSM) IC and high frequency applications. In this paper, the impact factors of the snapback characteristics of a LVTSCR and the configuring modes are analyzed and evaluated in detail. These parameters include anode series resistance, gate voltage, structure and size of devices. In addition, a double-trench LVTSCR is presented that can increase the hold-on voltage effectively and offers easy adjustment. Also, its snapback characteristics can obey the ESD design window rule very well. The strategy of ESD protection in a RFIC using a LVTSCR is discussed at the end of the paper.

We present the design and optimization of evanescently coupled waveguide photodiodes (EC-WPDs) based on the coupling modes theory and the beam propagation method. Efficient focalization of the optical power in the absorber is achieved by an appropriate choice of index matching layers of EC-WPDs. Numerical simulation shows that high-speed (40 GHz), high quantum efficiency (81%) and high linearity photodiodes can be achieved, and EC-WPDs are promising devices for future optical communication systems.

Double-pass forward and double-pass backward erbium-doped super-fluorescent fiber sources (EDSFSs) were combined in one configuration. A 980 nm laser diode pumped the same erbium-doped fiber from both directions using a coupler as a power splitter. The double-pass configuration was achieved by coating the fiber end face. Firstly, an optimal fiber length was found to obtain a high stability of output light wavelength with pump power, and then 1530/1550 nm wavelength division multiplexing was used for spectrum planarization, which expanded the bandwidth to more than 22 nm. The final step was a test of temperature stability. The results show that the rate of the central wavelength change kept to below 3.5 ppm/℃ in the range of -40 to 60 ℃ and 1-2 ppm/℃ in the range of 20-30 ℃. Considering all the three factors of the fiber optic gyro applications, we selected 80 mA as the pump current, in which case the central wavelength temperature instability was calculated as 2.70 ppm/℃, 3 dB bandwidth 22.85 nm, spectral flatness 0.2 dB, output power 5.17 mW and power efficiency up to 9.92%. This experimental result has a significant reference value to the selection of devices and proper design of ED-SFSs for the application of high-precision fiber optic gyroscopes.

A simple method of balun synthesis is proposed to estimate the balun structure in the operating frequency band. Then, a careful optimization is implemented to evaluate the estimated structure by a series of EM simulations. In order to investigate the impact of the patterned floating shield (PFS), the optimized baluns with and without PFS are fabricated in a 65 nm 1P6M CMOS process. The measurement results demonstrate that the PFS obviously improves the insertion loss (IL) in the frequency range and a linear improving trend appears smoothly. It is also found that the PFS gradually improves the phase balance as the frequency increases, while it has a very slight influence on the magnitude balance. To characterize the device's intrinsic power transfer ability, we propose a method to obtain the baluns' maximum available gain directly from the measured 3-port S-parameters and find that IL-comparison may not be very objective when evaluating the shielding effect. We also use the resistive coupling efficiency to characterize the shielding effect, and an imbalanced shielding efficiency is found though the PFS is perfectly symmetric in the measurement. It can be demonstrated that this phenomenon comes from the intrinsic imbalance of our balun layout.

This paper presents a new micro electromagnetic energy harvester that can convert transverse vibration energy to electrical power. It mainly consists of folded beams, a permanent magnet and copper planar coils. The calculated value of the natural frequency is 274 Hz and electromagnetic simulation shows that the magnetic flux density will decrease sharply with increasing space between the magnet and coils. A prototype has been fabricated using MEMS micromachining technology. The testing results show that at the resonant frequency of 242 Hz, the prototype can generate 0.55 μW of maximal output power with peak-peak voltage of 28 mV for 0.5g (g = 9.8 m/s²⁾ external acceleration.

Double-spindle triple-workstation (DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter (≥qslant 300 mm) silicon wafers for integrated circuits. It is important, but insufficiently studied, to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables. In this paper, the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed. A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed. Based on the proposed configuration, an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward. The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived. The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

A digitally controlled oscillator (DCO) using a three-transistor XOR gate as the variable load has been presented. A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-, five- and seven-stage DCO circuits have been designed using the proposed delay cell. The output frequency is controlled digitally with bits applied to the delay cells. The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW, respectively, with a change in the control word 111-000. The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW, respectively, with a change in the control word 11111-00000. Moreover, the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW, respectively, with a varying control word 1111111-0000000. The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

A novel lumped electro-absorption modulator with a charge layer and an undercut ridge waveguide (DU-EAM) was fabricated and measured. Also, two other kinds of \,EAM with straight ridge waveguides, one with a charge layer (D-EAM) and another with no charge layer (N-EAM), were fabricated and tested to ensure that the design of the DU-EAM would reduce the RC-time constant. The measured capacitance of the D-EAM and the DU-EAM is lower than that of the N-EAM under reverse bias voltage from -1 to -8 V due to the inserted charge layer. The capacitances of the N-EAM, the D-EAM and the DU-EAM are 0.375, 0.225 and 0.325 pF, respectively, at -3 V. In addition, the DU-EAM had a larger extinction ratio (25 dB at -3 V) and higher modulation efficiency (13 dB/V between -1 and -2 V) than two other straight-ridge-waveguide ones (the D-EAM performed 22 dB and 10 dB/V, the N-EAM performed 20 dB and 10 dB/V) due to the 5.2 μm wider active region.

A 3.125-Gb/s transimpedance amplifier (TIA) for an optical communication system is realized in 0.35 μm CMOS technology. The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point. In addition, noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩ and -3 dB bandwidth of 2.31 GHz. The measured average input referred noise current spectral density is about 18.8 pA/√Hz. The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS. Under a single 3.3-V supply voltage, the TIA consumes only 58.08 mW, including 20 mW from the output buffer. The whole die area is 465 × 435 μm².

A new optimization method of a source inductive degenerated low noise amplifier (LNA) with electrostatic discharge protection is proposed. It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given. Based on the developed method, a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.69 dB, a power gain of 15.2 dB, an input 1 dB compression point of -8 dBm and an input third-order intercept point of 1 dBm. The DC current is 4 mA under a supply of 1.8 V.

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers. A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor. The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) ΔΣ modulator with noise-shaped dithering techniques. Measurement results show that in all channels, phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz. The integrated RMS phase error is no more than 0.8°. The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm².

This paper presents a fully integrated RF front-end with an automatic gain control (AGC) scheme and a digitally controlled radio frequency varied gain amplifier (RFVGA) for a U/V band China Mobile Multimedia Broadcasting (CMMB) direct conversion receiver. The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal, which is of importance for CMMB application. The front-end, composed of a low noise amplifier (LNA), an RFVGA, a mixer and AGC, achieves an input referred 3rd order intercept point (IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode, and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode. The proposed RF front-end is fabricated in a 0.35 μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed. The proposed VGA uses the differential-ramp based technique; a digitally programmable gain amplifier (PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57 dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated using SMIC 0.13 μm CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm² of chip area including bondpads. In addition, the DCOC circuit shows 500 Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.

We present a monolithic ultraviolet (UV) image sensor based on a standard CMOS process. A compact UV sensitive device structure is designed as a pixel for the image sensor. This UV image sensor consists of a CMOS pixel array, high-voltage switches, a readout circuit and a digital control circuit. A 16 × 16 image sensor prototype chip is implemented in a 0.18 μm standard CMOS logic process. The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm²⁾ and can capture a UV image. It is suitable for large-scale monolithic bio-medical and space applications.

A fast-locking all-digital delay-locked loop (ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array (FPGA). The ADDLL performs a 90° phase-shift so that the data strobe (DQS) can enlarge the data valid window in order to minimize skew. In order to further reduce the locking time and to prevent the harmonic locking problem, a time-to-digital converter (TDC) is proposed. A duty cycle corrector (DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%. The ADDLL, implemented in a commercial 0.13 μm CMOS process, occupies a total of 0.017 mm² of active area. Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps. The time interval error (TIE) of the proposed circuit is 60.7 ps.

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.

A layout-pattern-dependent electroplating model is developed based on the physical mechanism of the electroplating process. Our proposed electroplating model has an advantage over former ones due to a consideration of the variation of copper deposition rate with different layout parameters during the process. The simulation results compared with silicon data demonstrate the improvement in accuracy.