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Volume 31, Issue 3, Mar 2010

    SEMICONDUCTOR PHYSICS

  • First-principle study on anatase TiO2 codoped with nitrogen and ytterbium

    Gao Pan, Zhang Xuejun, Zhou Wenfang, Wu Jing, Liu Qingju

    J. Semicond.  2010, 31(3): 032001

    doi: 10.1088/1674-4926/31/3/032001

    Abstract PDF Get Citation

    Crystal structures, electronic structures and optical properties of nitrogen and ytterbium doping anatase TiO2 were calculated by first principles with the plane-wave ultrasoft pseudopotential method based on the density functional theory. The calculated results show that the octahedral dipole moments in TiO2 increase due to the changes in lattice parameters, bond length and charges on atoms, which is very effective for the separation of photoexcited electron-hole pairs and the improvement of the photocatalytic activity of TiO2. The interband transition between OPπ states and Yb4f states make nitrogen and ytterbium doped TiO2 manifest greater absorption coefficients in the visible-light region.

  • Tunnelling piezoresistive effect of grain boundary in polysilicon nano-films

    Chuai Rongyan, Liu Bin, Liu Xiaowei, Sun Xianlong, Shi Changzhi, Yang Lijian

    J. Semicond.  2010, 31(3): 032002

    doi: 10.1088/1674-4926/31/3/032002

    Abstract PDF Get Citation

    The experiment results indicate that the gauge factor of highly boron doped polysilicon nanofilm is bigger than that of monocrystalline silicon with the same doping concentration, and increases with the grain size decreasing. To apply the unique properties reasonably in the fabrication of piezoresistive devices, it was expounded based on the analysis of energy band structure that the properties were caused by the tunnel current which varies with the strain change forming a tunnelling piezoresistive effect. Finally, a calculation method of piezoresistance coefficients around grain boundaries was presented, and then the experiment results of polysilicon nanofilms were explained theoretically.

  • Grain boundary layer behavior in ZnO/Si heterostructure

    Liu Bingce, Liu Cihui, Yi Bo

    J. Semicond.  2010, 31(3): 032003

    doi: 10.1088/1674-4926/31/3/032003

    Abstract PDF Get Citation

    The grain boundary layer behavior in ZnO/Si heterostucture is investigated. The current–voltage (I –V ) curves, deep level transient spectra (DLTS) and capacitance–voltage (C–V ) curves are measured. The transport currents of ZnO/Si heterojunction are dominated by grain boundary layer as high densities of interfacial states existed. The interesting phenomenon that the crossing of lnI – V curves of ZnO/Si heterojunction at various measurement temperatures and the decrease of its effective barrier height with the decrement of temperature are in contradiction with the ideal heterojunction thermal emission model is observed. The details will be discussed in the following.

  • Fluid model of inductively coupled plasma etcher based on COMSOL

    Cheng Jia, Ji Linhong, Zhu Yu, Shi Yixiang

    J. Semicond.  2010, 31(3): 032004

    doi: 10.1088/1674-4926/31/3/032004

    Abstract PDF Get Citation

    Fluid dynamic models are generally appropriate for the investigation of inductively coupled plasmas. A commercial ICP etcher filled with argon plasma is simulated in this study. The simulation is based on a multiphysical software, COMSOLTM, which is a partial differential equation solver. Just as with other plasma fluid models, there are drift–diffusion approximations for ions, the quasi-neutrality assumption for electrons movements, reduced Maxwell equations for electromagnetic fields, electron energy equations for electron temperatures and the Navier–Stokes equation for neutral background gas. The two-dimensional distribution of plasma parameters are shown at 200 W of power and 1.33 Pa (10 mTorr) of pressure. Then the profile comparison of the electron number density and temperature with respect to power is illustrated. Finally we believe that there might be some disagreement between the predicted values and the real ones, and the reasons for this difference would be the Maxwellian eedf assumption and the lack of the cross sections of collisions and the reaction rates.

  • SEMICONDUCTOR MATERIALS

  • Synthesis and optical properties of nanostructured Ce(OH)4

    Ansari A A, Kaushik A

    J. Semicond.  2010, 31(3): 033001

    doi: 10.1088/1674-4926/31/3/033001

    Abstract PDF Get Citation

    Nanocrystalline cerium hydroxide (NCs-Ce(OH)4) is a intermediate product of CeO2, synthesized successfully using a novel and simple wet chemical rout at an ambient temperature for the preparation of NCs CeO2 powder and film on mass scale for various purposes. The synthesized NCs-Ce(OH)4 was characterized using X-ray diffraction (XRD), scanning electron microscopy (SEM), thermo-gravimetric analysis (TGA), Fourier transform infrared (FTIR), UV-visible and photoluminescence (PL) spectroscopy. The average crystallite size of NCs-Ce(OH)4 has been estimated by the Scherrer equation to be 3–4 nm. The SEM examinations show that the surface texture was uniformly agglomerated and homogeneous. Thermal analysis suggests that cerium (IV) ion is in the tetra hydrated form. Absorption and luminescence spectroscopic studies have been examined for future application in the development of optical devices.

  • White light photoluminescence from ZnS films on porous Si substrates

    Wang Caifeng, Li Qingshan, Hu Bo, Li Weibing

    J. Semicond.  2010, 31(3): 033002

    doi: 10.1088/1674-4926/31/3/033002

    Abstract PDF Get Citation

    ZnS films were deposited on porous Si (PS) substrates using a pulsed laser deposition (PLD) technique. White light emission is observed in photoluminescence (PL) spectra, and the white light is the combination of blue and green emission from ZnS and red emission from PS. The white PL spectra are broad, intense in a visible band ranging from 450 to 700 nm. The effects of the excitation wavelength, growth temperature of ZnS films, PS porosity and annealing temperature on the PL spectra of ZnS/PS were also investigated.

  • Characteristics of GaN grown on 6H-SiC with different AlN buffers

    Ding Guojian, Guo Liwei, Xing Zhigang, Chen Yao, Xu Peiqiang, Jia Haiqiang, Zhou Junming, Chen Hong

    J. Semicond.  2010, 31(3): 033003

    doi: 10.1088/1674-4926/31/3/033003

    Abstract PDF Get Citation

    Characteristics of GaN grown on 6H-SiC (0001) substrates using different thicknesses of AlN buffers are studied. It is found that the surface morphology and crystal quality of GaN film closely depends on the strain state of the AlN buffer. For a thicker AlN buffer, there are cracks on GaN surface, which make the GaN films unsuitable for applications. While for a thinner AlN buffer, more dislocations are produced in the GaN film, which deteriorates the performance of GaN. Possible generation mechanisms of cracks and more dislocations are investigated and a 100 nm AlN buffer is suggested to be a better choice for high quality GaN on SiC.

  • SEMICONDUCTOR DEVICES

  • High performance AlGaN/GaN HEMTs with 2.4 μm source–drain spacing

    Wang Dongfang, Wei Ke, Yuan Tingting, Liu Xinyu

    J. Semicond.  2010, 31(3): 034001

    doi: 10.1088/1674-4926/31/3/034001

    Abstract PDF Get Citation

    This paper describes the performance of AlGaN/GaN HEMTs with 2.4 μm source–drain spacing. So far these are the smallest source–drain spacing AlGaN/GaN HEMTs which have been implemented with a domestic wafer and domestic process. This paper also compares their performance with that of 4 μm source–drain spacing devices. The former exhibit higher drain current, higher gain, and higher efficiency. It is especially significant that the maximum frequency of oscillation noticeably increased.

  • Insulated gate bipolar transistor with trench gate structure of accumulation channel

    Qian Mengliang, Li Zehong, Zhang Bo, Li Zhaoji

    J. Semicond.  2010, 31(3): 034002

    doi: 10.1088/1674-4926/31/3/034002

    Abstract PDF Get Citation

    An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simulation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K, respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.

  • Impact of doped boron concentration in emitter on high- and low-dose-rate damage in lateral PNP transistors

    Zheng Yuzhan, Lu Wu, Ren Diyuan, Wang Yiyuan, Wang Zhikuan, Yang Yonghui

    J. Semicond.  2010, 31(3): 034003

    doi: 10.1088/1674-4926/31/3/034003

    Abstract PDF Get Citation

    The characteristics of radiation damage under high or low dose rate in lateral PNP transistors with heavily or lightly doped emitter is investigated in this article. Experimental results show that as total dose increases, the base current of transistors would increase and current gain decreases. Furthermore, more degradation has been found in lightly-doped PNP transistors, and an abnormal effect is observed in heavily doped transistors. The role of radiation defects especially the double effects of oxide trapped charge is discussed in heavily or lightly doped transistors. Finally, through comparison between high- and low-dose-rate response of collector current (IC) in heavily doped LPNP transistors, the abnormal effect can be attribute to the annealing of oxide trapped charge. the response of collector current, IC, in heavily doped PNP transistors under high- and low-dose-rate irradiation is described in detail.

  • Threshold voltage adjustment of organic thin film transistor by introducing a polysilicon floating gate

    Wu Chenglong, Yang Jianhong, Cai Xueyuan, Shan Xiaofeng

    J. Semicond.  2010, 31(3): 034004

    doi: 10.1088/1674-4926/31/3/034004

    Abstract PDF Get Citation

    The structure of organic thin film transistors (OTFTs) is optimized by introducing a floating gate into the gate dielectric to reduce the threshold voltage of OTFTs. Then the optimized device is simulated, and the simulation results show that the threshold voltage of optimized device is reduced by about 10 V. The reduction of the threshold voltage is helpful and useful for the application of OTFTs in many areas. In addition, this way of reducing the threshold voltage of OTFT is compatible with traditional silicon technology and can be used in manufacturing.

  • A new static induction thyristor with high forward blocking voltage and excellent switching performances

    Zhang Caizhen, Wang Yongshun, Liu Chunjuan, Wang Zaixing

    J. Semicond.  2010, 31(3): 034005

    doi: 10.1088/1674-4926/31/3/034005

    Abstract PDF Get Citation

    A new static induction thyristor (SITH) with a strip anode region and p- buffer layer structure (SAP-B) has been successfully designed and fabricated. This structure is composed of a p- buffer layer and lightly doped n- regions embedded in the p+-emitter. Compared with the conventional structure of a buried-gate with a diffused source region (DSR buried-gate), besides the simple fabrication process, the forward blocking voltage of this SITH has been increased to 1600 V from the previous value of 1000 V, the blocking gain increased from 40 to 70, and the turn-off time decreased from 0.8 to 0.4 μs.

  • Light-current characteristics of vertical-cavity surface-emitting lasers with external optical feedback

    Zhang Xing, Ning Yongqiang, Sun Yanfang, Zhang Yan, Liu Guangyu, Peng Hangyu, Li Zaijin, Qin Li, Liu Yun, Wang Lijun

    J. Semicond.  2010, 31(3): 034006

    doi: 10.1088/1674-4926/31/3/034006

    Abstract PDF Get Citation

    The influence of external optical feedback (OFB) on the light-current characteristics of the vertical-cavity surface-emitting lasers (VCSELs) was investigated theoretically and experimentally. By calculating the OFB sensitivity parameter, the OFB sensibility of the VCSELs was compared with the edge emitting lasers’ (EELs). Based on the compound cavity theory, the light-current characteristics parameters of the VCSELs with external OFB, such as the threshold current and the slope efficiency, were calculated. The results of the experimental investigation indicated that the threshold current of the VCSELs with different DBR reflectivity decreased on different degrees, accompanied with a decrease of slope efficiency when under 10% feedback ratio of the external OFB, which is in good agreement with the theoretical calculation.

  • High contrast ratio, high uniformity multiple quantum well spatial light modulators

    Huang Yuyang, Liu H C, Wasilewski Z, Buchanan M, Laframboise S R, Yang Chen, Cui Guoxin, Bian Lifeng, Yang Hui, Zhang Yaohui

    J. Semicond.  2010, 31(3): 034007

    doi: 10.1088/1674-4926/31/3/034007

    Abstract PDF Get Citation

    Our latest research results on GaAs–AlGaAs multiple quantum well spatial light modulators are presented. The thickness uniformity of the epitaxial layers across the 3-inch wafer grown by our molecular beam epitaxy is better than 0.1% and the variation of cavity resonance wavelength within the wafer is only 0.9 nm. A contrast ratio (CR) of 102 by varying bias voltage from 0 to 6.7 V is achieved after fine tuning the cavity by etching an adjust layer. Both theoretical and experimental results demonstrate that incorporating an adjust layer is an effective tuning method for obtaining high CR.

  • Tapered quantum cascade lasers operating at 9.0 μm

    Gao Yu, Liu Fengqi, Liu Junqi, Li Lu, Wang Lijun, Wang Zhanguo

    J. Semicond.  2010, 31(3): 034008

    doi: 10.1088/1674-4926/31/3/034008

    Abstract PDF Get Citation

    The tapered quantum cascade lasers operating at about 9.0 μm are reported. In contrast to the common ridge waveguide laser, tapered devices give rather small horizontal beam divergence. Performances of devices with identical 11 μm ridge waveguide sections and different tapered gain sections are comparatively studied. The optimal taper angle of 3° leads to a relative high output power and a very small horizontal beam divergence of 7.1°.

  • SEMICONDUCTOR INTEGRATED CIRCUITS

  • A 4 W K-band GaAs MMIC power amplifier with 22 dB gain

    Huang Zhengliang, Yu Faxin, Zheng Yao

    J. Semicond.  2010, 31(3): 035001

    doi: 10.1088/1674-4926/31/3/035001

    Abstract PDF Get Citation

    A 4 W K-band AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) high power amplifier (PA) is reported. This amplifier is designed to fully match for a 50 Ω input and output impedance based on the 0.15 μm power PHEMT process. Under the condition of 5.6 V and 2.6 A DC bias, the amplifier has achieved a 22 dB small-signal gain, better than a 13 dB input return loss, and 36 dBm saturation power with 25% PAE from 19 to 22 GHz.

  • A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

    Guo Shita, Huang Lu, Yuan Haiquan, Feng Lisong, Liu Zhiming

    J. Semicond.  2010, 31(3): 035002

    doi: 10.1088/1674-4926/31/3/035002

    Abstract PDF Get Citation

    This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18 μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order Σ–Δ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is –116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than –60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.

  • A wideband frequency synthesizer for a receiver application at multiple frequencies

    Wang Xiaosong, Huang Shuilong, Chen Pufeng, Lei Mumin, Li Zhiqiang, Zhang Haiying

    J. Semicond.  2010, 31(3): 035003

    doi: 10.1088/1674-4926/31/3/035003

    Abstract PDF Get Citation

    An integer-N frequency synthesizer for a receiver application at multiple frequencies was implemented in 0.18 μm 1P6M CMOS technology. The synthesizer generates 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz local signals for the receiver. A wide-range voltage-controlled oscillator (VCO) based on a reconfigurable LC tank with a binary weighted switched capacitor array and a switched inductor array is employed to cover the desired frequencies with a sufficient margin. The measured tuning range of the VCO is from 1.76 to 2.59 GHz. From the carriers of 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz, the measured phase noises are –122.13 dBc/Hz, –122.19 dBc/Hz, –121.8 dBc/Hz and –121.05 dBc/Hz, at 1 MHz offset, respectively. Their in-band phase noises are –80.09 dBc/Hz, –80.29 dBc/Hz, –83.05 dBc/Hz and –86.38 dBc/Hz, respectively. The frequency synthesizer including buffers consumes a total power of 70 mW from a 2 V power supply. The chip size is 1.5×1 mm2.

  • A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

    Xiao Shimao, Yu Yunfeng, Ma Chengyan, Ye Tianchun, Yin Ming

    J. Semicond.  2010, 31(3): 035004

    doi: 10.1088/1674-4926/31/3/035004

    Abstract PDF Get Citation

    The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than –95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

  • A millimeter-wave monolithic doubly balanced diode mixer

    Li Qin, Wang Zhigong, Xu Leijun

    J. Semicond.  2010, 31(3): 035005

    doi: 10.1088/1674-4926/31/3/035005

    Abstract PDF Get Citation

    A broadband miniature doubly balanced diode mixer chip fabricated by Win’s 0.15 μm pHEMT technology is presented. In order to save chip area, a four-fold modified Marchand balun is used. A coupled line U section improves the port to port isolation and provides the IF-output port. The mixer achieves a low conversion loss of 5.5 to 10.7 dB and high isolation of more than 26 dB over a 26–40 GHz RF/LO bandwidth and a DC–14 GHz IF bandwidth. The mixer’s chip size is around 0.96 mm2.

  • A low power 12-b 40-MS/s pipeline ADC

    Yin Xiumei, Wei Qi, Xu Lai, Yang Huazhong

    J. Semicond.  2010, 31(3): 035006

    doi: 10.1088/1674-4926/31/3/035006

    Abstract PDF Get Citation

    This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages, particularly, 3-bit/stage architectures are used to improve the ADC’s linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.

  • A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS

    Zhang Changchun, Wang Zhigong, Shi Si, Guo Yufeng

    J. Semicond.  2010, 31(3): 035007

    doi: 10.1088/1674-4926/31/3/035007

    Abstract PDF Get Citation

    Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-lockedclock and data recovery (CDR) circuit has been designed and fabricated in SMIC’s 0.18-μm CMOS technology. The Pottbacker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440 μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of –111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.

  • SEMICONDUCTOR TECHNOLOGY

  • Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

    Li Yongliang, Xu Qiuxia

    J. Semicond.  2010, 31(3): 036001

    doi: 10.1088/1674-4926/31/3/036001

    Abstract PDF Get Citation

    The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900 ℃ for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si–N bonds that dissolves very slowly in HF-based solutions. Existing Si–N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.

  • GaAs surface wet cleaning by a novel treatment in revolving ultrasonic atomization solution

    Li Zaijin, Hu Liming, Wang Ye, Yang Ye, Peng Hangyu, Zhang Jinlong, Qin Li, Liu Yun, Wang Lijun

    J. Semicond.  2010, 31(3): 036002

    doi: 10.1088/1674-4926/31/3/036002

    Abstract PDF Get Citation

    A novel process for the wet cleaning of GaAs surface is presented. It is designed for technological simplicity and minimum damage generated within the GaAs surface. It combines GaAs cleaning with three conditions consisting of (1) removal of thermodynamically unstable species and (2) surface oxide layers must be completely removed after thermal cleaning, and (3) a smooth surface must be provided. Revolving ultrasonic atomization technology is adopted in the cleaning process. At first impurity removal is achieved by organic solvents; second NH4OH : H2O2 : H2O = 1 : 1 : 10 solution and HCl : H2O2 : H2O = 1 : 1 : 20 solution in succession to etch a very thin GaAs layer, the goal of the step is removing metallic contaminants and forming a very thin oxidation layer on the GaAs wafer surface; NH4OH : H2O = 1 : 5 solution is used as the removed oxide layers in the end. The effectiveness of the process is demonstrated by the operation of the GaAs wafer. Characterization of the oxide composition was carried out by X-ray photoelectron spectroscopy. Metal-contamination and surface morphology was observed by a total reflection X-ray fluorescence spectroscopy and atomic force microscope. The research results show that the cleaned surface is without contamination or metal contamination. Also, the GaAs substrates surface is very smooth for epitaxial growth using the rotary ultrasonic atomization technology.

  • Influence of hydrogenation on the dark current mechanism of HgCdTe photovoltaic detectors

    Qiao Hui, Hu Weida, Ye Zhenhua, Li Xiangyang, Gong Haimei

    J. Semicond.  2010, 31(3): 036003

    doi: 10.1088/1674-4926/31/3/036003

    Abstract PDF Get Citation

    The influence of hydrogenation on the dark current mechanism of HgCdTe photovoltaic detectors is studied. The hydrogenation is achieved by exposing samples to a H2/Ar plasma atmosphere that was produced during a reactive ion etching process. A set of variable-area photomask was specially designed to evaluate the hydrogenation effect. It was found that the current–voltage characteristics were gradually improved when detectors were hydrogenated by different areas. The fitting results of experimental results at reverse bias conditions sustained that the improvement of current–voltage curves was due to the suppression of trap assisted tunneling current and the enhancement of minority lifetime in the depletion region. It was also found that the dominative forward current was gradually converted from a generation–recombination current to a diffusion current with the enlargement of the hydrogenation area, which was infered from the ideality factors by abstraction of forward resistance–voltage curves of different detectors.

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