Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

The absence of large-size gallium nitride (GaN) substrates with low dislocation density remains a primary bottleneck for advancing GaN-based devices. Here, we demonstrate the achievement of 8-inch freestanding GaN substrates grown by hydride vapor phase epitaxy. Critical to this achievement is the improvement in gas-flow uniformity, which ensures exceptional thickness homogeneity and enables the crack-free growth of GaN. After laser lift-off (LLO) separation, the freestanding GaN substrate exhibits superior crystal quality, evidenced by full width at half maximum values of 68 and 54 arcsec for X-ray diffraction rocking curves of (002) and (102) planes, alongside a low dislocation density of 1.6 × 10⁶ cm⁻². This approach establishes a robust pathway for the production of large-size GaN substrates, which are essential for advancing next-generation power electronics and high-efficiency photonics.

β-Ga₂O₃ MOS inverter should play a crucial role in β-Ga₂O₃ electronic circuits. Enhancement-mode (E-mode) MOSFET was fabricated based on β-Ga₂O₃ film grown by atomic layer deposition technology, and the β-Ga₂O₃ inverter was further monolithically integrated on this basis. The β-Ga₂O₃ nMOSFET exhibits excellent electrical characteristics with an on/off current ratio reaching 10⁵. The logic inverter shows outstanding voltage inversion characteristics under low-frequency from 1 to 400 Hz operation. As the frequency continues to increase to 10 K, the reverse characteristic becomes worse due to parasitic capacitance induced by processes, and the difference between the highest and lowest values of V_OUT has an exponential decay relationship with the frequency. This paper provides the practice for the development of β-Ga₂O₃-based circuits.

The mobility degradation induced by negative bias temperature instability (NBTI) is usually ignored in traditional NBTI modeling and simulation, resulting in overestimation of the circuit lifetime, especially after long-term operation. In this paper, the mobility degradation is modeled in combination with the universal NBTI model. The coulomb scattering induced by interface states is revealed to be the dominant component responsible for mobility degradation. The proposed mobility degradation model fits the measured data well and provides an accurate solution for evaluating coupling of NBTI with HCI (hot carrier injection) and SHE (self-heating effect), which indicates that mobility degradation should be considered in long-term circuit aging simulation.

Robotic computing systems play an important role in enabling intelligent robotic tasks through intelligent algorithms and supporting hardware. In recent years, the evolution of robotic algorithms indicates a roadmap from traditional robotics to hierarchical and end-to-end models. This algorithmic advancement poses a critical challenge in achieving balanced system-wide performance. Therefore, algorithm-hardware co-design has emerged as the primary methodology, which analyzes algorithm behaviors on hardware to identify common computational properties. These properties can motivate algorithm optimization to reduce computational complexity and hardware innovation from architecture to circuit for high performance and high energy efficiency. We then reviewed recent works on robotic and embodied AI algorithms and computing hardware to demonstrate this algorithm-hardware co-design methodology. In the end, we discuss future research opportunities by answering two questions: (1) how to adapt the computing platforms to the rapid evolution of embodied AI algorithms, and (2) how to transform the potential of emerging hardware innovations into end-to-end inference improvements.

The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control circuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-, double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Meanwhile, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.