Spin-orbit torque (SOT) is widely considered as the key technology for next-generation magnetic random-access memory (MRAM), leveraging ultrafast operating speed and unlimited endurance. However, integrating perpendicular magnetic anisotropy (PMA) SOT-MRAM stacks with the back-end-of-line (BEOL) thermal budget remains a critical challenge, as PMA degradation and Pt-Fe interdiffusion typically occur under 400 °C annealing. Here we propose a double CoFeB reference layer (DCFB) structure to address these issues. The additional CoFeB reference layer and two extra CoFeB/W interfaces significantly enhance the PMA of the reference layers, while improving the crystallization of the overlying Pt/Co multilayers. Furthermore, the DCFB stack effectively acts as a diffusion barrier against Pt-Fe interdiffusion. Consequently, a fabricated magnetic tunnel junction (MTJ) incorporating the DCFB stack achieves a high tunneling magnetoresistance (TMR) of 137% even after annealing at 400 °C. Our work provides a robust, simplified approach for the design of SOT-MRAM stacks with BEOL thermal budget tolerance.
Currently, the global 5G network, cloud computing, and data center industries are experiencing rapid development. The continuous growth of data center traffic has driven the vigorous progress in high-speed optical transceivers for optical interconnection within data centers. The electro-absorption modulated laser (EML), which is widely used in optical fiber communications, data centers, and high-speed data transmission systems, represents a high-performance photoelectric conversion device. Compared to traditional directly modulated lasers (DMLs), EMLs demonstrate lower frequency chirp and higher modulation bandwidth, enabling support for higher data rates and longer transmission distances. This article introduces the composition, working principles, manufacturing processes, and applications of EMLs. It reviews the progress on advanced indium phosphide (InP)-based EML devices from research institutions worldwide, while summarizing and comparing data transmission rates and key technical approaches across various studies.
A skipper image sensor (SIS) with lateral overflow gate-coupled capacitor (LOGCC) is proposed in this work. During the integration period, the transfer gates after TG are switched on to construct a LOGCC with specific operation timing. Once high light illumination fully charges the pinned photodiode (PPD), the extra photogenerated electrons will overflow to LOGCC, which effectively improve the dynamic range (DR) of SIS. Before the readout of signal in PPD, the electrons stored in LOGCC are sampled and then reset through the floating diffusion (FD). In the end, the electrons in PPD are sampled by the method of the conventional skipper pixels. According to TCAD simulation results, the extra electrons are transferred to LOGCC through the TG effectively. Measurement of prototype chip shows that the DR is extended to 89.3 dB. As contrast, the DR is 66 dB when switching off the transfer gates, i.e. LOGCC. Compared with traditional SIS, the proposed architecture achieved DR extension by introducing LOGCC which is constructed with transfer gates. Therefore, this study proposes the introduction of LOGCC to expand the application scenarios of SIS, providing a new approach for its use in conditions requiring stronger light.
Achieving high emission efficiency at low current densities remains a challenge for micro-LEDs. Here, we demonstrate a controllable interfacial strategy by tuning the annealing temperature of RF-superimposed DC sputtered ITO to modulate carrier injection dynamics. STEM analysis reveals 500 °C annealing triggers discrete substitutional In-atom incorporation into the p-GaN lattice, forming localized nanoscale contact regions. This architecture induces a localized carrier injection mechanism that significantly enhances the efficiency of micro-LEDs at low current densities. Specifically, the 500 °C-annealed 10 μm devices exhibit a dramatic enhancement in light output power (LOP), reaching 1.3 × 10−1 mW at 5 A/cm2, which is significantly higher than the 5.3 × 10−4 mW measured for 700 °C-annealed devices. Furthermore, the peak efficiency current density (Jpeak) is dramatically shifted from 140 to 17 A/cm2 for 5 μm devices. Capacitance-voltage analysis further corroborates the localized carrier injection mechanism. These findings establish contact interfacial modulation as a robust strategy for optimizing micro-LEDs in low-power display applications and tailoring device-level performance across broader optoelectronics.
Robotic computing systems play an important role in enabling intelligent robotic tasks through intelligent algorithms and supporting hardware. In recent years, the evolution of robotic algorithms indicates a roadmap from traditional robotics to hierarchical and end-to-end models. This algorithmic advancement poses a critical challenge in achieving balanced system-wide performance. Therefore, algorithm-hardware co-design has emerged as the primary methodology, which analyzes algorithm behaviors on hardware to identify common computational properties. These properties can motivate algorithm optimization to reduce computational complexity and hardware innovation from architecture to circuit for high performance and high energy efficiency. We then reviewed recent works on robotic and embodied AI algorithms and computing hardware to demonstrate this algorithm-hardware co-design methodology. In the end, we discuss future research opportunities by answering two questions: (1) how to adapt the computing platforms to the rapid evolution of embodied AI algorithms, and (2) how to transform the potential of emerging hardware innovations into end-to-end inference improvements.
Efficient spin injection is crucial for developing high-performance spintronic and optoelectronic devices. To address the issue of low spin injection efficiency caused by lattice mismatch and interface defects in traditional CoFeB/MgO tunnel junctions, this work proposes a strategy of using graphene as an insertion layer to optimize interface quality and enhance the spin injection efficiency of tunnel junctions. By systematically investigating three types of tunnel junction structures, namely CoFeB/MgO, CoFeB/Graphene/MgO and CoFeB/MgO/Graphene, we demonstrate that the graphene insertion layer can effectively release interface stress, reduce defects and distortions induced by lattice mismatch, and thereby suppress spin scattering. Meanwhile, it alleviates resistance mismatch while preserving high spin polarization. Ultimately, the spin injection polarization is increased from 10.6% to 16.2%, representing an enhancement of approximately 53%. Additionally, the optimized CoFeB/MgO/Graphene tunnel junction was integrated into GaN-based spin light-emitting diodes, resulting in an increased circular polarization of electroluminescence from 8.4% to 17.3%. This work provides an interface engineering strategy for achieving efficient spin injection and advancing the development of spin-optoelectronic devices.
The computational cost of TCAD simulations is becoming prohibitively high with the complexity of advanced process technologies, making simulation acceleration a critical research priority. While end-to-end surrogate models mapping process recipes to device structures and characteristics offer a promising alternative, their application is often limited by poor generalizability and explainability. In this work, we present MPNet, a modular deep learning surrogate modeling framework for process TCAD. MPNet comprises distinct surrogate models for individual process modules, which are assembled into an integrated framework. These modular models employ a novel UNet-attention feature evolution method to capture the complex evolutions of device geometry and doping profiles. Each module can be trained separately on its individual process, after which the modules are cascaded and jointly fine-tuned to minimize error accumulation throughout the cascade. The efficacy of the proposed MPNet framework is demonstrated through a MOSFET integrated process TCAD case study. Results show that MPNet achieves a computational speedup of over 103 times compared to conventional TCAD, while maintaining predictive fidelity exceeding 98%. Finally, to illustrated the application of the proposed framework, MPNet is coupled with a PSO algorithm, showcasing its utility for fast process optimization to meet specific process targets.
