Since the invention of amorphous indium–gallium–zinc–oxide (IGZO) based thin-film transistors (TFTs) by Hideo Hosono in 2004, investigations on the topic of IGZO TFTs have been rapidly expanded thanks to their high electrical performance, large-area uniformity, and low processing temperature. This article reviews the recent progress and major trends in the field of IGZO-based TFTs. After a brief introduction of the history of IGZO and the main advantages of IGZO-based TFTs, an overview of IGZO materials and IGZO-based TFTs is given. In this part, IGZO material electron travelling orbitals and deposition methods are introduced, and the specific device structures and electrical performance are also presented. Afterwards, the recent advances of IGZO-based TFT applications are summarized, including flat panel display drivers, novel sensors, and emerging neuromorphic systems. In particular, the realization of flexible electronic systems is discussed. The last part of this review consists of the conclusions and gives an outlook over the field with a prediction for the future.

The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control circuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-, double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Meanwhile, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.

Robots are widely used, providing significant convenience in daily life and production. With the rapid development of artificial intelligence and neuromorphic computing in recent years, the realization of more intelligent robots through a profound intersection of neuroscience and robotics has received much attention. Neuromorphic circuits based on memristors used to construct hardware neural networks have proved to be a promising solution of shattering traditional control limitations in the field of robot control, showcasing characteristics that enhance robot intelligence, speed, and energy efficiency. Starting with introducing the working mechanism of memristors and peripheral circuit design, this review gives a comprehensive analysis on the biomimetic information processing and biomimetic driving operations achieved through the utilization of neuromorphic circuits in brain-like control. Four hardware neural network approaches, including digital-analog hybrid circuit design, novel device structure design, multi-regulation mechanism, and crossbar array, are summarized, which can well simulate the motor decision-making mechanism, multi-information integration and parallel control of brain at the hardware level. It will be definitely conductive to promote the application of memristor-based neuromorphic circuits in areas such as intelligent robotics, artificial intelligence, and neural computing. Finally, a conclusion and future prospects are discussed.

Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

Ferroelectric hysteresis loop measurement under high driving frequency generally faces great challenges. Parasitic factors in testing circuits such as leakage current and RC delay could result in abnormal hysteresis loops with erroneous remnant polarization (P_r) and coercive field (E_c). In this study, positive-up-negative-down (PUND) measurement under a wide frequency range was performed on a 10-nm thick Hf_0.5Zr_0.5O₂ ferroelectric film. Detailed analysis on the leakage current and RC delay was conducted as the polarization switching occurs in the FE capacitor. After considering the time lag caused by RC delay, reasonable calibration of current response over the voltage pulse stimulus was employed in the integral of polarization current over time. In such a method, rational P–V loops measured at high frequencies (>1 MHz) was successfully achieved. This work provides a comprehensive understanding on the effect of parasitic factors on the polarization switching behavior of FE films.

The finding of the robust ferroelectricity in HfO₂-based thin films is fantastic from the view point of both the fundamentals and the applications. In this review article, the current research status of the future prospects for the ferroelectric HfO₂-based thin films and devices are presented from fundamentals to applications. The related issues are discussed, which include: 1) The ferroelectric characteristics observed in HfO₂-based films and devices associated with the factors of dopant, strain, interface, thickness, defect, fabrication condition, and more; 2) physical understanding on the observed ferroelectric behaviors by the density functional theory (DFT)-based theory calculations; 3) the characterizations of microscopic and macroscopic features by transmission electron microscopes-based and electrical properties-based techniques; 4) modeling and simulations, 5) the performance optimizations, and 6) the applications of some ferroelectric-based devices such as ferroelectric random access memory, ferroelectric-based field effect transistors, and the ferroelectric tunnel junction for the novel information processing systems.

CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

The high critical electric field strength of Ga₂O₃ enables higher operating voltages and reduced switching losses in power electronic devices. Suitable Schottky metals and epitaxial films are essential for further enhancing device performance. In this work, the fabrication of vertical Ga₂O₃ barrier diodes with three different barrier metals was carried out on an n^–-Ga₂O₃ homogeneous epitaxial film deposited on an n⁺-β-Ga₂O₃ substrate by metal−organic chemical vapor deposition, excluding the use of edge terminals. The ideal factor, barrier height, specific on-resistance, and breakdown voltage characteristics of all devices were investigated at room temperature. In addition, the vertical Ga₂O₃ barrier diodes achieve a higher breakdown voltage and exhibit a reverse leakage as low as 4.82 ×10⁻⁸ A/cm² by constructing a NiO/Ga₂O₃ heterojunction. Therefore, Ga₂O₃ power detailed investigations into Schottky barrier metal and NiO/Ga₂O₃ heterojunction of Ga₂O₃ homogeneous epitaxial films are of great research potential in high-efficiency, high-power, and high-reliability applications.