Impurity deionization on the direct-current current–voltage characteristics from electron–hole recombination (R-DCIV) at SiO₂/Si interface traps in MOS transistors is analyzed using the steady-state Shockley-Read-Hall recombination kinetics and the Fermi distributions for electrons and holes. Insignificant distortion is observed over 90% of the bell-shaped R-DCIV curves centered at their peaks when impurity deionization is excluded in the theory. This is due to negligible impurity deionization because of the much lower electron and hole concentrations at the interface than the impurity concentration in the 90% range.

Heteroepitaxial undoped ZnO films were grown on Si (100) substrates by radio-frequency reactive sputtering, and then some of the samples were annealed at N₂-800 ℃ (Sample 1, S1) and O₂-800 ℃ (Sample 2, S2) for 1 h, respectively. The electrical transport characteristics of a ZnO/p-Si heterojunction were investigated. We found two interesting phenomena. First, the temperature coefficients of grain boundary resistances of S1 were positive (positive temperature coefficients, PTC) while that of both the as-grown sample and S2 were negative (negative temperature coefficients, NTC). Second, the I–V properties of S2 were similar to those common p–n junctions while that of both the as-grown sample and S1 had double Schottky barrier behaviors, which were in contradiction with the ideal p–n heterojunction model. Combined with the deep level transient spectra results, this revealed that the concentrations of intrinsic defects in ZnO grains and the densities of interfacial states in ZnO/p-Si heterojunction varied with the different annealing ambiences, which caused the grain boundary barriers in ZnO/p-Si heterojunction to vary. This resulted in adjustment electrical properties of ZnO/p-Si heterojunction that may be suitable in various applications.

We study the growth of an InGaN and AlGaN/GaN/InGaN/GaN double heterojunction structure by metal organic chemical vapor deposition (MOCVD). It is found that the crystal quality of the InGaN back barrier layer significantly affects the electronic property of the AlGaN/GaN/InGaN/GaN double heterojunction. A high crystal quality InGaN layer is obtained by optimizing the growth pressure and temperature. Due to the InGaN layer polarization field opposite to that in the AlGaN layer, an additional potential barrier is formed between the GaN and the InGaN layer, which enhances carrier confinement of the 2DEG and reduces the buffer leakage current of devices. The double heterojunction high-electron-mobility transistors with an InGaN back barrier yield a drain induced barrier lowering of 1.5 mV/V and the off-sate source-drain leakage current is as low as 2.6 μA/mm at V_DS = 10 V.

The prospects of a p⁺nn⁺ cubic silicon carbide (3C-SiC/β-SiC) based IMPATT diode as a potential solid-state terahertz source is studied for the first time through a modified generalized simulation scheme. The simulation predicts that the device is capable of generating an RF power output of 63.0 W at 0.33 THz with an efficiency of 13%. The effects of parasitic series resistance on the device performance and exploitable RF power level are further simulated. The studies clearly establish the potential of 3C-SiC as a base semiconductor material for a high-power THz IMPATT device. Based on the simulation results, an attempt has been made to fabricate β-SiC based IMPATT devices in the THz region. Single crystalline, epitaxial 3C-SiC films are deposited on silicon (Si) <100> substrates by rapid thermal chemical vapour deposition (RTPCVD) at a temperature as low as 800 ℃ using a single precursor methylsilane, which contains Si and C atoms in the same molecule. No initial surface carbonization step is required in this method. A p–n junction with an n-type doping concentration of 4 × 10²⁴ m^-3 (which is similar to the simulated design data) has been grown successfully and the characterization of the grown 3C-SiC film is reported in this paper. It is found that the inclusion of Ge improves the crystal quality and reduces the surface roughness.

Analytical expressions of electron transmittance and tunneling current in an anisotropic TiN_x/HfO₂/SiO₂/p-Si(100) metal–oxide–semiconductor (MOS) capacitor were derived by considering the coupling of transverse and longitudinal energies of an electron. Exponential and Airy wavefunctions were utilized to obtain the electron transmittance and the electron tunneling current. A transfer matrix method, as a numerical approach, was used as a benchmark to assess the analytical approaches. It was found that there is a similarity in the transmittances calculated among exponential- and Airy-wavefunction approaches and the TMM at low electron energies. However, for high energies, only the transmittance calculated by using the Airy-wavefunction approach is the same as that evaluated by the TMM. It was also found that only the tunneling currents calculated by using the Airy-wavefunction approach are the same as those obtained under the TMM for a range of oxide voltages. Therefore, a better analytical description for the tunneling phenomenon in the MOS capacitor is given by the Airy-wavefunction approach. Moreover, the tunneling current density decreases as the titanium concentration of the TiN_x metal gate increases because the electron effective mass of TiN_x decreases with increasing nitrogen concentration. In addition, the mass anisotropy cannot be neglected because the tunneling currents obtained under the isotropic and anisotropic masses are very different.

The transition of the barrier-type thyristor (BTH) from blocking to conducting-state occurs between two entirely contrary physical states with great disparity in nature. The physical effects and mechanisms of the transition are studied in depth. The features of the transition snapback point are analyzed in detail. The transition snapback point has duality and is just the position where the barrier is flattened. It has a significant influence on the capture cross-section of the hole and high-level hole lifetime, resulting in the device entering into deep base conductance modulation. The physical nature of the negative differential resistance segment I–V characteristics is studied. It is testified by using experimental data that the deep conductance modulation is the basic feature and the linchpin of the transition process. The conditions and physical mechanisms of conductance modulation are investigated. The related physical subjects, including the flattening of the channel barrier, the buildup of the double injection, the formation of the plasma, the realization of the high-level injection, the elimination of the gate junction depletion region, the deep conductance modulation, and the increase in the hole's lifetime are all discussed in this paper.

The effect of negative bias temperature instability (NBTI) on a single event transient (SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.

Due to carrier band-to-band-tunneling (BTBT) through channel-source/drain contacts, conventional MOS-like Carbon Nanotube Field Effect Transistors (C-CNFETs) suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed and all kinds of source/drain contacting conditions are considered in this paper. The non-equilibrium Green's function (NEGF) formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold performance, even with source/drain contacts being of Schottky type. And these are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends strongly on the choice of tuning voltage value, which should be paid much attention to obtain a proper trade-off between power and speed in application.

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS (SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment, a TCAD simulation and a charge pumping test. For different stress conditions, degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented. Then the effect of various doses of n-type drain drift (NDD) region implant on R_on degradation is investigated. Experimental results show that a lower NDD dosage can reduce the hot-carrier induced R_on degradation effectively, which is different from uniform gate oxide NLDMOS (UG-NLDMOS) transistors.

Low voltage organic thin film transistors (OTFTs) were created using polymethyl-methacrylate-cog-lyciclyl-methacrylate (PMMA-GMA) as the gate dielectric. The OTFTs performed acceptably at supply voltages of about 10 V. From a densely packed copolymer brush, a leakage current as low as 2 × 10^-8 A/cm² was obtained. From the measured capacitance–insulator frequency characteristics, a dielectric constant in the range 3.9–5.0 was obtained. By controlling the thickness of the gate dielectric, the threshold voltage was reduced from –3.5 to –2.0 V. The copper phthalocyanine (CuPc) based organic thin film transistor could be operated at low voltage and 1.2 × 10^-3 cm²/(V.s) mobility.

This paper presents an improved analytical model for an RF-LDMOST structure based on the 2D Poisson equation. The derived model indicates the influence of high doped shallow drift and low doping concentration p epitaxial layer on the electric field distribution. In particular, the importance of the thickness of the p epitaxial layer for electric field distributions in RF-LDMOST are shown through MATLAB analytical results based on the model. Then ISE TCAD simulations and experiments are processed and their results are in agreement with the analytical model. This model contributes to the comprehension and optimization design of RF-LDMOST.

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15–20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology.

Intrinsic stability of the heterojunction bipolar transistor (HBT) was analyzed and discussed based on a small signal equivalent circuit model. The stability factor of the HBT device was derived based on a compact T-type small signal equivalent circuit model of the HBT. The effect of the mainly small signal model parameters of the HBT on the stability of the HBT was thoroughly examined. The discipline of parameter optimum to improve the intrinsic stability of the HBT was achieved. The theoretic analysis results of the stability were also used to explain the experimental results of the stability of the HBT and they were verified by the experimental results.

A novel two-step method is employed, for the first time, to fabricate nonvolatile memory devices that have metal nanocrystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concern for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method.

Using a Volterra series, an explicit formula is derived for the connection between input 3rd-order intercept point and collector bias current (I_CQ) in a common–emitter bipolar junction transistor amplifier. The analysis indicates that the larger I_CQ is, the more linear the amplifier is. Furthermore, this has been verified by experiment. This study also integrates a method called dynamic bias current for expanding the dynamic range of an LNA (low noise amplifier) as an application of the analysis result obtained above. IMR3 (3rd-order intermodulation rate) is applied to evaluate the LNA's performance with and without adopting this method in this study.

The reflectivity versus incident angle of a GaP/Au reflector, a GaP/SiO₂/Au triple ODR (omni-directional reflector) and a GaP/ITO/Au triple ODR was calculated. Compared to AlGaInP LEDs with a GaAs absorbing substrate, thin film LEDs with a Au reflector, a SiO₂ ODR and an ITO ODR were fabricated. At a current of 20 mA, the optical output power of four samples was respectively 1.04, 1.14, 2.53 and 2.15 mW. The Au diffusion in the annealing process reduces the reflectivity of the Au/GaP reflector to 9%. The different transmittance of quarter-wave thickness ITO and SiO₂ induces different optical output power between the SiO₂ and ITO thin film LEDs. The insertion of Zn in the ITO ODR LED does not affect the light output but evidently reduces the voltage.

Readout electronics, especially digital electronics, for two-element CdZnTe (CZT) detectors in parallel are developed. The preliminary results show the detection efficiency of the two-element CZT detectors in parallel with analog electronics is as many as 1.8 and 2.1 times the single ones, and the energy resolution (FWHM) is limited by that of the single one by the means of analog electronics. However, the digital method for signal processing will be sufficiently better by contrast with an analog method especially in energy resolution. The energy resolution by the means of digital electronics can be improved by about 26.67%, compared to that only with analog electronics, while their detection efficiency is almost the same. The cause for this difference is also discussed.

Design, fabrication and characterization of a novel two-color detector for ultraviolet and infrared applications are reported. The detector has a simple multilayer structure composed of n-Al_0.3Ga_0.7N/i-GaN/p-GaN/SiO₂/LaNiO₃/PZT/Pt fabricated on a sapphire substrate. Ultraviolet and infrared properties are measured. For the ultraviolet region, a flat band spectral response is achieved in the 302–363 nm band. The detector displays an unbiased responsivity of 0.064 A/W at 355 nm. The current–voltage curve shows that current at zero bias is –1.57 × 10^-12 A. This led to a detectivity of 1.81 × 10¹¹ cm . Hz^1/2/W. In the infrared region, the detectivity of the detector is 1.58 × 10⁵ cm . Hz^1/2/W at 4 μm.

The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation. A recombination process between trapped charges is an important issue on the retention of charge trapping memory. Our results show that accumulated trapped holes during P/E cycling can have an influence on retention, and the recombination mechanism between trapped charges should be taken into account when evaluating the retention capability of TANOS.

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5–1.7dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

A novel low-pass filter that consists of a switched capacitor filter (SCF) and its antialiasing prefilter and smoothing postfilter is proposed for a microsensor signal processing system, which is used in separation point detection on the surface of micro air vehicles. In the system, the filter is not only applied to finish the function of filtering but also used as the front end antialiasing filter of the over sampling analog-to-digital converter. This proposed implementation mostly relies on the design of a high-precision SCF employing a correlated double sampling technique and optimisation switches. Simultaneously, the multiple-loop feedback low pass filter with good high frequency attenuation characteristics is applied as the pre- and postfilter. The design is implemented in the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm double-poly three-metal (2P3M) 3.3 V CMOS technology, with satisfactory results. The chip die area occupies only 0.39 mm² and dissipates1.53 mW.

A monolithic low-power and low-phase-noise digitally controlled oscillator (DCO) based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18 μm cmos process with six metal layers. A third new way to change capacitance is proposed and implemented in this work. Results show that the phase noise at 1 MHz offset frequency is below –122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also, the DCO can work at low supply voltage conditions with a 1.6 V power supply and 4.1 mA supply current for the DCO's core circuit, achieving a phase-noise of –121.5 dBc/Hz at offset of 1 MHz. It demonstrates that the supply pushing of DCO is less than 10 MHz/V.

To improve the compensation for the inherent instability in a current mode converter, the adaptive slope compensation, giving attention to the problems of the traditional compensation on compensation accuracy, loading capability and turning jitter, is presented. Based on the analysis of current loop, by detecting the input and output voltage, converting the adaptive slope compensation current, the compensation of the current loop is optimized successfully. It can not only improve the compensation accuracy but also eliminate the over compensation, the turning jitter and the poor loading capability in the reported slope compensation. A power supply chip with adaptive slope compensation has been fabricated in a 0.35 μm CMOS process. The measurement results show that the chip starts up and operates steadily with the constant current limit under conditions of 5 V input voltage, from 10% to 100% duty cycle.

A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm². System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.

This paper presents an inductorless complementary-noise-canceling LNA (CNCLNA) for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5–16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best P_1dB is –7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2× 0.2 mm².

This paper presents the design and implementation of a 14-bit, 100 MS/s CMOS digital-to-analog converter (DAC). Analog background self-calibration based on the concept of analog current trimming is introduced. A constant clock load switch driver, a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance. The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33 × 0.97 mm² of the core area. The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog, respectively. The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB, respectively. The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.

Based on the Preston equation, the mathematical model of the material removal rate (MRR), aiming at a line-orbit chemical mechanical polisher, is established. The MRR and the material removal non-uniformity (MRNU) are numerically calculated by MATLAB, and the effects of the reciprocating parameters on the MRR and the MRNU are discussed. It is shown that the smaller the inclination angle and the larger the amplitude, the higher the MRR and the lower the MRNU. The reciprocating speed of the carrier plays a minor role to improve the MRR and decrease the MRNU. The results provide a guide for the design of a polisher and the determination of a process in line-orbit chemical mechanical polishing.

A signal processing method for the friction-based endpoint detection system of a chemical mechanical polishing (CMP) process is presented. The signal process method uses the wavelet threshold denoising method to reduce the noise contained in the measured original signal, extracts the Kalman filter innovation from the denoised signal as the feature signal, and judges the CMP endpoint based on the feature of the Kalman filter innovation sequence during the CMP process. Applying the signal processing method, the endpoint detection experiments of the Cu CMP process were carried out. The results show that the signal processing method can judge the endpoint of the Cu CMP process.

Spin-on-glass (SOG), an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide (SiO₂) deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO₂ and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.